Document Outline

• Cover
• Cautions
• Contents
• Section 1 Overview
  • 1.1 Overview
  • 1.2 Internal Block Diagram
  • 1.3 Pin Arrangement and Functions
    • 1.3.1 Pin Arrangement
    • 1.3.2 Pin Functions
• Section 2 CPU
  • 2.1 Overview
    • 2.1.1 Features
    • 2.1.2 Differences between H8S/2600 CPU and H8S/2000 CPU
    • 2.1.3 Differences from H8/300 CPU
    • 2.1.4 Differences from H8/300H CPU
  • 2.2 CPU Operating Modes
  • 2.3 Address Space
  • 2.4 Register Configuration
    • 2.4.1 Overview
    • 2.4.2 General Registers
    • 2.4.3 Control Registers
    • 2.4.4 Initial Register Values
  • 2.5 Data Formats
    • 2.5.1 General Register Data Formats
    • 2.5.2 Memory Data Formats
  • 2.6 Instruction Set
    • 2.6.1 Overview
    • 2.6.2 Instructions and Addressing Modes
    • 2.6.3 Table of Instructions Classified by Function
    • 2.6.4 Basic Instruction Formats
    • 2.6.5 Notes on Use of Bit-Manipulation Instructions
  • 2.7 Addressing Modes and Effective Address Calculation
    • 2.7.1 Addressing Mode
    • 2.7.2 Effective Address Calculation
  • 2.8 Processing States
    • 2.8.1 Overview
    • 2.8.2 Reset State
    • 2.8.3 Exception-Handling State
    • 2.8.4 Program Execution State
    • 2.8.5 Power-Down State
  • 2.9 Basic Timing
    • 2.9.1 Overview
    • 2.9.2 On-Chip Memory (ROM, RAM)
    • 2.9.3 On-Chip Supporting Module Access Timing
• Section 3 MCU Operating Modes
  • 3.1 Overview
    • 3.1.1 Operating Mode Selection
    • 3.1.2 Register Configuration
  • 3.2 Register Descriptions
    • 3.2.1 Mode Control Register (MDCR)
    • 3.2.2 System Control Register (SYSCR)
  • 3.3 Operating Mode (Mode 1)
  • 3.4 Address Map in Each Operating Mode
• Section 4 Power-Down State
  • 4.1 Overview
    • 4.1.1 Register Configuration
  • 4.2 Register Descriptions
    • 4.2.1 Standby Control Register (SBYCR)
    • 4.2.2 Low-Power Control Register (LPWRCR)
    • 4.2.3 Timer Register A (TMA)
    • 4.2.4 Module Stop Control Register (MSTPCR)
  • 4.3 Medium-Speed Mode
  • 4.4 Sleep Mode
    • 4.4.1 Sleep Mode
    • 4.4.2 Clearing Sleep Mode
  • 4.5 Module Stop Mode
    • 4.5.1 Module Stop Mode
  • 4.6 Standby Mode
    • 4.6.1 Standby Mode
    • 4.6.2 Clearing Standby Mode
    • 4.6.3 Setting Oscillation Settling Time after Clearing Standby Mode
  • 4.7 Watch Mode
    • 4.7.1 Watch Mode
    • 4.7.2 Clearing Watch Mode
  • 4.8 Subsleep Mode
    • 4.8.1 Subsleep Mode
    • 4.8.2 Clearing Subsleep Mode
  • 4.9 Subactive Mode
    • 4.9.1 Subactive Mode
    • 4.9.2 Clearing Subactive Mode
  • 4.10 Direct Transition
    • 4.10.1 Overview of Direct Transition
• Section 5 Exception Handling
  • 5.1 Overview
    • 5.1.1 Exception Handling Types and Priority
    • 5.1.2 Exception Handling Operation
    • 5.1.3 Exception Sources and Vector Table
  • 5.2 Reset
    • 5.2.1 Overview
    • 5.2.2 Reset Sequence
    • 5.2.3 Interrupts after Reset
  • 5.3 Interrupts
  • 5.4 Trap Instruction
  • 5.5 Stack Status after Exception Handling
  • 5.6 Notes on Use of the Stack
• Section 6 Interrupt Controller
  • 6.1 Overview
    • 6.1.1 Features
    • 6.1.2 Block Diagram
    • 6.1.3 Pin Configuration
    • 6.1.4 Register Configuration
  • 6.2 Register Descriptions
    • 6.2.1 System Control Register (SYSCR)
    • 6.2.2 Interrupt Control Registers A to D (ICRA to ICRD)
    • 6.2.3 IRQ Enable Register (IENR)
    • 6.2.4 IRQ Edge Select Registers (IEGR)
    • 6.2.5 IRQ Status Register (IRQR)
    • 6.2.6 Port Mode Register (PMR1)
  • 6.3 Interrupt Sources
    • 6.3.1 External Interrupts
    • 6.3.2 Internal Interrupts
    • 6.3.3 Interrupt Exception Vector Table
  • 6.4 Interrupt Operation
    • 6.4.1 Interrupt Control Modes and Interrupt Operation
    • 6.4.2 Interrupt Control Mode 0
    • 6.4.3 Interrupt Control Mode 1
    • 6.4.4 Interrupt Exception Handling Sequence
    • 6.4.5 Interrupt Response Times
  • 6.5 Usage Notes
    • 6.5.1 Contention between Interrupt Generation and Disabling
    • 6.5.2 Instructions that Disable Interrupts
    • 6.5.3 Interrupts during Execution of EEPMOV Instruction
• Section 7 ROM
  • 7.1 Overview
    • 7.1.1 Block Diagram
  • 7.2 Overview of Flash Memory
    • 7.2.1 Features
    • 7.2.2 Block Diagram
    • 7.2.3 Flash Memory Operating Modes
    • 7.2.4 Pin Configuration
    • 7.2.5 Register Configuration
  • 7.3 Flash Memory Register Descriptions
    • 7.3.1 Flash Memory Control Register 1 (FLMCR1)
    • 7.3.2 Flash Memory Control Register 2 (FLMCR2)
    • 7.3.3 Erase Block Register 1 (EBR1)
    • 7.3.4 Erase Block Register 2 (EBR2)
    • 7.3.5 Serial/Timer Control Register (STCR)
  • 7.4 On-Board Programming Modes
    • 7.4.1 Boot Mode
    • 7.4.2 User Program Mode
  • 7.5 Programming/Erasing Flash Memory
    • 7.5.1 Program Mode (n=1 when the target address range is H'00000 to H'3FFFF and n=2 when the target address range is H'40000 to
    • 7.5.2 Program-Verify Mode
    • 7.5.3 Erase Mode (n = 1 when the target address range is H'00000 to H'3FFFF and n = 2 when the target address range is H'40000 t
    • 7.5.4 Erase-Verify Mode (n = 1 when the target address range is H'00000 to H'3FFFF and n = 2 when the target address range is H'
  • 7.6 Flash Memory Protection
    • 7.6.1 Hardware Protection
    • 7.6.2 Software Protection
    • 7.6.3 Error Protection
  • 7.7 Interrupt Handling when Programming/Erasing Flash Memory
  • 7.8 Flash Memory Writer Mode
    • 7.8.1 Writer Mode Setting
    • 7.8.2 Socket Adapters and Memory Map
    • 7.8.3 Writer Mode Operation
    • 7.8.4 Memory Read Mode
    • 7.8.5 Auto-Program Mode
    • 7.8.6 Auto-Erase Mode
    • 7.8.7 Status Read Mode
    • 7.8.8 Status Polling
    • 7.8.9 Writer Mode Transition Time
    • 7.8.10 Notes on Memory Programming
  • 7.9 Notes when Converting the F�ZTAT Application Software to the Mask-ROM Versions
• Section 8 RAM
  • 8.1 Overview
    • 8.1.1 Block Diagram
• Section 9 Clock Pulse Generator
  • 9.1 Overview
    • 9.1.1 Block Diagram
    • 9.1.2 Register Configuration
  • 9.2 Register Descriptions
    • 9.2.1 Standby Control Register (SBYCR)
    • 9.2.2 Low-Power Control Register (LPWRCR)
  • 9.3 Oscillator
    • 9.3.1 Connecting a Crystal Resonator
    • 9.3.2 External Clock Input
  • 9.4 Duty Adjustment Circuit
  • 9.5 Medium-Speed Clock Divider
  • 9.6 Bus Master Clock Selection Circuit
  • 9.7 Subclock Oscillator Circuit
    • 9.7.1 Connecting 32.768 kHz Crystal Resonator
    • 9.7.2 When Subclock is not Needed
  • 9.8 Subclock Waveform Shaping Circuit
  • 9.9 Notes on the Resonator
• Section 10 I/O Port
  • 10.1 Overview
    • 10.1.1 Port Functions
    • 10.1.2 Port Input
    • 10.1.3 MOS Pull-Up Transistors
  • 10.2 Port 0
    • 10.2.1 Overview
    • 10.2.2 Register Configuration
      • (1) Port Mode Register 0 (PMR0)
      • (2) Port Data Register 0 (PDR0)
    • 10.2.3 Pin Functions
    • 10.2.4 Pin States
  • 10.3 Port 1
    • 10.3.1 Overview
    • 10.3.2 Register Configuration
      • Port Mode Register 1 (PMR1)
      • Port Control Register 1 (PCR1)
      • Port Data Register 1 (PDR1)
      • MOS Pull-Up Select Register 1 (PUR1)
    • 10.3.3 Pin Functions
    • 10.3.4 Pin States
  • 10.4 Port 2
    • 10.4.1 Overview
    • 10.4.2 Register Configuration
      • Port Control Register 2 (PCR2)
      • Port Data Register 2 (PDR2)
      • MOS Pull-Up Select Register 2 (PUR2)
    • 10.4.3 Pin Functions
    • 10.4.4 Pin States
  • 10.5 Port 3
    • 10.5.1 Overview
    • 10.5.2 Register Configuration
      • Port Mode Register 3 (PMR3)
      • Port Control Register 3 (PCR3)
      • Port Data Register 3 (PDR3)
      • MOS Pull-Up Select Register 3 (PUR3)
    • 10.5.3 Pin Functions
    • 10.5.4 Pin States
  • 10.6 Port 4
    • 10.6.1 Overview
    • 10.6.2 Register Configuration
      • Port Mode Register 4 (PMR4)
      • Port Control Register 4 (PCR4)
      • Port Data Register 4 (PDR4)
    • 10.6.3 Pin Functions
    • 10.6.4 Pin States
  • 10.7 Port 6
    • 10.7.1 Overview
    • 10.7.2 Register Configuration
      • Port Mode Register 6 (PMR6)
      • Port Mode Register A (PMRA)
      • Port Control Register 6 (PCR6)
      • Port Data Register 6 (PDR6)
      • Realtime Output Trigger Select Register (RTPSR1)
      • Real Time Output Trigger Edge Select Register (RTPEGR)
    • 10.7.3 Pin Functions
    • 10.7.4 Operation
    • 10.7.5 Pin States
  • 10.8 Port 7
    • 10.8.1 Overview
    • 10.8.2 Register Configuration
      • Port Mode Register 7 (PMR7)
      • Port Mode Register B (PMRB)
      • Port Control Register 7 (PCR7)
      • Port Data Register 7 (PDR7)
      • Realtime Output Trigger Select Register 2 (RTPSR2)
      • Realtime Output Trigger Edge Selection Register (RTPEGR)
    • 10.8.3 Pin Functions
    • 10.8.4 Operation
    • 10.8.5 Pin States
  • 10.9 Port 8
    • 10.9.1 Overview
    • 10.9.2 Register Configuration
      • Port Mode Register 8 (PMR8)
      • Port Mode Register C (PMRC)
      • Port Control Register 8 (PCR8)
      • Port Data Register 8 (PDR8)
    • 10.9.3 Pin Functions
    • 10.9.4 Pin States
• Section 11 Timer A
  • 11.1 Overview
    • 11.1.1 Features
    • 11.1.2 Block Diagram
    • 11.1.3 Register Configuration
  • 11.2 Register Descriptions
    • 11.2.1 Timer Mode Register A (TMA)
    • 11.2.2 Timer Counter A (TCA)
    • 11.2.3 Module Stop Control Register (MSTPCR)
  • 11.3 Operation
    • 11.3.1 Operation as the Interval Timer
    • 11.3.2 Operation as Clock Timer
    • 11.3.3 Initializing the Counts
• Section 12 Timer B
  • 12.1 Overview
    • 12.1.1 Features
    • 12.1.2 Block Diagram
    • 12.1.3 Pin Configuration
    • 12.1.4 Register Configuration
  • 12.2 Register Descriptions
    • 12.2.1 Timer Mode Register B (TMB)
    • 12.2.2 Timer Counter B (TCB)
    • 12.2.3 Timer Load Register B (TLB)
    • 12.2.4 Port Mode Register A (PMRA)
    • 12.2.5 Module Stop Control Register (MSTPCR)
  • 12.3 Operation
    • 12.3.1 Operation as the Interval Timer
    • 12.3.2 Operation as the Auto Reload Timer
    • 12.3.3 Event Counter
• Section 13 Timer J
  • 13.1 Overview
    • 13.1.1 Features
    • 13.1.2 Block Diagram
    • 13.1.3 Pin Configuration
    • 13.1.4 Register Configuration
  • 13.2 Register Descriptions
    • 13.2.1 Timer Mode Register J (TMJ)
    • 13.2.2 Timer J Control Register (TMJC)
    • 13.2.3 Timer J Status Register (TMJS)
    • 13.2.4 Timer Counter J (TCJ)
    • 13.2.5 Timer Counter K (TCK)
    • 13.2.6 Timer Load Register J (TLJ)
    • 13.2.7 Timer Load Register K (TLK)
    • 13.2.8 Module Stop Control Register (MSTPCR)
  • 13.3 Operation
    • 13.3.1 8-bit Reload Timer (TMJ-1)
    • 13.3.2 8-bit Reload Timer (TMJ-2)
    • 13.3.3 Remote Controlled Data Transmission
    • 13.3.4 TMJ-2 Expansion Function
• Section 14 Timer L
  • 14.1 Overview
    • 14.1.1 Features
    • 14.1.2 Block Diagram
    • 14.1.3 Register Configuration
  • 14.2 Register Descriptions
    • 14.2.1 Timer L Mode Register (LMR)
    • 14.2.2 Linear Time Counter (LTC)
    • 14.2.3 Reload/Compare Match Register (RCR)
    • 14.2.4 Module Stop Control Register (MSTPCR)
  • 14.3 Operation
    • 14.3.1 Compare Match Clear Operation
• Section 15 Timer R
  • 15.1 Overview
    • 15.1.1 Features
    • 15.1.2 Block Diagram
    • 15.1.3 Pin Configuration
    • 15.1.4 Register Configuration
  • 15.2 Register Descriptions
    • 15.2.1 Timer R Mode Register 1 (TMRM1)
    • 15.2.2 Timer R Mode Register 2 (TMRM2)
    • 15.2.3 Timer R Control/Status Register (TMRCS)
    • 15.2.4 Timer R Capture Register 1 (TMRCP1)
    • 15.2.5 Timer R Capture Register 2 (TMRCP2)
    • 15.2.6 Timer R Load Register 1 (TMRL1)
    • 15.2.7 Timer R Load Register 2 (TMRL2)
    • 15.2.8 Timer R Load Register 3 (TMRL3)
    • 15.2.9 Module Stop Control Register (MSTPCR)
  • 15.3 Operation
    • 15.3.1 Reload Timer Counter Equipped with Capturing Function TMRU-1
    • 15.3.2 Reload Timer Counter Equipped with Capturing Function TMRU-2
    • 15.3.3 Reload Counter Timer TMRU-3
    • 15.3.4 Mode Identification
    • 15.3.5 Reeling Controls
    • 15.3.6 Acceleration and Braking Processes of the Capstan Motor
    • 15.3.7 Slow Tracking Mono-Multi Function
  • 15.4 Interrupt Cause
  • 15.5 Settings for Respective Functions
    • 15.5.1 Mode Identification
    • 15.5.2 Reeling Controls
    • 15.5.3 Slow Tracking Mono-Multi Function
    • 15.5.4 Acceleration and Braking Processes of the Capstan Motor
• Section 16 Timer X1
  • 16.1 Overview
    • 16.1.1 Features
    • 16.1.2 Block Diagram
    • 16.1.3 Pin Configuration
    • 16.1.4 Register Configuration
  • 16.2 Register Descriptions
    • 16.2.1 Free Running Counter (FRC)
    • 16.2.2 Output Comparing Registers A and B (OCRA and OCRB)
    • 16.2.3 Input Capture Registers A Through D (ICRA Through ICRD)
    • 16.2.4 Timer Interrupt Enabling Register (TIER)
    • 16.2.5 Timer Control/Status Register X (TCSRX)
    • 16.2.6 Timer Control Register X (TCRX)
    • 16.2.7 Timer Output Comparing Control Register (TOCR)
    • 16.2.8 Module Stop Control Register (MSTPCR)
  • 16.3 Operation
    • 16.3.1 Operation of Timer X1
    • 16.3.2 Counting Timing of the FRC
    • 16.3.3 Output Comparing Signal Outputting Timing
    • 16.3.4 FRC Clearing Timing
    • 16.3.5 Input Capture Signal Inputting Timing
    • 16.3.6 Input Capture Flag (ICFA through ICFD) Setting Up Timing
    • 16.3.7 Output Comparing Flag (OCFA and OCFB) Setting Up Timing
    • 16.3.8 Overflow Flag (CVF) Setting Up Timing
  • 16.4 Operation Mode of Timer X1
  • 16.5 Interrupt Causes
  • 16.6 Exemplary Uses of Timer X1
  • 16.7 Precautions when Using Timer X1
    • 16.7.1 Competition between Writing and Clearing with the FRC
    • 16.7.2 Competition between Writing and Counting Up with the FRC
    • 16.7.3 Competition between Writing and Comparing Match with the OCR
    • 16.7.4 Changing Over the Internal Clocks and Counter Operations
• Section 17 Watchdog Timer (WDT)
  • 17.1 Overview
    • 17.1.1 Features
    • 17.1.2 Block Diagram
    • 17.1.3 Register Configuration
  • 17.2 Register Descriptions
    • 17.2.1 Watchdog Timer Counter (WTCNT)
    • 17.2.2 Watchdog Timer Control/Status Register (WTCSR)
    • 17.2.3 System Control Register (SYSCR)
    • 17.2.4 Notes on Register Access
  • 17.3 Operation
    • 17.3.1 Watchdog Timer Operation
    • 17.3.2 Interval Timer Operation
    • 17.3.3 Timing of Setting of Overflow Flag (OVF)
  • 17.4 Interrupts
  • 17.5 Usage Notes
    • 17.5.1 Contention between Watchdog Timer Counter (WTCNT) Write and Increment
    • 17.5.2 Changing Value of CKS2 to CKS0
    • 17.5.3 Switching between Watchdog Timer Mode and Interval Timer Mode
• Section 18 8-Bit PWM
  • 18.1 Overview
    • 18.1.1 Features
    • 18.1.2 Block Diagram
    • 18.1.3 Pin Configuration
    • 18.1.4 Register Configuration
  • 18.2 Register Descriptions
    • 18.2.1 8-bit PWM Data Registers 0, 1, 2 and 3 (PWR0, PWR1, PWR2, PWR3)
    • 18.2.2 8-bit PWM Control Register (PW8CR)
    • 18.2.3 Port Mode Register 3 (PMR3)
    • 18.2.4 Module Stop Control Register (MSTPCR)
  • 18.3 8-Bit PWM Operation
• Section 19 12-Bit PWM
  • 19.1 Overview
    • 19.1.1 Features
    • 19.1.2 Block Diagram
    • 19.1.3 Pin Configuration
    • 19.1.4 Register Configuration
  • 19.2 Register Descriptions
    • 19.2.1 12-Bit PWM Control Registers (CPWCR, DPWCR)
    • 19.2.2 12-Bit PWM Data Registers (DPWDR, CPWDR)
  • 19.3 Operation
    • 19.3.1 Output Waveform
• Section 20 14-Bit PWM
  • 20.1 Overview
    • 20.1.1 Features
    • 20.1.2 Block Diagram
    • 20.1.3 Pin Configuration
    • 20.1.4 Register Configuration
  • 20.2 Register Descriptions
    • 20.2.1 PWM Control Register (PWCR)
    • 20.2.2 PWM Data Registers U and L (PWDRU, PWDRL)
    • 20.2.3 Module Stop Control Register (MSTPCR)
  • 20.3 14-Bit PWM Operation
• Section 21 Prescalar Unit
  • 21.1 Overview
    • 21.1.1 Features
    • 21.1.2 Block Diagram
    • 21.1.3 Pin Configuration
    • 21.1.4 Register Configuration
  • 21.2 Registers
    • 21.2.1 Input Capture Register 1 (ICR1)
    • 21.2.2 Prescalar Unit Control/Status Register (PCSR)
    • 21.2.3 Port Mode Register 1 (PMR1)
  • 21.3 Noise Cancel Circuit
  • 21.4 Operation
    • 21.4.1 Prescalar S (PSS)
    • 21.4.2 Prescalar W (PSW)
    • 21.4.3 Stable Oscillation Wait Time Count
    • 21.4.4 8-bit PWM
    • 21.4.5 8-bit Input Capture Using ,& ,& ,& ,& Pin
    • 21.4.6 Frequency Division Clock Output
• Section 22 Serial Communication Interface 1 (SCI1)
  • 22.1 Overview
    • 22.1.1 Features
    • 22.1.2 Block Diagram
    • 22.1.3 Pin Configuration
    • 22.1.4 Register Configuration
  • 22.2 Register Descriptions
    • 22.2.1 Receive Shift Register 1 (RSR1)
    • 22.2.2 Receive Data Register 1 (RDR1)
    • 22.2.3 Transmit Shift Register 1 (TSR1)
    • 22.2.4 Transmit Data Register 1 (TDR1)
    • 22.2.5 Serial Mode Register 1 (SMR1)
    • 22.2.6 Serial Control Register 1 (SCR1)
    • 22.2.7 Serial Status Register 1 (SSR1)
    • 22.2.8 Bit Rate Register 1 (BRR1)
    • 22.2.9 Serial Interface Mode Register 1 (SCMR1)
    • 22.2.10 Module Stop Control Register (MSTPCR)
  • 22.3 Operation
    • 22.3.1 Overview
    • 22.3.2 Operation in Asynchronous Mode
    • 22.3.3 Multiprocessor Communication Function
    • 22.3.4 Operation in Synchronous Mode
  • 22.4 SCI Interrupts
  • 22.5 Usage Notes
• Section 23
  • 23.1 Overview
    • 23.1.1 Features
    • 23.1.2 Block Diagram
    • 23.1.3 Pin Configuration
    • 23.1.4 Register Configuration
  • 23.2 Register Descriptions
    • 23.2.1 I2C Bus Data Register (ICDR)
    • 23.2.2 Slave Address Register (SAR)
    • 23.2.3 Second Slave Address Register (SARX)
    • 23.2.4 I2C Bus Mode Register (ICMR)
    • 23.2.5 I2C Bus Control Register (ICCR)
    • 23.2.6 I2C Bus Status Register (ICSR)
    • 23.2.7 Serial/Timer Control Register (STCR)
    • 23.2.8 DDC Switch Register (DDCSWR)
    • 23.2.9 Module Stop Control Register (MSTPCR)
  • 23.3 Operation
    • 23.3.1 I2C Bus Data Format
    • 23.3.2 Master Transmit Operation
    • 23.3.3 Master Receive Operation
    • 23.3.4 Slave Receive Operation
    • 23.3.5 Slave Transmit Operation
    • 23.3.6 IRIC Setting Timing and SCL Control
    • 23.3.7 Automatic Switching from Formatless Transfer to I
    • 23.3.8 Noise Canceler
    • 23.3.9 Sample Flowcharts
    • 23.3.10 Initializing Internal Status
  • 23.4 Usage Notes
• Section 24 A/D Converter
  • 24.1 Overview
    • 24.1.1 Features
    • 24.1.2 Block Diagram
    • 24.1.3 Pin Configuration
    • 24.1.4 Register Configuration
  • 24.2 Register Descriptions
    • 24.2.1 Software-Triggered A/D Result Register (ADR)
    • 24.2.2 Hardware-Triggered A/D Result Register (AHR)
    • 24.2.3 A/D Control Register (ADCR)
    • 24.2.4 A/D Control/Status Register (ADCSR)
    • 24.2.5 Trigger Select Register (ADTSR)
    • 24.2.6 Port Mode Register 0 (PMR0)
    • 24.2.7 Module Stop Control Register (MSTPCR)
  • 24.3 Interface to Bus Master
  • 24.4 Operation
    • 24.4.1 Software-Triggered A/D Conversion
    • 24.4.2 Hardware- or External-Triggered A/D Conversion
  • 24.5 Interrupt Sources
• Section 25 Address Trap Controller (ATC)
  • 25.1 Overview
    • 25.1.1 Features
    • 25.1.2 Block Diagram
    • 25.1.3 Register Configuration
  • 25.2 Register Descriptions
    • 25.2.1 Address Trap Control Register (ATCR)
    • 25.2.2 Trap Address Register 2 to 0 (TAR2 to TAR0)
  • 25.3 Precautions in Usage
    • 25.3.1 Basic Operations
    • 25.3.2 Enabling
    • 25.3.3 Bcc Instruction
    • 25.3.4 BSR Instruction
    • 25.3.5 JSR Instruction
    • 25.3.6 JMP Instruction
    • 25.3.7 RTS Instruction
    • 25.3.8 SLEEP Instruction
    • 25.3.9 Competing Interrupt
• Section 26 Servo Circuits
  • 26.1 Overview
    • 26.1.1 Functions
    • 26.1.2 Block Diagram
  • 26.2 Servo Port
    • 26.2.1 Overview
    • 26.2.2 Block Diagram
    • 26.2.3 Pin Configuration
    • 26.2.4 Register Configuration
    • 26.2.5 Register Description
      • Servo Port Mode Register (SPMR)
      • Servo Monitor Control Register (SVMCR)
      • CTL Gain Control Register (CTLGR)
    • 26.2.6 DFG/DPG Input Signals
  • 26.3 Reference Signal Generators
    • 26.3.1 Overview
    • 26.3.2 Block Diagram
    • 26.3.3 Register Configuration
    • 26.3.4 Register Description
      • Reference Period Mode Register (RFM)
      • Reference Period Register 1 (RFD)
      • Reference Period Register 2 (CRF)
      • REF30 Counter Register (RFC)
      • Reference Period Mode Register 2 (RFM2)
    • 26.3.5 Operation
  • 26.4 HSW (Head-switch) Timing Generator
    • 26.4.1 Overview
    • 26.4.2 Block Diagram
    • 26.4.3 HSW Timing Generator Configuration
    • 26.4.4 Register Configuration
    • 26.4.5 Register Description
      • HSW Mode Register 1 (HSM1)
      • HSW Mode Register 2 (HSM2)
      • FIFO Output Pattern Register 1 (FPDRA)
      • FIFO Output Pattern Register 2 (FPDRB)
      • FIFO Timing Pattern Register 1 (FTPRA)
      • FIFO Timing Pattern Register 2 (FTPRB)
      • DFG Reference Register 1 (DFCRA)
      • DFG Reference Register 2 (DFCRB)
      • FIFO Timer Capture Register (FTCTR)
      • DFG Reference Count Register (DFCTR)
    • 26.4.6 Operation
    • 26.4.7 Interrupts
    • 26.4.8 Cautions
  • 26.5 High-Speed Switching Circuit for Four-Head Special Playback
    • 26.5.1 Overview
    • 26.5.2 Block Diagram
    • 26.5.3 Pin Configuration
    • 26.5.4 Register Description
      • Special Playback Control Register (CHCR)
  • 26.6 Drum Speed Error Detector
    • 26.6.1 Overview
    • 26.6.2 Block Diagram
    • 26.6.3 Register Configuration
    • 26.6.4 Register Description
      • DFG Speed Error Data Register (DFER)
      • DFG Lock Upper Data Register (DFRUDR)
      • DFG Lock LOWER Data Register (DFRLDR)
      • Drum Speed Error Detection Control Register (DFVCR)
    • 26.6.5 Operation
    • 26.6.6 f H Correction in Trick Play Mode
  • 26.7 Drum Phase Error Detector
    • 26.7.1 Overview
    • 26.7.2 Block Diagram
    • 26.7.3 Register Configuration
    • 26.7.4 Register Description
      • Drum Phase Preset Data Registers (DPPR1, DPPR2)
      • Drum Phase Error Data Registers (DPER1, DPER2)
      • Drum Phase Error Detection Control Register (DPGCR)
    • 26.7.5 Operation
    • 26.7.6 Phase Comparison
  • 26.8 Capstan Speed Error Detector
    • 26.8.1 Overview
    • 26.8.2 Block Diagram
    • 26.8.3 Register Configuration
    • 26.8.4 Register Description
      • Specified CFG Speed Preset Data Register (CFPR)
      • CFG Speed Error Data Register (CFER)
      • CFG Lock UPPER Data Register (CFRUDR)
      • CFG Lock LOWER Data Register (CFRLDR)
      • Capstan Speed Error Detection Control Register (CFVCR)
    • 26.8.5 Operation
  • 26.9 Capstan Phase Error Detector
    • 26.9.1 Overview
    • 26.9.2 Block Diagram
    • 26.9.3 Register Configuration
    • 26.9.4 Register Description
      • Specified Capstan Phase Preset Data Registers (CPPR1, CPPR2)
      • Capstan Phase Error Data Registers (CPER1, CPER2)
      • Capstan Phase Error Detection Control Register (CPGCR)
    • 26.9.5 Operation
  • 26.10 X-Value and Tracking Adjustment Circuit
    • 26.10.1 Overview
    • 26.10.2 Block Diagram
    • 26.10.3 Register Description
      • X-Value and TRK-Value Control Register (XTCR)
      • X-Value Data Register (XDR)
      • TRK-Value Data Register (TRDR)
  • 26.11 Digital Filters
    • 26.11.1 Overview
    • 26.11.2 Block Diagram
    • 26.11.3 Arithmetic Buffer
    • 26.11.4 Register Configuration
    • 26.11.5 Register Description
      • Gain Constants (DGKp, DGKs, CGKp, CGKs)
      • Coefficients (DAp, DBp, DAs, DBs, CAp, CBp, CAs, CBs)
      • Offset (DOfp, DOfs, COfp, COfs)
      • Delay Initialization Register (CZp, CZs, DZp, DZs)
      • Drum System Digital Filter Control Register (DFIC)
      • Capstan System Digital Filter Control Register (CFIC)
      • Digital Filter Control Register (DFUCR)
    • 26.11.6 Filter Characteristics
    • 26.11.7 Operations in Case of Transient Response
    • 26.11.8 Initialization of Z
  • 26.12 Additional V Signal Generator
    • 26.12.1 Overview
    • 26.12.2 Pin Configuration
    • 26.12.3 Register Configuration
    • 26.12.4 Register Description
    • 26.12.5 Additional V Pulse Signal
  • 26.13 CTL Circuit
    • 26.13.1 Overview
    • 26.13.2 Block Diagram
    • 26.13.3 Pin Configuration
    • 26.13.4 Register Configuration
    • 26.13.5 Register Description
      • CTL Control Register (CTCR)
      • CTL Mode Register (CTLM)
      • REC-CTL Duty Data Register 1 (RCDR1)
      • REC-CTL Duty Data Register 2 (RCDR2)
      • REC-CTL Duty Data Register 3 (RCDR3)
      • REC-CTL Duty Data Register 4 (RCDR4)
      • REC-CTL Duty Data Register 5 (RCDR5)
      • Duty I/O Register (DI/O)
      • Bit Pattern Register (BTPR)
    • 26.13.6 Operation
    • 26.13.7 CTL Input Section
    • 26.13.8 Duty Discriminator
    • 26.13.9 CTL Output Section
    • 26.13.10 Trapezoid Waveform Circuit
    • 26.13.11 Note on CTL Interrupt
  • 26.14 Frequency Dividers
    • 26.14.1 Overview
    • 26.14.2 CTL Frequency Divider
      • Register Description
        • DVCTL Control Register (CTVC)
        • CTL Frequency Division Register (CTLR)
    • 26.14.3 CFG Frequency Divider
      • Register Description:
      • DVCFG Control Register (CDVC)
      • CFG Frequency Division Register 2 (CDIVR2)
      • DVCFG Mask Period Register (CTMR)
    • 26.14.4 DFG Noise Removal Circuit
      • Register Description:
        • FG Control Register (FGCR)
  • 26.15 Sync Signal Detector
    • 26.15.1 Overview
    • 26.15.2 Block Diagram
    • 26.15.3 Pin Configuration
    • 26.15.4 Register Configuration
    • 26.15.5 Register Description
      • Vertical Sync Signal Threshold Register (VTR)
      • Horizontal Sync Signal Threshold Register (HTR)
      • H Complement Start Time Setting Register (HRTR)
      • Complementary H Pulse Width Setting Register (HPWR)
      • Noise Detection Window Setting Register (NWR)
      • Noise Detection Register (NDR)
      • Sync Signal Control Register (SYNCR)
    • 26.15.6 Noise Detection
    • 26.15.7 Activation of the Sync Signal Detector
  • 26.16 Servo Interrupt
    • 26.16.1 Overview
    • 26.16.2 Register Configuration
    • 26.16.3 Register Description
      • Servo Interrupt Enable Register 1 (SIENR1)
      • Servo Interrupt Enable Register 2 (SIENR2)
      • Servo Interrupt Request Register 1 (SIRQR1)
      • Servo Interrupt Request Register 2 (SIRQR2)
• Section 27 Sync Separator for OSD and Data Slicer
  • 27.1 Overview
    • 27.1.1 Features
    • 27.1.2 Block Diagram
    • 27.1.3 Pin Configuration
    • 27.1.4 Register Configuration
  • 27.2 Register Description
    • 27.2.1 Sync Separation Input Mode Register (SEPIMR)
    • 27.2.2 Sync Separation Control Register (SEPCR)
    • 27.2.3 Sync Separation AFC Control Register (SEPACR)
    • 27.2.4 Horizontal Sync Signal Threshold Register (HVTHR)
    • 27.2.5 Vertical Sync Signal Threshold Register (VVTHR)
    • 27.2.6 Field Detection Window Register (FWIDR)
    • 27.2.7 H Complement and Mask Timing Register (HCMMR)
    • 27.2.8 Noise Detection Counter (NDETC)
    • 27.2.9 Noise Detection Level Register (NDETR)
    • 27.2.10 Data Slicer Detection Window Register (DDETWR)
    • 27.2.11 Internal Sync Frequency Register (INFRQR)
  • 27.3 Operation
    • 27.3.1 Selecting Source Signals for Sync Separation
    • 27.3.2 Vsync Separation
    • 27.3.3 Hsync Separation
    • 27.3.4 Field Detection
    • 27.3.5 Noise Detection
    • 27.3.6 Automatic Frequency Controller (AFC)
    • 27.3.7 Module Stop Control Register (MSTPCR)
• Section 28 Data Slicer
  • 28.1 Overview
    • 28.1.1 Features
    • 28.1.2 Block Diagram
    • 28.1.3 Pin Configuration
    • 28.1.4 Register Configuration
    • 28.1.5 Data Slicer Use Conditions
  • 28.2 Register Description
    • 28.2.1 Slice Even- (Odd-) Field Mode Register (SEVFD, SODFD)
    • 28.2.2 Slice Line Setting Registers 1 to 4 (SLINE1 to SLINE4)
    • 28.2.3 Slice Detection Registers 1 to 4 (SDTCT1 to SDTCT4)
    • 28.2.4 Slice Data Registers 1 to 4 (SDATA1 to SDATA4)
    • 28.2.5 Module Stop Control Register (MSTPCR)
    • 28.2.6 Monitor Output Setting Register (DOUT)
  • 28.3 Operation
    • 28.3.1 Slice Line Specification
    • 28.3.2 Slice Sequence
• Section 29 On-Screen Display (OSD)
  • 29.1 Overview
    • 29.1.1 Features
    • 29.1.2 Block Diagram
    • 29.1.3 Pin Configuration
    • 29.1.4 Register Configuration
    • 29.1.5 TV Formats and Display Modes
  • 29.2 Description of Display Functions
    • 29.2.1 Superimposed Mode and Text Display Mode
    • 29.2.2 Character Configuration
    • 29.2.3 On-Screen Display Configuration
  • 29.3 Settings in Character Units
    • 29.3.1 Character Configuration
    • 29.3.2 Character Colors
    • 29.3.3 Halftones/Cursors
    • 29.3.4 Blinking
    • 29.3.5 Button Display
    • 29.3.6 Character Data ROM (OSDROM)
    • 29.3.7 Display Data RAM (OSDRAM)
  • 29.4 Settings in Row Units
    • 29.4.1 Button Patterns
    • 29.4.2 Display Enlargement
    • 29.4.3 Character Brightness
    • 29.4.4 Cursor Color, Brightness, Halftone Levels
    • 29.4.5 Row Registers (CLINEn, n = rows 1 to 12)
  • 29.5 Settings in Screen Units
    • 29.5.1 Display Positions
    • 29.5.2 Turning the OSD Display On and Off
    • 29.5.3 Display Method
    • 29.5.4 Blinking Period
    • 29.5.5 Borders
    • 29.5.6 Background Color and Brightness
    • 29.5.7 Character, Cursor, and Background Chroma Saturation
    • 29.5.8 Display Position Registers (HPOS and VPOS)
    • 29.5.9 Screen Control Register (DCNTL)
  • 29.6 Other Settings
    • 29.6.1 TV Format
    • 29.6.2 Display Data RAM Control
    • 29.6.3 Timing of OSD Display Updates Using Register Rewriting
    • 29.6.4 4fsc/2fsc
    • 29.6.5 OSDV Interrupts
    • 29.6.6 OSD Format Register (DFORM)
  • 29.7 Digital Output
    • 29.7.1 R, G, and B Outputs
    • 29.7.2 YCO and YBO Outputs
    • 29.7.3 Digital Output Specification Register (DOUT)
    • 29.7.4 Module Stop Control Register (MTSTPCR)
  • 29.8 Notes on OSD Font Creation
    • 29.8.1 Note 1 on Font Creation (Font Width)
    • 29.8.2 Note 2 on Font Creation (Borders)
    • 29.8.3 Note 3 on Font Creation (Blinking)
    • 29.8.4 Note 4 on Font Creation (Buttons)
  • 29.9 OSD Oscillator, AFC, and Dot Clock
    • 29.9.1 Sync Signals
    • 29.9.2 AFC Circuit
    • 29.9.3 Dot Clock
    • 29.9.4 4/2fsc
  • 29.10 OSD Operation in CPU Operation Modes
  • 29.11 Character Data ROM (OSDROM) Access by CPU
    • 29.11.1 Serial Timer Control Register (STCR)
• Section 30 Electrical Characteristics
  • 30.1 Absolute Maximum Ratings
  • 30.2 Electrical Characteristics of HD6432199, HD6432198, HD6432197,and HD6432196
    • 30.2.1 DC Characteristics of HD6432199, HD6432198, HD6432197, and HD6432196
    • 30.2.2 Allowable Output Currents of HD6432199, HD6432198, HD6432197, and HD6432196
    • 30.2.3 AC Characteristics of HD6432199, HD6432198, HD6432197, and HD6432196
    • 30.2.4 Serial Interface Timing of HD6432199, HD6432198, HD6432197, and HD6432196
    • 30.2.5 A/D Converter Characteristics of HD6432199, HD6432198, HD6432197, and HD6432196
    • 30.2.6 Servo Section Electrical Characteristics of HD6432199, HD6432198, HD6432197,and HD6432196
    • 30.2.7 OSD Electrical Characteristics of HD6432199, HD6432198, HD6432197, and HD6432196
  • 30.3 Electrical Characteristics of HD64F2199
    • 30.3.1 DC Characteristics of HD64F2199
    • 30.3.2 Allowable Output Currents of HD64F2199
    • 30.3.3 AC Characteristics of HD64F2199
    • 30.3.4 Serial Interface Timing of HD64F2199
    • 30.3.5 A/D Converter Characteristics of HD64F2199
    • 30.3.6 Servo Section Electrical Characteristics of HD64F2199
    • 30.3.7 OSD Electrical Characteristics of HD64F2199
• Appendix A Instruction Set
  • A.1 Instructions
    • Operation Notation
    • Condition Code Notation
  • A.2 Instruction Codes
  • A.3 Operation Code Map
  • A.4 Number of Execution States
  • A.5 Bus Status during Instruction Execution
  • A.6 Change of Condition Codes
• Appendix B Internal I/O Registers
  • B.1 Addresses
  • B.2 Function List
• Appendix C Pin Circuit Diagrams
  • C.1 Pin Circuit Diagrams
• Appendix D Port States in Each Processing State
  • D.1 Pin Circuit Diagrams
• Appendix E Usage Notes
  • E.1 Power Supply Rise and Fall Order
  • E.2 Sample External Circuits
  • E.3 Handling of Pins When OSD Is Not Used
• Appendix F Product Lineup
• Appendix G Package Dimensions