Document Outline
- Cover
- Cautions
- General Precautions on Handling of Product
- Configuration of This Manual
- Preface
- Main Revisions and Additions in this Edition
- Contents
- Section 1 Overview
- 1.1 Overview
- 1.2 Internal Block Diagram
- 1.3 Pin Arrangement
- 1.4 Pin Functions
- Section 2 CPU
- 2.1 Features
- 2.1.1 Differences between H8S/2600 CPU and H8S/2000 CPU
- 2.1.2 Differences from H8/300 CPU
- 2.1.3 Differences from H8/300H CPU
- 2.2 CPU Operating Modes
- 2.2.1 Normal Mode
- 2.2.2 Advanced Mode
- 2.3 Address Space
- 2.4 Register Configuration
- 2.4.1 General Registers
- 2.4.2 Program Counter (PC)
- 2.4.3 Extended Control Register (EXR)
- 2.4.4 Condition-Code Register (CCR)
- 2.4.5 Multiply-Accumulate Register (MAC)
- 2.4.6 Initial Values of CPU Registers
- 2.5 Data Formats
- 2.5.1 General Register Data Formats
- 2.5.2 Memory Data Formats
- 2.6 Instruction Set
- 2.6.1 Table of Instructions Classified by Function
- 2.6.2 Basic Instruction Formats
- 2.7 Addressing Modes and E ective Address Calculation
- 2.7.1 Register Direct Rn
- 2.7.2 Register Indirect @ERn
- 2.7.3 Register Indirect with Displacement @(d:16,ERn)or @(d:32,ERn)
- 2.7.4 Register Indirect with Post-Increment or Pre-Decrement @ERn+or @-ERn
- 2.7.5 Absolute Address @aa:8,@aa:16,@aa:24,or @aa:32
- 2.7.6 Immediate #xx:8,#xx:16,or #xx:32
- 2.7.7 Program-Counter Relative @(d:8,PC)or @(d:16,PC)
- 2.7.8 Memory Indirect @@aa:8
- 2.7.9 Effective Address Calculation
- 2.8 Processing States
- 2.9 Usage Notes
- 2.9.1 Usage Notes on Bit Manipulation Instructions
- Section 3 MCU Operating Modes
- 3.1 Operating Mode Selection
- 3.2 Register Descriptions
- 3.2.1 Mode Control Register(MDCR)
- 3.2.2 System Control Register(SYSCR)
- 3.3 Pin Functions in Each Operating Mode
- 3.4 Address Map
- Section 4 Exception Handling
- 4.1 Exception Handling Types and Priority
- 4.2 Exception Sources and Exception Vector Table
- 4.3 Reset
- 4.3.1 Reset Exception Handling
- 4.3.2 Interrupts after Reset
- 4.3.3 State of On-Chip Supporting Modules after Reset Release
- 4.4 Traces
- 4.5 Interrupts
- 4.6 Trap Instruction
- 4.7 Stack Status after Exception Handling
- 4.8 Usage Note
- Section 5 Interru t Controller
- 5.1 Features
- 5.2 Input/Output Pins
- 5.3 Register Descriptions
- 5.3.1 Interrupt Priority Registers A to H,J,K,M (IPRA to IPRH,IPRJ,IPRK,IPRM)
- 5.3.2 IRQ Enable Register (IER)
- 5.3.3 IRQ Sense Control Registers H and L (ISCRH,ISCRL)
- 5.3.4 IRQ Status Register (ISR)
- 5.4 Interrupt
- 5.4.1 External Interrupts
- 5.4.2 Internal Interrupts
- 5.5 Interrupt Exception Handling Vector Table
- 5.6 Interrupt Control Modes and Interrupt Operation
- 5.6.1 Interrupt Control Mode 0
- 5.6.2 Interrupt Control Mode 2
- 5.6.3 Interrupt Exception Handling Sequence
- 5.6.4 Interrupt Response Times
- 5.6.5 DTC Activation by Interrupt
- 5.7 Usage Notes
- 5.7.1 Contention between Interrupt Generation and Disabling
- 5.7.2 Instructions that Disable Interrupts
- 5.7.3 When Interrupts are Disabled
- 5.7.4 Interrupts during Execution of EEPMOV Instruction
- Section 6 PC Break Controller (PBC)
- 6.1 Features
- 6.2 Register Descriptions
- 6.2.1 Break Address Register A (BARA)
- 6.2.2 Break Address Register B (BARB)
- 6.2.3 Break Control Register A (BCRA)
- 6.2.4 Break Control Register B (BCRB)
- 6.3 Operation
- 6.3.1 PC Break Interrupt Due to Instruction Fetch
- 6.3.2 PC Break Interrupt Due to Data Access
- 6.3.3 Notes on PC Break Interrupt Handling
- 6.3.4 Operation in Transitions to Power-Down Modes
- 6.3.5 When Instruction Execution is Delayed by One State
- 6.4 Usage Notes
- 6.4.1 Module Stop Mode Setting
- 6.4.2 PC Break Interrupts
- 6.4.3 CMFA and CMFB
- 6.4.4 PC Break Interrupt when DTC is Bus Master
- 6.4.5 PC Break Set for Instruction Fetch at Address Following BSR,JSR,JMP,TRAPA, RTE,or RTS Instruction
- 6.4.6 I Bit Set by LDC,ANDC,ORC,or XORC Instruction
- 6.4.7 PC Break Set for Instruction Fetch at Address Following Bcc Instruction
- 6.4.8 PC Break Set for Instruction Fetch at Branch Destination Address of Bcc Instruction
- Section 7 Bus Controller
- 7.1 Basic Timing
- 7.1.1 On-Chip Memory Access Timin (ROM,RAM)
- 7.1.2On-Chip Support Module Access Timing
- 7.1.3 On-Chip HCAN Module Access Timing
- 7.1.4 On-Chip MMT Module Access Timing
- 7.2Bus Arbitration
- 7.2.1 Order of Priority of the Bus Masters
- 7.2.2 Bus Transfer Timing
- Section 8 Data Transfer Controller (DTC)
- 8.1 Features
- 8.2 Register Configuration
- 8.2.1 DTC Mode Register A (MRA)
- 8.2.2 DTC Mode Register B (MRB)
- 8.2.3 DTC Source Address Register (SAR)
- 8.2.4 DTC Destination Address Register (DAR)
- 8.2.5 DTC Transfer Count Register A (CRA)
- 8.2.6 DTC Transfer Count Register B (CRB)
- 8.2.7 DTC Enable Registers (DTCER)
- 8.2.8 DTC Vector Register (DTVECR)
- 8.3 Activation Sources
- 8.4 Location of Register Information and DTC Vector Table
- 8.5 Operation
- 8.5.1 Normal Mode
- 8.5.2 Repeat Mode
- 8.5.3 Block Transfer Mode
- 8.5.4 Chain Transfer
- 8.5.5 Interrupts
- 8.5.6 Operation Timing
- 8.5.7 Number of DTC Execution States
- 8.6 Procedures for Using DTC
- 8.6.1 Activation by Interrupt
- 8.6.2 Activation by Software
- 8.7 Examples of Use of the DTC
- 8.7.1 Normal Mode
- 8.7.2 Chain Transfer
- 8.7.3 Software Activation
- 8.8 Usage Notes
- 8.8.1 Module Stop Mode Setting
- 8.8.2 On-Chip RAM
- 8.8.3 DTCE Bit Setting
- Section 9 I/O Ports
- 9.1 Por 1
- 9.1.1 Port 1 Data Direction Register (P1DDR)
- 9.1.2 Port 1 Data Register (P1DR)
- 9.1.3 Port 1 Register (PORT1)
- 9.1.4 Pin Functions
- 9.2 Por 4
- 9.2.1 Port 4 Register (PORT4)
- 9.3 Por 9
- 9.3.1 Port 9 Register (PORT9)
- 9.4 Por A
- 9.4.1 Port A Data Direction Register (PADDR)
- 9.4.2 Port A Data Register (PADR)
- 9.4.3 Port A Register (PORTA)
- 9.4.4 Port A Pull-Up MOS Control Register (PAPCR)
- 9.4.5 Port A Open-Drain Control Register (PAODR)
- 9.4.6 Pin Functions
- 9.5 Por B
- 9.5.1 Port B Data Direction Register (PBDDR)
- 9.5.2 Port B Data Register (PBDR)
- 9.5.3 Port B Register (PORTB)
- 9.5.4 Port B Pull-Up MOS Control Register (PBPCR)
- 9.5.5 Port B Open-Drain Control Register (PBODR)
- 9.5.6 Pin Functions
- 9.6 Por C
- 9.6.1 Port C Data Direction Register (PCDDR)
- 9.6.2 Port C Data Register (PCDR)
- 9.6.3 Port C Register (PORTC)
- 9.6.4 Port C Pull-Up MOS Control Register (PCPCR)
- 9.6.5 Port C Open-Drain Control Register (PCODR)
- 9.6.6 Pin Functions
- 9.7 Por D
- 9.7.1 Port D Data Direction Register (PDDDR)
- 9.7.2 Port D Data Register (PDDR)
- 9.7.3 Port D Register (PORTD)
- 9.7.4 Port D Pull-up MOS Control Register (PDPCR)
- 9.8 Por F
- 9.8.1 Port F Data Direction Register (PFDDR)
- 9.8.2 Port F Data Register (PFDR)
- 9.8.3 Port F Register (PORTF)
- 9.8.4 Pin Functions
- Section 10 16-Bit Timer Pulse Unit (TPU)
- 10.1 Features
- 10.2 Input/Output Pins
- 10.3 Register Descriptions
- 10.3.1 Timer Control Register (TCR)
- 10.3.2 Timer Mode Register (TMDR)
- 10.3.3 Timer I/O Control Register (TIOR)
- 10.3.4 Timer Interrupt Enable Register (TIER)
- 10.3.5 Timer Status Register (TSR)
- 10.3.6 Timer Counter (TCNT)
- 10.3.7 Timer General Register (TGR)
- 10.3.8 Timer Start Register (TSTR)
- 10.3.9 Timer Synchro Register (TSYR)
- 10.4 Operation
- 10.4.1 Basic Functions
- 10.4.2 Synchronous Operation
- 10.4.3 Buffer Operation
- 10.4.4 Cascaded Operation
- 10.4.5 PWM Modes
- 10.4.6 Phase Counting Mode
- 10.5 Interrupts
- 10.6 DTC Activation
- 10.7 A/D Converter Activation
- 10.8 Operation Timing
- 10.8.1 Input/Output Timing
- 10.8.2 Interrupt Signal Timing
- 10.9 Usage Notes
- 10.9.1 Module Stop Mode Setting
- 10.9.2 Input Clock Restrictions
- 10.9.3 Caution on Period Setting
- 10.9.4 Contention between TCNT Write and C ear Operations
- 10.9.5 Contention between TCNT Write and Increment Operations
- 10.9.6 Contention between TGR Write and Compare Match
- 10.9.7 Contention between Buffer Register Write and Compare Match
- 10.9.8 Contention between TGR Read and Input Capture
- 10.9.9 Contention between TGR Write and Input Capture
- 10.9.10 Contention between Buffer Register Write and Input Capture
- 10.9.11 Contention between Overflow/Underflow and Counter Clearing
- 10.9.12 Contention between TCNT Write and Overflow/Underflow
- 10.9.13 Multiplexing of I/O Pins
- 10.9.14 Interrupts in Module Stop Mode
- Section 11 Motor Management Timer (MMT)
- 11.1 Features
- 11.2 Input/Output Pins
- 11.3 Register Descriptions
- 11.3.1 Timer Mode Register (TMDR)
- 11.3.2 Timer Control Register (TCNR)
- 11.3.3 Timer Status Register (TSR)
- 11.3.4 Timer Counter (TCNT)
- 11.3.5 Timer Buffer Registers (TBR)
- 11.3.6 Timer General Registers (TGR)
- 11.3.7 Timer Dead Time Counters (TDCNT)
- 11.3.8 Timer Dead Time Data Register (TDDR)
- 11.3.9 Timer Period Buffer Register (TPBR)
- 11.3.10 Timer Period Data Register (TPDR)
- 11.3.11 MMT Pin Control Register (MMTPC)
- 11.4 Operation
- 11.4.1 Sample Setting Procedure
- 11.4.2 Output Protection Functions
- 11.5 Interrupts
- 11.6 Operation Timing
- 11.6.1 Input/Output Timing
- 11.6.2 Interrupt Signal Timing
- 11.7 Usage Notes
- 11.7.1 Module Stop Mode Setting
- 11.7.2 Notes for MMT Operation
- 11.8 Port Output Enable (POE)
- 11.8.1 Features
- 11.8.2 Input/Output Pins
- 11.8.3 Register Descriptions
- 11.8.4 Operation
- Section 12 Programmable Pulse Generator (PPG)
- 12.1 Features
- 12.2 Input/Output Pins
- 12.3Register Descriptions
- 12.3.1 Next Data Enable Registers H,L (NDERH,NDERL)
- 12.3.2 Output Data Registers H,L (PODRH,PODRL)
- 12.3.3 Next Data Registers H,L (NDRH,NDRL)
- 12.3.4 PPG Output Control Register (PCR)
- 12.3.5 PPG Output Mode Register (PMR)
- 12.4 Operation
- 12.4.1 Overview
- 12.4.2 Output Timing
- 12.4.3 Sample Setup Procedure for Normal Pulse Output
- 12.4.4 Example of Normal Pulse Output (Example of Five-Phase Pulse Output)
- 12.4.5 Non-Overlapping Pulse Output
- 12.4.6 Sample Setup Procedure for Non-Overlapping Pulse Output
- 12.4.7 Example of Non-Overlapping Pulse Output (Example of Four-Phase Complementary Non-Overlapping Output)
- 12.4.8 Inverted Pulse Output
- 12.4.9 Pulse Output Triggered by Input Capture
- 12.5 Usage Notes
- 12.5.1 Module Stop Mode Setting
- 12.5.2 Operation of Pulse Output Pins
- Section 13 Watchdog Timer
- 13.1 Features
- 13.2 Register Descriptions
- 13.2.1 Timer Counter (TCNT)
- 13.2.2 Timer Control/Status Register (TCSR)
- 13.2.3 Reset Control/Status Register (RSTCSR)
- 13.3 Operation
- 13.3.1 Watchdog Timer Mode
- 13.3.2 Interval Timer Mode
- 13.4 Interrupts
- 13.5 Usage Notes
- 13.5.1 Notes on Register Access
- 13.5.2 Contention between Timer Counter (TCNT)Write and Increment
- 13.5.3 Changing Value of CKS2 to CKS0
- 13.5.4 Switching between Watchdog Timer Mode and Interval Timer Mode
- 13.5.5 Internal Reset in Watchdog Timer Mode
- 13.5.6 OVF Flag Clearing in Intervel Timer Mode
- Section 14 Serial Communication Interface (SCI)
- 14.1 Features
- 14.2 Input/Output Pins
- 14.3 Register Descriptions
- 14.3.1 Receive Shift Register (RSR)
- 14.3.2 Receive Data Register (RDR)
- 14.3.3 Transmit Data Register (TDR)
- 14.3.4 Transmit Shift Register (TSR)
- 14.3.5 Serial Mode Register (SMR)
- 14.3.6 Serial Control Register (SCR)
- 14.3.7 Serial Status Register (SSR)
- 14.3.8 Smart Card Mode Register (SCMR)
- 14.3.9 Bit Rate Register (BRR)
- 14.4 Operation in Asynchronous Mode
- 14.4.1 Data Transfer Format
- 14.4.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode
- 14.4.3 Clock
- 14.4.4 SCI Initialization (Asynchronous Mode)
- 14.4.5 Data Transmission (Asynchronous Mode)
- 14.4.6 Serial Data Reception (Asynchronous Mode)
- 14.5 Multiprocessor Communication Function
- 14.5.1 Multiprocessor Serial Data Transmission
- 14.5.2 Multiprocessor Serial Data Reception
- 14.6 Operation in Clocked Synchronous Mode
- 14.6.1 Clock
- 14.6.2 SCI Initialization (Clocked Synchronous Mode)
- 14.6.3 Serial Data Transmission (Clocked Synchronous Mode)
- 14.6.4 Serial Data Reception (Clocked Synchronous Mode)
- 14.6.5 Simultaneous Serial Data Transmission and Reception (Clocked Synchronous Mode)
- 14.7 Operation in Smart Card Interface
- 14.7.1 Pin Connection Example
- 14.7.2 Data Format (Except for Block Transfer Mode)
- 14.7.3 Block Transfer Mode
- 14.7.4 Receive Data Sampling Timing and Reception Margin in Smart Card Interface Mode
- 14.7.5 Initialization
- 14.7.6 Data Transmission (Except for Block Transfer Mode)
- 14.7.7 Serial Data Reception (Except for Block Transfer Mode)
- 14.7.8 Clock Output Control
- 14.8 Interrupts
- 14.8.1 Interrupts in Normal Serial Communication Interface Mode
- 14.8.2 Interrupts in Smart Card Interface Mode
- 14.9 Usage Notes
- 14.9.1 Module Stop Mode Setting
- 14.9.2 Break Detection and Processing
- 14.9.3 Mark State and Break Detection
- 14.9.4 Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only)
- Section 15 Hitachi Controller Area Network (HCAN)
- 15.1 Features
- 15.2 Input/Output Pins
- 15.3 Register Descriptions
- 15.3.1 Master Control Register (MCR)
- 15.3.2 General Status Register (GSR)
- 15.3.3 Bit Configuration Register (BCR)
- 15.3.4 Mailbox Configuration Register (MBCR)
- 15.3.5 Transmit Wait Register (TXPR)
- 15.3.6 Transmit Wait Cancel Register (TXCR)
- 15.3.7 Transmit Acknowledge Register (TXACK)
- 15.3.8 Abort Acknowledge Register (ABACK)
- 15.3.9 Receive Complete Register (RXPR)
- 15.3.10 Remote Request Register (RFPR)
- 15.3.11 Interrupt Register (IRR)
- 15.3.12 Mailbox Interrupt Mask Register (MBIMR)
- 15.3.13 Interrupt Mask Register (IMR)
- 15.3.14 Receive Error Counter (REC)
- 15.3.15 Transmit Error Counter (TEC)
- 15.3.16 Unread Message Status Register (UMSR)
- 15.3.17 Local Acceptance Filter Masks (LAFML,LAFMH)
- 15.3.18 Message Control (MC0 to MC15)
- 15.3.19 Message Data (MD0 to MD15)
- 15.3.20 HCAN Monitor Register (HCANMON)
- 15.4 Operation
- 15.4.1 Hardware and Software Resets
- 15.4.2 Initialization after Hardware Reset
- 15.4.3 Message Transmission
- 15.4.4 Message Reception
- 15.4.5 HCAN Sleep Mode
- 15.4.6 HCAN Halt Mode
- 15.5 Interrupts
- 15.6 DTC Interface
- 15.7 CAN Bus Interface
- 15.8 Usage Notes
- 15.8.1 Module Stop Mode Setting
- 15.8.2 Reset
- 15.8.3 HCAN Sleep Mode
- 15.8.4 Interrupts
- 15.8.5 Error Counters
- 15.8.6 Register Access
- 15.8.7 HCAN Medium-Speed Mode
- 15.8.8 Register Hold in Standby Modes
- 15.8.9 Usage of Bit Manipulation Instructions
- 15.8.10 HCAN TXCR Operation
- Section 16 A/D Converter
- 16.1 Features
- 16.2 Input/Output Pins
- 16.3 Register Description
- 16.3.1 A/D Data Registers A to D (ADDRA to ADDRD)
- 16.3.2 A/D Control/Status Register (ADCSR)
- 16.3.3 A/D Control Register (ADCR)
- 16.4 Operation
- 16.4.1 Single Mode
- 16.4.2 Scan Mode
- 16.4.3 Input Sampling and A/D Conversion Time
- 16.4.4 External Trigger Input Timing
- 16.5 Interrupts
- 16.6 A/D Conversion Precision Definitions
- 16.7 Usage Notes
- 16.7.1 Module Stop Mode Setting
- 16.7.2 Permissible Signal Source Impedance
- 16.7.3 Influences on Absolute Precision
- 16.7.4 Range of Analog Power Supply and Other Pin Settings
- 16.7.5 Notes on Board Design
- 16.7.6 Notes on Noise Countermeasures
- Section 17 RAM
- Section 18 ROM
- 18.1 Features
- 18.2 Mode Transitions
- 18.3 Block Configuration
- 18.4 Input/Output Pins
- 18.5 Register Descriptions
- 18.5.1 Flash Memory Control Register 1 (FLMCR1)
- 18.5.2 Flash Memory Control Register 2 (FLMCR2)
- 18.5.3 Erase Block Register 1 (EBR1)
- 18.5.4 Erase Block Register 2 (EBR2)
- 18.5.5 RAM Emulation Register (RAMER)
- 18.6 On-Board Programming Modes
- 18.6.1 Boot Mode
- 18.6.2 Programming/Erasing in User Program Mode
- 18.7 Flash Memory Emulation in RAM
- 18.8 Flash Memory Programming/Erasing
- 18.8.1 Program/Program-Verify
- 18.8.2 Erase/Erase-Verify
- 18.8.3 Interrupt Handling when Programming/Erasing Flash Memory
- 18.9 Program/Erase Protection
- 18.9.1 Hardware Protection
- 18.9.2 Software Protection
- 18.9.3 Error Protection
- 18.10 Programmer Mode
- 18.11 Power-Down States for Flash Memory
- Section 19 Clock Pulse Generator
- 19.1 Register Descriptions
- 19.1.1 System Clock Control Register (SCKCR)
- 19.1.2 Low-Power Control Register (LPWRCR)
- 19.2 Oscillator
- 19.2.1 Connecting a Crystal Resonator
- 19.2.2 External Clock Input
- 19.3 PLL Circuit
- 19.4 Medium-Speed Clock Divider
- 19.5 Bus Master Clock Selection Circuit
- 19.6 Usage Notes
- 19.6.1 Note on Crystal Resonator
- 19.6.2 Note on Board Design
- Section 20 Power-Down Modes
- 20.1 Register Descriptions
- 20.1.1 Standby Control Register (SBYCR)
- 20.1.2 Module Stop Control Registers A to C (MSTPCRA to MSTPCRC)
- 20.2 Medium-Speed Mode
- 20.3 Sleep Mode
- 20.3.1 Transition to Sleep Mode
- 20.3.2 Clearing Sleep Mode
- 20.4 Soft are Standby Mode
- 20.4.1 Transition to Software Standby Mode
- 20.4.2 Clearing Software Standby Mode
- 20.4.3 Setting Oscillation Stabilization Time after Clearing Software Standby Mode
- 20.4.4 Soft are Standby Mode Application Example
- 20.5 Hardware Standby Mode
- 20.5.1 Transition to Hardware Standby Mode
- 20.5.2 Clearing Hardware Standby Mode
- 20.5.3 Hardware Standby Mode Timings
- 20.6 Module Stop Mode
- 20.7 Clock Output Disabling Function
- 20.8 Usage Notes
- 20.8.1 I/O Port Status
- 20.8.2 Current Dissipation during Oscillation Stabilization Wait Period
- 20.8.3 DTC Module Stop
- 20.8.4 On-Chip Supporting Module Interrupt
- 20.8.5 Writing to MSTPCR
- Section 21 Electrical Characteristics
- 21.1 Absolute Maximum Ratings
- 21.2 DC Characteristics
- 21.3 AC Characteristics
- 21.3.1 Clock Timing
- 21.3.2 Control Signal Timing
- 21.3.3 Timing of On-Chip Supporting Modules
- 21.4 A/D Conversion Characteristics
- 21.5 Flash Memory Characteristics
- Appendix
- A.On-Chip I/O Register
- A.1 Register Addresses
- A.2 Register Bits
- A.3 Register States in Each Operating Mode
- B.I/O Port States in Each Pin State
- C.Product Code Lineup
- D.Package Dimensions
- Index
- Colophon
Regarding the change of names mentioned in the document, such as Hitachi
Electric and Hitachi XX, to Renesas Technology Corp.
The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas
Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog
and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)
Accordingly, although Hitachi, Hitachi, Ltd., Hitachi Semiconductors, and other Hitachi brand
names are mentioned in the document, these names have in fact all been changed to Renesas
Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and
corporate statement, no changes whatsoever have been made to the contents of the document, and
these changes do not constitute any alteration to the contents of the document itself.
Renesas Technology Home Page: http://www.renesas.com
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
To all our customers
Cautions
Keep safety first in your circuit designs!
1.
Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but
there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire
or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i)
placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or
mishap.
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Hitachi 16-Bit Single-Chip Microcomputer
H8S/2612 Series
H8S/2612
HD6432612
H8S/2611
HD6432611
H8S/2612F-ZTAT
TM
HD64F2612
Hardware Manual
ADE-602-220C
Rev. 4.0
3/18/03
Hitachi, Ltd.
The revision list can be viewed directly by
clicking the title page.
The revision list summarizes the locations of
revisions and additions. Details should always
be checked by referring to the relevant text.
Rev. 4.0, 03/03, Page ii of xxxii
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi's or any third party's
patent, copyright, trademark, or other intellectual property rights for information contained in
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rights, including intellectual property rights, in connection with use of the information
contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you
have received the latest product standards or specifications before final design, purchase or
use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability.
However, contact Hitachi's sales office before using the product in an application that
demands especially high quality and reliability or where its failure or malfunction may directly
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4. Design your application so that the product is used within the ranges guaranteed by Hitachi
particularly for maximum rating, operating supply voltage range, heat radiation characteristics,
installation conditions and other characteristics. Hitachi bears no responsibility for failure or
damage when used beyond the guaranteed ranges. Even within the guaranteed ranges,
consider normally foreseeable failure rates or failure modes in semiconductor devices and
employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi
product does not cause bodily injury, fire or other consequential damage due to operation of
the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document
without written approval from Hitachi.
7. Contact Hitachi's sales office for any questions regarding this document or Hitachi
semiconductor products.
Rev. 4.0, 03/03, Page iii of xxxii
General Precautions on Handling of Product
1. Treatment of NC Pins
Note:
Do not connect anything to the NC pins.
The NC (not connected) pins are either not connected to any of the internal circuitry or are
used as test pins or to reduce noise. If something is connected to the NC pins, the
operation of the LSI is not guaranteed.
2. Treatment of Unused Input Pins
Note:
Fix all unused input pins to high or low level.
Generally, the input pins of CMOS products are high-impedance input pins. If unused pins
are in their open states, intermediate levels are induced by noise in the vicinity, a pass-
through current flows internally, and a malfunction may occur.
3. Processing before Initialization
Note:
When power is first supplied, the product's state is undefined.
The states of internal circuits are undefined until full power is supplied throughout the
chip and a low level is input on the reset pin. During the period where the states are
undefined, the register settings and the output state of each pin are also undefined. Design
your system so that it does not malfunction because of processing while it is in this
undefined state. For those products which have a reset function, reset the LSI immediately
after the power supply has been turned on.
4. Prohibition of Access to Undefined or Reserved Addresses
Note:
Access to undefined or reserved addresses is prohibited.
The undefined or reserved addresses may be used to expand functions, or test registers
may have been be allocated to these addresses. Do not access these registers; the system's
operation is not guaranteed if they are accessed.