Cautions

Keep safety first in your circuit designs!

1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better

and more reliable, but there is always the possibility that trouble may occur with them. Trouble with
semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate
measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or
(iii) prevention against any malfunction or mishap.

Notes regarding these materials

1. These materials are intended as a reference to assist our customers in the selection of the Renesas

Technology Corporation product best suited to the customer's application; they do not convey any
license under any intellectual property rights, or any other rights, belonging to Renesas Technology
Corporation or a third party.

2. Renesas Technology Corporation assumes no responsibility for any damage, or infringement of any

third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or
circuit application examples contained in these materials.

3. All information contained in these materials, including product data, diagrams, charts, programs and

algorithms represents information on products at the time of publication of these materials, and are
subject to change by Renesas Technology Corporation without notice due to product improvements or
other reasons. It is therefore recommended that customers contact Renesas Technology Corporation
or an authorized Renesas Technology Corporation product distributor for the latest product information
before purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors.
Renesas Technology Corporation assumes no responsibility for any damage, liability, or other loss
rising from these inaccuracies or errors.
Please also pay attention to information published by Renesas Technology Corporation by various
means, including the Renesas Technology Corporation Semiconductor home page
(http://www.renesas.com).

4. When using any or all of the information contained in these materials, including product data, diagrams,

charts, programs, and algorithms, please be sure to evaluate all information as a total system before
making a final decision on the applicability of the information and products. Renesas Technology
Corporation assumes no responsibility for any damage, liability or other loss resulting from the
information contained herein.

5. Renesas Technology Corporation semiconductors are not designed or manufactured for use in a device

or system that is used under circumstances in which human life is potentially at stake. Please contact
Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor
when considering the use of a product contained herein for any specific purposes, such as apparatus or
systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use.

6. The prior written approval of Renesas Technology Corporation is necessary to reprint or reproduce in

whole or in part these materials.

7. If these products or technologies are subject to the Japanese export control restrictions, they must be

exported under a license from the Japanese government and cannot be imported into a country other
than the approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the
country of destination is prohibited.

8. Please contact Renesas Technology Corporation for further details on these materials or the products

contained therein.

Rev. 2.0, 04/02, page ii of xliv

Cautions

1. Hitachi neither warrants nor grants licenses of any rights of Hitachi's or any third party's

patent, copyright, trademark, or other intellectual property rights for information contained in
this document. Hitachi bears no responsibility for problems that may arise with third party's
rights, including intellectual property rights, in connection with use of the information
contained in this document.

2. Products and product specifications may be subject to change without notice. Confirm that you

have received the latest product standards or specifications before final design, purchase or
use.

3. Hitachi makes every attempt to ensure that its products are of high quality and reliability.

However, contact Hitachi's sales office before using the product in an application that
demands especially high quality and reliability or where its failure or malfunction may directly
threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear
power, combustion control, transportation, traffic, safety equipment or medical equipment for
life support.

4. Design your application so that the product is used within the ranges guaranteed by Hitachi

particularly for maximum rating, operating supply voltage range, heat radiation characteristics,
installation conditions and other characteristics. Hitachi bears no responsibility for failure or
damage when used beyond the guaranteed ranges. Even within the guaranteed ranges,
consider normally foreseeable failure rates or failure modes in semiconductor devices and
employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi
product does not cause bodily injury, fire or other consequential damage due to operation of
the Hitachi product.

5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document

without written approval from Hitachi.

Contact Hitachi's sales office for any questions regarding this document or Hitachi
semiconductor products.

Rev. 2.0, 04/02, page iii of xliv

General Precautions on Handling of Product

1. Treatment of NC Pins

Note:

Do not connect anything to the NC pins.
The NC (not connected) pins are either not connected to any of the internal circuitry or are
used as test pins or to reduce noise. If something is connected to the NC pins, the
operation of the LSI is not guaranteed.

2. Treatment of Unused Input Pins

Note:

Fix all unused input pins to high or low level.
Generally, the input pins of CMOS products are high-impedance input pins. If unused pins
are in their open states, intermediate levels are induced by noise in the vicinity, a pass-
through current flows internally, and a malfunction may occur.

3. Processing before Initialization

Note:

When power is first supplied, the product's state is undefined.
The states of internal circuits are undefined until full power is supplied throughout the
chip and a low level is input on the reset pin. During the period where the states are
undefined, the register settings and the output state of each pin are also undefined. Design
your system so that it does not malfunction because of processing while it is in this
undefined state. For those products which have a reset function, reset the LSI immediately
after the power supply has been turned on.

4. Prohibition of Access to Undefined or Reserved Addresses

Note:

Access to undefined or reserved addresses is prohibited.
The undefined or reserved addresses may be used to expand functions, or test registers
may have been be allocated to these addresses. Do not access these registers; the system's
operation is not guaranteed if they are accessed.

Rev. 2.0, 04/02, page iv of xliv

Configuration of This Manual

This manual comprises the following items:

1. General Precautions on Handling of Product

2. Configuration of This Manual

3. Preface

4. Contents

5. Overview

6. Description of Functional Modules

CPU and System-Control Modules

On-Chip Peripheral Modules

The configuration of the functional description of each module differs according to the
module. However, the generic style includes the following items:

i) Feature

ii) Input/Output Pin

iii) Register Description

iv) Operation

v) Usage Note

When designing an application system that includes this LSI, take notes into account. Each section
includes notes in relation to the descriptions given, and usage notes are given, as required, as the
final part of each section.

7. List of Registers

8. Electrical Characteristics

9. Appendix

10. Main Revisions and Additions in this Edition (only for revised versions)

The list of revisions is a summary of points that have been revised or added to earlier versions.
This does not include all of the revised contents. For details, see the actual locations in this
manual.

11. Index

Rev. 2.0, 04/02, page v of xliv

Preface

The H8S/2678 Series and H8S/2678R Series are microcomputers (MCU) made up of the
H8S/2600 CPU employing Hitachi's original architecture as their cores, and the peripheral
functions required to configure a system.

The H8S/2600 CPU has an internal 32-bit configuration, sixteen 16-bit general registers, and a
simple and optimized instruction set for high-speed operation. The H8S/2600 CPU can handle a
16-Mbyte linear address space.

This LSI is equipped with direct memory access controller (DMAC and EXDMAC) and data
transfer controller (DTC) bus masters, ROM and RAM memory, a 16-bit timer pulse unit (TPU), a
programmable pulse generator (PPG), an 8-bit timer (TMR), a watchdog timer (WDT), a serial
communication interface (SCI and IrDA), a 10-bit A/D converter, an 8-bit D/A converter, and I/O
ports as on-chip peripheral modules required for system configuration

A high functionality bus controller is also provided, enabling fast and easy connection of DRAM,
SDRAM, and other kinds of memory.

A single-power flash memory (F-ZTAT

*) version and masked ROM version are available for

this LSI's ROM. The F-ZTAT version provides flexibility as it can be reprogrammed in no time to
cope with all situations from the early stages of mass production to full-scale mass production.
This is particularly applicable to application devices with specifications that will most probably
change.

This manual describes this LSI's hardware.

Note: * F-ZTAT

is a trademark of Hitachi, Ltd.

Target Users:

This manual was written for users who will be using this LSI in the design of
application systems. Target users are expected to understand the fundamentals of
electrical circuits, logical circuits, and microcomputers.

Objective:

This manual was written to explain the hardware functions and electrical
characteristics of this LSI to the target users.
Refer to the H8S/2600 Series, H8S/2000 Series Programming Manual for a
detailed description of the instruction set.

Notes on reading this manual:

In order to understand the overall functions of the chip

Read the manual according to the contents. This manual can be roughly categorized into parts
on the CPU, system control functions, peripheral functions and electrical characteristics.

Rev. 2.0, 04/02, page vi of xliv

In order to understand the details of the CPU's functions

Read the H8S/2600 Series, H8S/2000 Series Programming Manual.

In order to understand the details of a register when its name is known

Read the index that is the final part of the manual to find the page number of the entry on the
register. The addresses, bits, and initial values of the registers are summarized in section 23,
List of Registers.

Examples:

The following notation is used for cases when the same or a
similar function, e.g. 16-bit timer pulse unit or serial
communication, is implemented on more than one channel:
XXX_N (XXX is the register name and N is the channel
number)

Bit order:

The MSB is on the left and the LSB is on the right.

Number notation:

Binary is B'xxxx, hexadecimal is H'xxxx, decimal is xxxx.

Signal notation:

An overbar is added to a low-active signal:

[[[[

Related Manuals:

The latest versions of all related manuals are available from our web site.
Please ensure you have the latest versions of all documents you require.
http://www.hitachisemiconductor.com/

H8S/2678 Series and H8S/2678R Series manuals:

Manual Title

ADE No.

H8S/2678 Series,H8S/2678R Series Hardware Manual

This manual

H8S/2600 Series, H8S/2000 Series Programming Manual

ADE-602-083

User's manuals for development tools:

Manual Title

ADE No.

H8S, H8/300 Series C/C++ Compiler, Assembler, Optimizing Linkage Editor
User's Manual

ADE-702-247

H8S, H8/300 Series Simulator/Debugger User's Manual

ADE-702-282

H8S, H8/300 Series Hitachi Embedded Workshop, Hitachi Debugging
Interface Tutorial

ADE-702-231

Hitachi Embedded Workshop User's Manual

ADE-702-201

Rev. 2.0, 04/02, page vii of xliv

Contents

Section 1 Overview ........................................................................................ 1

1.1

Features ....................................................................................................................... 1

1.2

Block Diagram............................................................................................................. 3

1.3

Pin Description ............................................................................................................ 5
1.3.1

Pin Arrangement.............................................................................................. 5

1.3.2

Pin Arrangement in Each Operating Mode ....................................................... 7

1.3.3

Pin Functions................................................................................................... 13

Section 2 CPU................................................................................................ 21

2.1

Features ....................................................................................................................... 21
2.1.1

Differences between H8S/2600 CPU and H8S/2000 CPU................................. 22

2.1.2

Differences from H8/300 CPU ......................................................................... 22

2.1.3

Differences from H8/300H CPU ...................................................................... 23

2.2

CPU Operating Modes ................................................................................................. 23
2.2.1

Normal Mode .................................................................................................. 23

2.2.2

Advanced Mode .............................................................................................. 25

2.3

Address Space.............................................................................................................. 28

2.4

Registers...................................................................................................................... 29
2.4.1

General Registers............................................................................................. 30

2.4.2

Program Counter (PC) ..................................................................................... 31

2.4.3

Extended Register (EXR)................................................................................. 31

2.4.4

Condition-Code Register (CCR)....................................................................... 32

2.4.5

Multiply-Accumulate Register (MAC) ............................................................. 33

2.4.6

Initial Values of CPU Internal Registers........................................................... 33

2.5

Data Formats................................................................................................................33
2.5.1

General Register Data Formats......................................................................... 34

2.5.2

Memory Data Formats ..................................................................................... 36

2.6

Instruction Set............................................................................................................. . 37
2.6.1

Table of Instructions Classified by Function..................................................... 38

2.6.2

Basic Instruction Formats ................................................................................ 47

2.7

Addressing Modes and Effective Address Calculation .................................................. 48
2.7.1

2.7.2

2.7.3

2.7.4

2.7.5

Absolute Address--@aa:8, @aa:16, @aa:24, or @aa:32 .................................. 50

2.7.6

Immediate--#xx:8, #xx:16, or #xx:32 .............................................................. 50

2.7.7

Program-Counter Relative--@(d:8, PC) or @(d:16, PC) .................................. 51

Rev. 2.0, 04/02, page viii of xliv

2.7.8

Memory Indirect--@@aa:8............................................................................. 51

2.7.9

Effective Address Calculation.......................................................................... 52

2.8

Processing States ......................................................................................................... 54

2.9

Usage Note .................................................................................................................. 55
2.9.1

Usage Notes on Bit-wise Operation Instructions............................................... 55

Section 3 MCU Operating Modes .................................................................. 57

3.1

Operating Mode Selection............................................................................................ 57

3.2

Register Descriptions ................................................................................................... 59
3.2.1

Mode Control Register (MDCR)...................................................................... 59

3.2.2

System Control Register (SYSCR)................................................................... 59

3.3

Operating Mode Descriptions....................................................................................... 61
3.3.1

Mode 1............................................................................................................ 61

3.3.2

Mode 2............................................................................................................ 61

3.3.3

Mode 3............................................................................................................ 61

3.3.4

Mode 4............................................................................................................ 61

3.3.5

Mode 5............................................................................................................ 62

3.3.6

Mode 6............................................................................................................ 62

3.3.7

Mode 7............................................................................................................ 62

3.3.8

Mode 10.......................................................................................................... 63

3.3.9

Mode 11.......................................................................................................... 63

3.3.10 Mode 12.......................................................................................................... 63
3.3.11 Mode 13.......................................................................................................... 63
3.3.12 Mode 14.......................................................................................................... 63
3.3.13 Mode 15.......................................................................................................... 63
3.3.14 Pin Functions .................................................................................................. 63

3.4

Memory Map in Each Operating Mode......................................................................... 65

Section 4 Exception Handling........................................................................ 75

4.1

Exception Handling Types and Priority ........................................................................ 75

4.2

Exception Sources and Exception Vector Table ............................................................ 75

4.3

Reset ........................................................................................................................... 77
4.3.1

Reset exception handling ................................................................................. 77

4.3.2

Interrupts after Reset ....................................................................................... 79

4.3.3

On-Chip Peripheral Functions after Reset Release............................................ 79

4.4

Traces.......................................................................................................................... 80

4.5

Interrupts ..................................................................................................................... 80

4.6

Trap Instruction ........................................................................................................... 81

4.7

Stack Status after Exception Handling .......................................................................... 82

4.8

Usage Note .................................................................................................................. 83

Section 5 Interrupt Controller ........................................................................ 85

Rev. 2.0, 04/02, page ix of xliv

5.1

Features ....................................................................................................................... 85

5.2

Input/Output Pins ......................................................................................................... 86

5.3

Register Descriptions ................................................................................................... 87
5.3.1

Interrupt Control Register (INTCR) ................................................................. 87

5.3.2

Interrupt Priority Registers A to K (IPRA to IPRK) .......................................... 88

5.3.3

IRQ Enable Register (IER) .............................................................................. 90

5.3.4

IRQ Sense Control Registers H and L (ISCRH, ISCRL) ................................... 92

5.3.5

IRQ Status Register (ISR) ................................................................................ 97

5.3.6

IRQ Pin Select Register (ITSR)........................................................................ 98

5.3.7

Software Standby Release IRQ Enable Register (SSIER).................................. 100

5.4

Interrupt Sources.......................................................................................................... 100
5.4.1

External Interrupts ........................................................................................... 100

5.4.2

Internal Interrupts ............................................................................................ 101

5.5

Interrupt Exception Handling Vector Table................................................................... 102

5.6

Interrupt Control Modes and Interrupt Operation .......................................................... 107
5.6.1

Interrupt Control Mode 0 ................................................................................. 107

5.6.2

Interrupt Control Mode 2 ................................................................................. 109

5.6.3

Interrupt Exception Handling Sequence ........................................................... 110

5.6.4

Interrupt Response Times ................................................................................ 112

5.6.5

DTC and DMAC Activation by Interrupt ......................................................... 113

5.7

Usage Notes.................................................................................................................116
5.7.1

Contention between Interrupt Generation and Disabling ................................... 116

5.7.2

Instructions that Disable Interrupts................................................................... 117

5.7.3

Times when Interrupts are Disabled ................................................................. 117

5.7.4

Interrupts during Execution of EEPMOV Instruction........................................ 117

5.7.5

Change of IRQ Pin Select Register (ITSR) Setting ........................................... 117

5.7.6

Note on IRQ Status Register (ISR)................................................................... 118

Section 6 Bus Controller (BSC) ..................................................................... 119

6.1

Features ....................................................................................................................... 119

6.2

Input/Output Pins ......................................................................................................... 121

6.3

Register Descriptions ................................................................................................... 123
6.3.1

Bus Width Control Register (ABWCR)............................................................ 124

6.3.2

Access State Control Register (ASTCR)........................................................... 124

6.3.3

Wait Control Registers AH, AL, BH, and BL
(WTCRAH, WTCRAL, WTCRBH, and WTCRBL)......................................... 125

6.3.4

Read Strobe Timing Control Register (RDNCR) .............................................. 130

6.3.5

&6 Assertion Period Control Registers H, L (CSACRH, CSACRL)..................131

6.3.6

Area 0 Burst ROM Interface Control Register (BROMCRH)
Area 1 Burst ROM Interface Control Register (BROMCRL) ............................ 133

6.3.7

Bus Control Register (BCR)............................................................................. 134

6.3.8

DRAM Control Register (DRAMCR) .............................................................. 136

Rev. 2.0, 04/02, page x of xliv

6.3.9

DRAM Access Control Register (DRACCR) ................................................... 143

6.3.10 Refresh Control Register (REFCR) .................................................................. 147
6.3.11 Refresh Timer Counter (RTCNT) .................................................................... 150
6.3.12 Refresh Time Constant Register (RTCOR)....................................................... 150

6.4

Bus Control ................................................................................................................. 150
6.4.1

Area Division .................................................................................................. 150

6.4.2

Bus Specifications ........................................................................................... 152

6.4.3

Memory Interfaces .......................................................................................... 153

6.4.4

Chip Select Signals.......................................................................................... 155

6.5

Basic Bus Interface ...................................................................................................... 156
6.5.1

Data Size and Data Alignment ......................................................................... 156

6.5.2

Valid Strobes................................................................................................... 158

6.5.3

Basic Operation Timing................................................................................... 158

6.5.4

Wait Control ................................................................................................... 166

6.5.5

Read Strobe (

5') Timing................................................................................ 168

6.5.6

Extension of Chip Select (

&6) Assertion Period ............................................... 169

6.6

DRAM Interface .......................................................................................................... 170
6.6.1

Setting DRAM Space ...................................................................................... 170

6.6.2

Address Multiplexing ...................................................................................... 171

6.6.3

Data Bus ......................................................................................................... 172

6.6.4

Pins Used for DRAM Interface ........................................................................ 173

6.6.5

Basic Timing................................................................................................... 174

6.6.6

Column Address Output Cycle Control ............................................................ 175

6.6.7

Row Address Output State Control .................................................................. 176

6.6.8

Precharge State Control ................................................................................... 178

6.6.9

Wait Control ................................................................................................... 179

6.6.10 Byte Access Control ........................................................................................ 182
6.6.11 Burst Operation ............................................................................................... 183
6.6.12 Refresh Control ............................................................................................... 187
6.6.13 DMAC and EXDMAC Single Address Transfer Mode and DRAM Interface.... 192

6.7

Synchronous DRAM Interface ..................................................................................... 195
6.7.1

Setting Continuous Synchronous DRAM Space ............................................... 195

6.7.2

Address Multiplexing ...................................................................................... 196

6.7.3

Data Bus ......................................................................................................... 197

6.7.4

Pins Used for Synchronous DRAM Interface ................................................... 197

6.7.5

Synchronous DRAM Clock ............................................................................. 199

6.7.6

Basic Operation Timing................................................................................... 199

6.7.7

CAS Latency Control ...................................................................................... 201

6.7.8

Row Address Output State Control .................................................................. 203

6.7.9

Precharge State Count ..................................................................................... 205

6.7.10 Bus Cycle Control in Write Cycle .................................................................... 207
6.7.11 Byte Access Control ........................................................................................ 208

Rev. 2.0, 04/02, page xi of xliv

6.7.12 Burst Operation ............................................................................................... 210
6.7.13 Refresh Control ............................................................................................... 214
6.7.14 Mode Register Setting of Synchronous DRAM ................................................ 219
6.7.15 DMAC and EXDMAC Single Address Transfer Mode and

Synchronous DRAM Interface ......................................................................... 221

6.8

Burst ROM Interface.................................................................................................... 226
6.8.1

Basic Timing ................................................................................................... 226

6.8.2

Wait Control.................................................................................................... 228

6.8.3

Write Access ................................................................................................... 228

6.9

Idle Cycle .................................................................................................................... 229
6.9.1

Operation ........................................................................................................ 229

6.9.2

Pin States in Idle Cycle .................................................................................... 245

6.10

Write Data Buffer Function .......................................................................................... 245

6.11

Bus Release ................................................................................................................. 246
6.11.1 Operation ........................................................................................................ 246
6.11.2 Pin States in External Bus Released State......................................................... 248
6.11.3 Transition Timing ............................................................................................ 249

6.12

Bus Arbitration ............................................................................................................251
6.12.1 Operation ........................................................................................................ 251
6.12.2 Bus Transfer Timing........................................................................................ 251

6.13

Bus Controller Operation in Reset ................................................................................ 253

6.14

Usage Notes................................................................................................................. 253
6.14.1 External Bus Release Function and All-Module-Clocks-Stopped Mode ............ 253
6.14.2 External Bus Release Function and Software Standby ...................................... 253
6.14.3 External Bus Release Function and CBR Refreshing/Auto Refreshing .............. 253
6.14.4

%5(42 Output Timing ...................................................................................254

6.14.5 Notes on Usage of the Synchronous DRAM..................................................... 254

Section 7 DMA Controller (DMAC) .............................................................. 255

7.1

Features ....................................................................................................................... 255

7.2

Input/Output Pins ......................................................................................................... 257

7.3

Register Descriptions ................................................................................................... 257
7.3.1

Memory Address Registers (MARA and MARB)............................................. 258

7.3.2

I/O Address Registers (IOARA and IOARB) ................................................... 259

7.3.3

Execute Transfer Count Registers (ETCRA and ETCRB) ................................. 259

7.3.4

DMA Control Registers (DMACRA and DMACRB) ....................................... 261

7.3.5

DMA Band Control Registers H and L (DMABCRH and DMABCRL) ............ 268

7.3.6

DMA Write Enable Register (DMAWER) ....................................................... 279

7.3.7

DMA Terminal Control Register (DMATCR) .................................................. 281

7.4

Activation Sources ....................................................................................................... 282
7.4.1

Activation by Internal Interrupt Request........................................................... 282

7.4.2

Activation by External Request ........................................................................ 283

Rev. 2.0, 04/02, page xii of xliv

7.4.3

Activation by Auto-Request............................................................................. 283

7.5

Operation................................................................................................................... .. 284
7.5.1

Transfer Modes ............................................................................................... 284

7.5.2

Sequential Mode.............................................................................................. 286

7.5.3

Idle Mode........................................................................................................ 288

7.5.4

Repeat Mode ................................................................................................... 290

7.5.5

Single Address Mode....................................................................................... 293

7.5.6

Normal Mode .................................................................................................. 296

7.5.7

Block Transfer Mode....................................................................................... 299

7.5.8

Basic Bus Cycles............................................................................................. 305

7.5.9

DMA Bus Cycles (Dual Address Mode) .......................................................... 305

7.5.10 DMA Bus Cycles (Single Address Mode) ........................................................ 313
7.5.11 Write Data Buffer Function ............................................................................. 319
7.5.12 Multi-Channel Operation ................................................................................. 320
7.5.13 Relation between DMAC and External Bus Requests, Refresh Cycles,

and EXDMAC................................................................................................. 321

7.5.14 DMAC and NMI Interrupts.............................................................................. 322
7.5.15 Forced Termination of DMAC Operation......................................................... 322
7.5.16 Clearing Full Address Mode ............................................................................ 323

7.6

Interrupt Sources.......................................................................................................... 324

7.7

Usage Notes................................................................................................................. 325
7.7.1

DMAC Register Access during Operation........................................................ 325

7.7.2

Module Stop.................................................................................................... 327

7.7.3

Write Data Buffer Function ............................................................................. 327

7.7.4

7(1' Output.................................................................................................. 327

7.7.5

Activation by Falling Edge on

'5(4 Pin ........................................................ 328

7.7.6

Activation Source Acceptance ......................................................................... 329

7.7.7

Internal Interrupt after End of Transfer............................................................. 329

7.7.8

Channel Re-Setting.......................................................................................... 329

Section 8 EXDMA Controller........................................................................ 331

8.1

Features ....................................................................................................................... 331

8.2

Input/Output Pins......................................................................................................... 333

8.3

Register Descriptions ................................................................................................... 334
8.3.1

EXDMA Source Address Register (EDSAR) ................................................... 334

8.3.2

EXDMA Destination Address Register (EDDAR)............................................ 335

8.3.3

EXDMA Transfer Count Register (EDTCR) .................................................... 335

8.3.4

EXDMA Mode Control Register (EDMDR) .................................................... 337

8.3.5

EXDMA Address Control Register (EDACR).................................................. 341

8.4

Operation..................................................................................................................... 345
8.4.1

Transfer Modes ............................................................................................... 345

8.4.2

Address Modes................................................................................................ 346

Rev. 2.0, 04/02, page xiii of xliv

8.4.3

DMA Transfer Requests .................................................................................. 350

8.4.4

Bus Modes ...................................................................................................... 350

8.4.5

Transfer Modes ............................................................................................... 352

8.4.6

Repeat Area Function ...................................................................................... 354

8.4.7

Registers during DMA Transfer Operation ....................................................... 356

8.4.8

Channel Priority Order..................................................................................... 360

8.4.9

EXDMAC Bus Cycles (Dual Address Mode) ................................................... 363

8.4.10 EXDMAC Bus Cycles (Single Address Mode)................................................. 368
8.4.11 Examples of Operation Timing in Each Mode .................................................. 373
8.4.12 Ending DMA Transfer ..................................................................................... 386
8.4.13 Relationship between EXDMAC and Other Bus Masters.................................. 387

8.5

Interrupt Sources.......................................................................................................... 387

8.6

Usage Notes.................................................................................................................390
8.6.1

EXDMAC Register Access during Operation ................................................... 390

8.6.2

Module Stop State ........................................................................................... 390

8.6.3

('5(4 Pin Falling Edge Activation................................................................390

8.6.4

Activation Source Acceptance ......................................................................... 390

8.6.5

Enabling Interrupt Requests when IRF = 1 in EDMDR..................................... 391

8.6.6

(7(1' Pin and CBR Refresh Cycle................................................................391

Section 9 Data Transfer Controller (DTC)...................................................... 393

9.1

Features ....................................................................................................................... 393

9.2

Register Descriptions ................................................................................................... 394
9.2.1

DTC Mode Register A (MRA)......................................................................... 395

9.2.2

DTC Mode Register B (MRB) ......................................................................... 396

9.2.3

DTC Source Address Register (SAR)............................................................... 396

9.2.4

DTC Destination Address Register (DAR) ....................................................... 396

9.2.5

DTC Transfer Count Register A (CRA) ........................................................... 396

9.2.6

DTC Transfer Count Register B (CRB) ............................................................ 397

9.2.7

DTC Enable Registers A to G (DTCERA to DTCERG).................................... 397

9.2.8

DTC Vector Register (DTVECR)..................................................................... 397

9.3

Activation Sources ....................................................................................................... 398

9.4

Location of Register Information and DTC Vector Table .............................................. 399

9.5

Operation..................................................................................................................... 402
9.5.1

Normal Mode .................................................................................................. 404

9.5.2

Repeat Mode ................................................................................................... 405

9.5.3

Block Transfer Mode ....................................................................................... 406

9.5.4

Chain Transfer................................................................................................. 407

9.5.5

Interrupt Sources ............................................................................................. 408

9.5.6

Operation Timing ............................................................................................ 409

9.5.7

Number of DTC Execution States .................................................................... 410

9.6

Procedures for Using DTC ........................................................................................... 411

Rev. 2.0, 04/02, page xiv of xliv

9.6.1

Activation by Interrupt .................................................................................... 411

9.6.2

Activation by Software .................................................................................... 411

9.7

Examples of Use of the DTC........................................................................................ 411
9.7.1

Normal Mode .................................................................................................. 411

9.7.2

Chain Transfer................................................................................................. 412

9.7.3

Chain Transfer when Counter = 0 .................................................................... 413

9.7.4

Software Activation......................................................................................... 414

9.8

Usage Notes................................................................................................................. 415
9.8.1

Module Stop Mode Setting .............................................................................. 415

9.8.2

On-Chip RAM................................................................................................. 415

9.8.3

DTCE Bit Setting ............................................................................................ 415

Section 10 I/O Ports....................................................................................... 417

10.1

Port 1........................................................................................................................... 422
10.1.1 Port 1 Data Direction Register (P1DDR).......................................................... 422
10.1.2 Port 1 Data Register (P1DR)............................................................................ 423
10.1.3 Port 1 Register (PORT1).................................................................................. 423
10.1.4 Pin Functions .................................................................................................. 424

10.2

Port 2........................................................................................................................... 431
10.2.1 Port 2 Data Direction Register (P2DDR).......................................................... 431
10.2.2 Port 2 Data Register (P2DR)............................................................................ 432
10.2.3 Port 2 Register (PORT2).................................................................................. 432
10.2.4 Pin Functions .................................................................................................. 433

10.3

Port 3........................................................................................................................... 441
10.3.1 Port 3 Data Direction Register (P3DDR).......................................................... 442
10.3.2 Port 3 Data Register (P3DR)............................................................................ 442
10.3.3 Port 3 Register (PORT3).................................................................................. 443
10.3.4 Port 3 Open Drain Control Register (P3ODR) .................................................. 443
10.3.5 Port Function Control Register 2 (PFCR2) ....................................................... 444
10.3.6 Pin Functions .................................................................................................. 444

10.4

Port 4........................................................................................................................... 447
10.4.1 Port 4 Register (PORT4).................................................................................. 447
10.4.2 Pin Functions .................................................................................................. 447

10.5

Port 5........................................................................................................................... 448
10.5.1 Port 5 Data Direction Register (P5DDR).......................................................... 449
10.5.2 Port 5 Data Register (P5DR)............................................................................ 449
10.5.3 Port 5 Register (PORT5).................................................................................. 450
10.5.4 Pin Functions .................................................................................................. 450

10.6

Port 6........................................................................................................................... 452
10.6.1 Port 6 Data Direction Register (P6DDR).......................................................... 452
10.6.2 Port 6 Data Register (P6DR)............................................................................ 454
10.6.3 Port 6 Register (PORT6).................................................................................. 454

Rev. 2.0, 04/02, page xv of xliv

10.6.4 Pin Functions................................................................................................... 454

10.7

Port 7........................................................................................................................... 457
10.7.1 Port 7 Data Direction Register (P7DDR) .......................................................... 458
10.7.2 Port 7 Data Register (P7DR) ............................................................................ 458
10.7.3 Port 7 Register (PORT7).................................................................................. 459
10.7.4 Pin Functions................................................................................................... 459

10.8

Port 8........................................................................................................................... 462
10.8.1 Port 8 Data Direction Register (P8DDR) .......................................................... 462
10.8.2 Port 8 Data Register (P8DR) ............................................................................ 463
10.8.3 Port 8 Register (PORT8).................................................................................. 464
10.8.4 Pin Functions................................................................................................... 464

10.9

Port A .......................................................................................................................... 467
10.9.1 Port A Data Direction Register (PADDR) ........................................................ 468
10.9.2 Port A Data Register (PADR) .......................................................................... 469
10.9.3 Port A Register (PORTA) ................................................................................ 469
10.9.4 Port A Pull-Up MOS Control Register (PAPCR) .............................................. 470
10.9.5 Port A Open Drain Control Register (PAODR) ................................................ 470
10.9.6 Port Function Control Register 1 (PFCR1) ....................................................... 470
10.9.7 Pin Functions................................................................................................... 472
10.9.8 Port A Input Pull-Up MOS States..................................................................... 472

10.10 Port B .......................................................................................................................... 473

10.10.1 Port B Data Direction Register (PBDDR)......................................................... 473
10.10.2 Port B Data Register (PBDR)........................................................................... 474
10.10.3 Port B Register (PORTB)................................................................................. 474
10.10.4 Port B Pull-Up MOS Control Register (PBPCR) .............................................. 475
10.10.5 Pin Functions................................................................................................... 475
10.10.6 Port B Input Pull-Up MOS States..................................................................... 475

10.11 Port C .......................................................................................................................... 476

10.11.1 Port C Data Direction Register (PCDDR)......................................................... 476
10.11.2 Port C Data Register (PCDR)........................................................................... 477
10.11.3 Port C Register (PORTC)................................................................................. 477
10.11.4 Port C Pull-Up MOS Control Register (PCPCR) .............................................. 477
10.11.5 Pin Functions................................................................................................... 478
10.11.6 Port C Input Pull-Up MOS States..................................................................... 478

10.12 Port D .......................................................................................................................... 479

10.12.1 Port D Data Direction Register (PDDDR) ........................................................ 479
10.12.2 Port D Data Register (PDDR) .......................................................................... 480
10.12.3 Port D Register (PORTD) ................................................................................ 480
10.12.4 Port D Pull-up Control Register (PDPCR) ........................................................ 481
10.12.5 Pin Functions................................................................................................... 481
10.12.6 Port D Input Pull-Up MOS States..................................................................... 481

10.13 Port E .......................................................................................................................... 482

Rev. 2.0, 04/02, page xvi of xliv

10.13.1 Port E Data Direction Register (PEDDR) ......................................................... 482
10.13.2 Port E Data Register (PEDR) ........................................................................... 483
10.13.3 Port E Register (PORTE)................................................................................. 484
10.13.4 Port E Pull-up Control Register (PEPCR)......................................................... 484
10.13.5 Pin Functions .................................................................................................. 484
10.13.6 Port E Input Pull-Up MOS States..................................................................... 485

10.14 Port F .......................................................................................................................... 485

10.14.1 Port F Data Direction Register (PFDDR) ......................................................... 486
10.14.2 Port F Data Register (PFDR) ........................................................................... 487
10.14.3 Port F Register (PORTF) ................................................................................. 488
10.14.4 Pin Functions .................................................................................................. 488

10.15 Port G.......................................................................................................................... 491

10.15.1 Port G Data Direction Register (PGDDR) ........................................................ 492
10.15.2 Port G Data Register (PGDR) .......................................................................... 493
10.15.3 Port G Register (PORTG) ................................................................................ 493
10.15.4 Port Function Control Register 0 (PFCR0) ....................................................... 494
10.15.5 Pin Functions .................................................................................................. 494

10.16 Port H.......................................................................................................................... 496

10.16.1 Port H Data Direction Register (PHDDR) ........................................................ 497
10.16.2 Port H Data Register (PHDR) .......................................................................... 498
10.16.3 Port H Register (PORTH) ................................................................................ 498
10.16.4 Pin Functions .................................................................................................. 498

Section 11 16-Bit Timer Pulse Unit (TPU)..................................................... 501

11.1

Features ....................................................................................................................... 501

11.2

Input/Output Pins......................................................................................................... 505

11.3

Register Descriptions ................................................................................................... 506
11.3.1 Timer Control Register (TCR) ......................................................................... 507
11.3.2 Timer Mode Register (TMDR) ........................................................................ 513
11.3.3 Timer I/O Control Register (TIOR).................................................................. 514
11.3.4 Timer Interrupt Enable Register (TIER) ........................................................... 532
11.3.5 Timer Status Register (TSR) ............................................................................ 534
11.3.6 Timer Counter (TCNT).................................................................................... 536
11.3.7 Timer General Register (TGR)......................................................................... 537
11.3.8 Timer Start Register (TSTR)............................................................................ 537
11.3.9 Timer Synchronous Register (TSYR)............................................................... 538

11.4

Operation..................................................................................................................... 539
11.4.1 Basic Functions ............................................................................................... 539
11.4.2 Synchronous Operation ................................................................................... 544
11.4.3 Buffer Operation ............................................................................................. 546
11.4.4 Cascaded Operation......................................................................................... 549
11.4.5 PWM Modes ................................................................................................... 551

Rev. 2.0, 04/02, page xvii of xliv

11.4.6 Phase Counting Mode ...................................................................................... 556

11.5

Interrupt Sources..........................................................................................................562

11.6

DTC Activation ........................................................................................................... 564

11.7

DMAC Activation........................................................................................................ 564

11.8

A/D Converter Activation ............................................................................................ 564

11.9

Operation Timing......................................................................................................... 565
11.9.1 Input/Output Timing ........................................................................................ 565
11.9.2 Interrupt Signal Timing.................................................................................... 568

11.10 Usage Notes................................................................................................................. 571

11.10.1 Module Stop Mode Setting .............................................................................. 571
11.10.2 Input Clock Restrictions................................................................................... 571
11.10.3 Caution on Cycle Setting ................................................................................. 572
11.10.4 Contention between TCNT Write and Clear Operations.................................... 572
11.10.5 Contention between TCNT Write and Increment Operations ............................ 573
11.10.6 Contention between TGR Write and Compare Match ....................................... 574
11.10.7 Contention between Buffer Register Write and Compare Match ....................... 574
11.10.8 Contention between TGR Read and Input Capture............................................ 575
11.10.9 Contention between TGR Write and Input Capture........................................... 576
11.10.10 Contention between Buffer Register Write and Input Capture ....................... 576
11.10.11 Contention between Overflow/Underflow and Counter Clearing................... 577
11.10.12 Contention between TCNT Write and Overflow/Underflow.......................... 578
11.10.13 Multiplexing of I/O Pins .............................................................................. 578
11.10.14 Interrupts and Module Stop Mode ................................................................ 578

Section 12 Programmable Pulse Generator (PPG) .......................................... 579

12.1

Features ....................................................................................................................... 579

12.2

Input/Output Pins ......................................................................................................... 581

12.3

Register Descriptions ................................................................................................... 581
12.3.1 Next Data Enable Registers H, L (NDERH, NDERL)....................................... 582
12.3.2 Output Data Registers H, L (PODRH, PODRL) ............................................... 583
12.3.3 Next Data Registers H, L (NDRH, NDRL)....................................................... 584
12.3.4 PPG Output Control Register (PCR) ................................................................ 586
12.3.5 PPG Output Mode Register (PMR) .................................................................. 587

12.4

Operation..................................................................................................................... 589
12.4.1 Output Timing ................................................................................................. 590
12.4.2 Sample Setup Procedure for Normal Pulse Output............................................ 591
12.4.3 Example of Normal Pulse Output (Example of Five-Phase Pulse Output) ......... 592
12.4.4 Non-Overlapping Pulse Output ........................................................................ 593
12.4.5 Sample Setup Procedure for Non-Overlapping Pulse Output............................. 594
12.4.6 Example of Non-Overlapping Pulse Output

(Example of Four-Phase Complementary Non-Overlapping Output)................. 595

12.4.7 Inverted Pulse Output ...................................................................................... 596

Rev. 2.0, 04/02, page xviii of xliv

12.4.8 Pulse Output Triggered by Input Capture ......................................................... 597

12.5

Usage Notes................................................................................................................. 597
12.5.1 Module Stop Mode Setting .............................................................................. 597
12.5.2 Operation of Pulse Output Pins ........................................................................ 597

Section 13 8-Bit Timers (TMR) ..................................................................... 599

13.1

Features ....................................................................................................................... 599

13.2

Input/Output Pins......................................................................................................... 601

13.3

Register Descriptions ................................................................................................... 601
13.3.1 Timer Counter (TCNT).................................................................................... 601
13.3.2 Time Constant Register A (TCORA) ............................................................... 602
13.3.3 Time Constant Register B (TCORB)................................................................ 602
13.3.4 Timer Control Register (TCR) ........................................................................ 602
13.3.5 Timer Control/Status Register (TCSR)............................................................. 604

13.4

Operation..................................................................................................................... 607
13.4.1 Pulse Output.................................................................................................... 607

13.5

Operation Timing......................................................................................................... 608
13.5.1 TCNT Incrementation Timing.......................................................................... 608
13.5.2 Timing of CMFA and CMFB Setting when Compare-Match Occurs ................ 609
13.5.3 Timing of Timer Output when Compare-Match Occurs.................................... 609
13.5.4 Timing of Compare Match Clear...................................................................... 610
13.5.5 Timing of TCNT External Reset ...................................................................... 610
13.5.6 Timing of Overflow Flag (OVF) Setting .......................................................... 611

13.6

Operation with Cascaded Connection ........................................................................... 611
13.6.1 16-Bit Counter Mode....................................................................................... 611
13.6.2 Compare Match Count Mode ........................................................................... 612

13.7

Interrupts ..................................................................................................................... 612
13.7.1 Interrupt Sources and DTC Activation ............................................................. 612
13.7.2 A/D Converter Activation................................................................................ 613

13.8

Usage Notes................................................................................................................. 614
13.8.1 Contention between TCNT Write and Clear ..................................................... 614
13.8.2 Contention between TCNT Write and Increment.............................................. 614
13.8.3 Contention between TCOR Write and Compare Match .................................... 615
13.8.4 Contention between Compare Matches A and B............................................... 616
13.8.5 Switching of Internal Clocks and TCNT Operation .......................................... 617
13.8.6 Mode Setting with Cascaded Connection ......................................................... 619
13.8.7 Interrupts in Module Stop Mode ...................................................................... 619

Section 14 Watchdog Timer .......................................................................... 621

14.1

Features ....................................................................................................................... 621

14.2

Input/Output Pin .......................................................................................................... 622

14.3

Register Descriptions ................................................................................................... 622

Rev. 2.0, 04/02, page xix of xliv

14.3.1 Timer Counter (TCNT).................................................................................... 623
14.3.2 Timer Control/Status Register (TCSR) ............................................................. 623
14.3.3 Reset Control/Status Register (RSTCSR) ......................................................... 625

14.4

Operation..................................................................................................................... 626
14.4.1 Watchdog Timer Mode .................................................................................... 626
14.4.2 Interval Timer Mode........................................................................................ 627

14.5

Interrupt Source ...........................................................................................................628

14.6

Usage Notes................................................................................................................. 628
14.6.1 Notes on Register Access................................................................................. 628
14.6.2 Contention between Timer Counter (TCNT) Write and Increment .................... 629
14.6.3 Changing Value of CKS2 to CKS0 .................................................................. 630
14.6.4 Switching between Watchdog Timer Mode and Interval Timer Mode ............... 630
14.6.5 Internal Reset in Watchdog Timer Mode .......................................................... 630
14.6.6 System Reset by

:'729) Signal...................................................................631

Section 15 Serial Communication Interface (SCI, IrDA) ................................633

15.1

Features ....................................................................................................................... 633

15.2

Input/Output Pins ......................................................................................................... 635

15.3

Register Descriptions ................................................................................................... 636
15.3.1 Receive Shift Register (RSR)........................................................................... 637
15.3.2 Receive Data Register (RDR) .......................................................................... 637
15.3.3 Transmit Data Register (TDR) ......................................................................... 637
15.3.4 Transmit Shift Register (TSR).......................................................................... 638
15.3.5 Serial Mode Register (SMR) ............................................................................ 638
15.3.6 Serial Control Register (SCR) .......................................................................... 641
15.3.7 Serial Status Register (SSR)............................................................................. 644
15.3.8 Smart Card Mode Register (SCMR)................................................................. 648
15.3.9 Bit Rate Register (BRR) .................................................................................. 649
15.3.10 IrDA Control Register (IrCR) .......................................................................... 658
15.3.11 Serial Extension Mode Register (SEMR) ......................................................... 659

15.4

Operation in Asynchronous Mode ................................................................................ 661
15.4.1 Data Transfer Format....................................................................................... 661
15.4.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode 663
15.4.3 Clock .............................................................................................................. 664
15.4.4 SCI Initialization (Asynchronous Mode) .......................................................... 665
15.4.5 Data Transmission (Asynchronous Mode) ........................................................ 666
15.4.6 Serial Data Reception (Asynchronous Mode) ................................................... 668

15.5

Multiprocessor Communication Function ..................................................................... 672
15.5.1 Multiprocessor Serial Data Transmission ......................................................... 674
15.5.2 Multiprocessor Serial Data Reception .............................................................. 676

15.6

Operation in Clocked Synchronous Mode ..................................................................... 679
15.6.1 Clock .............................................................................................................. 679

Rev. 2.0, 04/02, page xx of xliv

15.6.2 SCI Initialization (Clocked Synchronous Mode)............................................... 680
15.6.3 Serial Data Transmission (Clocked Synchronous Mode) .................................. 681
15.6.4 Serial Data Reception (Clocked Synchronous Mode)........................................ 684
15.6.5 Simultaneous Serial Data Transmission and Reception

(Clocked Synchronous Mode).......................................................................... 686

15.7

Operation in Smart Card Interface Mode ...................................................................... 688
15.7.1 Pin Connection Example ................................................................................. 688
15.7.2 Data Format (Except for Block Transfer Mode) ............................................... 688
15.7.3 Block Transfer Mode....................................................................................... 690
15.7.4 Receive Data Sampling Timing and Reception Margin..................................... 690
15.7.5 Initialization .................................................................................................... 691
15.7.6 Data Transmission (Except for Block Transfer Mode) ...................................... 692
15.7.7 Serial Data Reception (Except for Block Transfer Mode) ................................. 695
15.7.8 Clock Output Control ...................................................................................... 696

15.8

IrDA Operation............................................................................................................ 698

15.9

Interrupt Sources.......................................................................................................... 701
15.9.1 Interrupts in Normal Serial Communication Interface Mode ............................. 701
15.9.2 Interrupts in Smart Card Interface Mode .......................................................... 702

15.10 Usage Notes............................................................................................................... .. 703

15.10.1 Module Stop Mode Setting .............................................................................. 703
15.10.2 Break Detection and Processing ....................................................................... 703
15.10.3 Mark State and Break Sending ......................................................................... 703
15.10.4 Receive Error Flags and Transmit Operations

(Clocked Synchronous Mode Only) ................................................................. 703

15.10.5 Relation between Writes to TDR and the TDRE Flag ....................................... 703
15.10.6 Restrictions on Use of DMAC or DTC............................................................. 704
15.10.7 Operation in Case of Mode Transition.............................................................. 704

Section 16 A/D Converter.............................................................................. 709

16.1

Features ....................................................................................................................... 709

16.2

Input/Output Pins......................................................................................................... 710

16.3

Register Descriptions ................................................................................................... 711
16.3.1 A/D Data Registers A to H (ADDRA to ADDRH) ........................................... 712
16.3.2 A/D Control/Status Register (ADCSR) ............................................................ 713
16.3.3 A/D Control Register (ADCR)......................................................................... 718

16.4

Operation..................................................................................................................... 720
16.4.1 Single Mode .................................................................................................... 720
16.4.2 Scan Mode ...................................................................................................... 720
16.4.3 Input Sampling and A/D Conversion Time....................................................... 721
16.4.4 External Trigger Input Timing ......................................................................... 723

16.5

Interrupt Source ........................................................................................................... 724

16.6

A/D Conversion Accuracy Definitions ......................................................................... 724

Rev. 2.0, 04/02, page xxi of xliv

16.7

Usage Notes................................................................................................................. 726
16.7.1 Module Stop Mode Setting .............................................................................. 726
16.7.2 Permissible Signal Source Impedance .............................................................. 726
16.7.3 Influences on Absolute Precision ..................................................................... 727
16.7.4 Setting Range of Analog Power Supply and Other Pins .................................... 727
16.7.5 Notes on Board Design .................................................................................... 728
16.7.6 Notes on Noise Countermeasures ..................................................................... 728

Section 17 D/A Converter .............................................................................. 731

17.1

Features ....................................................................................................................... 731

17.2

Input/Output Pins ......................................................................................................... 732

17.3

Register Descriptions ................................................................................................... 733
17.3.1 D/A Data Registers 0 to 3 (DADR0 to DADR3)............................................... 733
17.3.2 D/A Control Registers 01 and 23 (DACR01, DACR23).................................... 733

17.4

Operation..................................................................................................................... 737

17.5

Usage Notes................................................................................................................. 738
17.5.1 Setting for Module Stop Mode ......................................................................... 738
17.5.2 D/A Output Hold Function in Software Standby Mode ..................................... 738

Section 18 RAM ............................................................................................ 739

Section 19 Flash Memory (F-ZTAT Version)................................................. 741

19.1

Features ....................................................................................................................... 741

19.2

Mode Transitions ......................................................................................................... 742

19.3

Block Configuration..................................................................................................... 746

19.4

Input/Output Pins ......................................................................................................... 749

19.5

Register Descriptions ................................................................................................... 749
19.5.1 Flash Memory Control Register 1 (FLMCR1) .................................................. 749
19.5.2 Flash Memory Control Register 2 (FLMCR2) .................................................. 751
19.5.3 Erase Block Register 1 (EBR1) ........................................................................ 751
19.5.4 Erase Block Register 2 (EBR2) ........................................................................ 752
19.5.5 RAM Emulation Register (RAMER)................................................................ 754

19.6

On-Board Programming Modes.................................................................................... 756
19.6.1 Boot Mode ...................................................................................................... 756
19.6.2 User Program Mode......................................................................................... 759

19.7

Flash Memory Emulation in RAM................................................................................ 760

19.8

Flash Memory Programming/Erasing ........................................................................... 762
19.8.1 Program/Program-Verify ................................................................................. 762
19.8.2 Erase/Erase-Verify........................................................................................... 764
19.8.3 Interrupt Handling when Programming/Erasing Flash Memory......................... 764

19.9

Program/Erase Protection ............................................................................................. 766
19.9.1 Hardware Protection ........................................................................................ 766

Rev. 2.0, 04/02, page xxii of xliv

19.9.2 Software Protection ......................................................................................... 766
19.9.3 Error Protection............................................................................................... 766

19.10 Programmer Mode ....................................................................................................... 767
19.11 Power-Down States for Flash Memory ......................................................................... 767
19.12 Usage Notes................................................................................................................. 767
19.13 Note on Switching from F-ZTAT Version to Masked ROM Version............................. 773

Section 20 Masked ROM............................................................................... 775

Section 21 Clock Pulse Generator.................................................................. 777

21.1

Register Descriptions ................................................................................................... 777
21.1.1 System Clock Control Register (SCKCR) ........................................................ 777
21.1.2 PLL Control Register (PLLCR) ....................................................................... 779

21.2

Oscillator ..................................................................................................................... 779
21.2.1 Connecting a Crystal Resonator ....................................................................... 780
21.2.2 External Clock Input........................................................................................ 781

21.3

PLL Circuit.................................................................................................................. 782

21.4

Frequency Divider ....................................................................................................... 783

21.5

Usage Notes................................................................................................................. 783
21.5.1 Notes on Clock Pulse Generator....................................................................... 783
21.5.2 Notes on Resonator ......................................................................................... 783
21.5.3 Notes on Board Design .................................................................................... 784

Section 22 Power-Down Modes..................................................................... 785

22.1

Register Descriptions ................................................................................................... 788
22.1.1 Standby Control Register (SBYCR) ................................................................. 788
22.1.2 Module Stop Control Registers H and L (MSTPCRH, MSTPCRL) .................. 790

22.2

Operation..................................................................................................................... 791
22.2.1 Clock Division Mode....................................................................................... 791
22.2.2 Sleep Mode ..................................................................................................... 791
22.2.3 Software Standby Mode................................................................................... 792
22.2.4 Hardware Standby Mode ................................................................................. 794
22.2.5 Module Stop Mode .......................................................................................... 795
22.2.6 All-Module-Clocks-Stop Mode........................................................................ 796

22.3

ø Clock Output Control ................................................................................................ 796

22.4

Usage Notes................................................................................................................. 797
22.4.1 I/O Port Status................................................................................................. 797
22.4.2 Current Dissipation during Oscillation Stabilization Standby Period ................. 797
22.4.3 EXDMAC/DMAC/DTC Module Stop ............................................................. 797
22.4.4 On-Chip Peripheral Module Interrupts ............................................................. 797
22.4.5 Writing to MSTPCR........................................................................................ 797

Rev. 2.0, 04/02, page xxiii of xliv

Section 23 List of Registers............................................................................ 799

23.1

23.2

Register Bits ................................................................................................................ 811

23.3

Section 24 Electrical Characteristics............................................................... 835

24.1

Absolute Maximum Ratings ......................................................................................... 835

24.2

DC Characteristics ....................................................................................................... 836

24.3

AC Characteristics ....................................................................................................... 840

24.4

A/D Conversion Characteristics.................................................................................... 876

24.5

D/A Conversion Characteristics.................................................................................... 876

24.6

Flash Memory Characteristics ...................................................................................... 877

24.7

Usage Note .................................................................................................................. 879

Appendix

.....................................................................................................881

I/O Port States in Each Pin State................................................................................... 881

Product Lineup............................................................................................................. 890

Package Dimensions .................................................................................................... 891

Main Revisions and Additions in this Edition................................................... 893

Index

..................................................................................................... 901

Rev. 2.0, 04/02, page xxv of xliv

Figures

Section 1 Overview
Figure 1.1 H8S/2678 Series Internal Block Diagram ..................................................................3
Figure 1.2 H8S/2678R Series Internal Block Diagram................................................................4
Figure 1.3 H8S/2678 Series Pin Arrangement ............................................................................5
Figure 1.4 H8S/2678R Series Pin Arrangement..........................................................................6
Section 2 CPU
Figure 2.1 Exception Vector Table (Normal Mode)..................................................................25
Figure 2.2 Stack Structure in Normal Mode .............................................................................25
Figure 2.3 Exception Vector Table (Advanced Mode) ..............................................................26
Figure 2.4 Stack Structure in Advanced Mode..........................................................................27
Figure 2.5 Memory Map ..........................................................................................................28
Figure 2.6 CPU Registers ........................................................................................................29
Figure 2.7 Usage of General Registers .....................................................................................30
Figure 2.8 Stack ......................................................................................................................31
Figure 2.9 General Register Data Formats (1) ..........................................................................34
Figure 2.9 General Register Data Formats (2) ..........................................................................35
Figure 2.10 Memory Data Formats ..........................................................................................36
Figure 2.11 Instruction Formats (Examples).............................................................................48
Figure 2.12 Branch Address Specification in Memory Indirect Mode .......................................51
Figure 2.13 State Transitions ...................................................................................................55
Section 3 MCU Operating Modes
Figure 3.1 H8S/2676 Memory Map (1) ....................................................................................65
Figure 3.1 H8S/2676 Memory Map (2) ....................................................................................66
Figure 3.1 H8S/2676 Memory Map (3) ....................................................................................67
Figure 3.1 H8S/2676 Memory Map (4) ....................................................................................68
Figure 3.2 H8S/2675 Memory Map (1) ....................................................................................69
Figure 3.2 H8S/2675 Memory Map (2) ....................................................................................70
Figure 3.3 H8S/2673 Memory Map (1) ....................................................................................71
Figure 3.3 H8S/2673 Memory Map (2) ....................................................................................72
Figure 3.4 H8S/2670 Memory Map..........................................................................................73
Figure 3.5 H8S/2674R Memory Map .......................................................................................74
Section 4 Exception Handling
Figure 4.1 Reset Sequence (Advanced Mode with On-chip ROM Enabled) ..............................78
Figure 4.2 Reset Sequence (Advanced Mode with On-chip ROM Disabled) .............................79
Figure 4.3 Stack Status after Exception Handling .....................................................................82
Figure 4.4 Operation when SP Value Is Odd ............................................................................83
Section 5 Interrupt Controller
Figure 5.1 Block Diagram of Interrupt Controller.....................................................................86
Figure 5.2 Block Diagram of Interrupts IRQ15 to IRQ0 .........................................................101
Figure 5.3 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 0...108

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Figure 5.4 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 2 .. 110
Figure 5.5 Interrupt Exception Handling ................................................................................ 111
Figure 5.6 DTC, DMAC, and Interrupt Controller.................................................................. 114
Figure 5.7 Contention between Interrupt Generation and Disabling ........................................ 116
Section 6 Bus Controller (BSC)
Figure 6.1 Block Diagram of Bus Controller .......................................................................... 120
Figure 6.2 Read Strobe Negation Timing (Example of 3-State Access Space)......................... 130
Figure 6.3 CS and Address Assertion Period Extension

(Example of 3-State Access Space and RDNn = 0)................................................. 132

Figure 6.4 RAS Signal Assertion Timing

(2-State Column Address Output Cycle, Full Access) ............................................ 142

Figure 6.5 CAS Latency Control Cycle Disable Timing during Continuous

Synchronous DRAM Space Write Access (for CAS Latency 2).............................. 147

Figure 6.6 Area Divisions...................................................................................................... 151
Figure 6.7 CSn Signal Output Timing (n = 0 to 7) .................................................................. 156
Figure 6.8 Access Sizes and Data Alignment Control (8-Bit Access Space) ............................ 157
Figure 6.9 Access Sizes and Data Alignment Control (16-bit Access Space)........................... 157
Figure 6.10 Bus Timing for 8-Bit, 2-State Access Space ........................................................ 159
Figure 6.11 Bus Timing for 8-Bit, 3-State Access Space ........................................................ 160
Figure 6.12 Bus Timing for 16-Bit, 2-State Access Space (Even Address Byte Access) .......... 161
Figure 6.13 Bus Timing for 16-Bit, 2-State Access Space (Odd Address Byte Access) ........... 162
Figure 6.14 Bus Timing for 16-Bit, 2-State Access Space (Word Access)............................... 163
Figure 6.15 Bus Timing for 16-Bit, 3-State Access Space (Even Address Byte Access) .......... 164
Figure 6.16 Bus Timing for 16-Bit, 3-State Access Space (Odd Address Byte Access) ........... 165
Figure 6.17 Bus Timing for 16-Bit, 3-State Access Space (Word Access)............................... 166
Figure 6.18 Example of Wait State Insertion Timing .............................................................. 168
Figure 6.19 Example of Read Strobe Timing.......................................................................... 169
Figure 6.20 Example of Timing when Chip Select Assertion Period is Extended .................... 170
Figure 6.21 DRAM Basic Access Timing (RAST = 0, CAST = 0).......................................... 174
Figure 6.22 Example of Access Timing with 3-State Column Address Output Cycle

(RAST = 0) ......................................................................................................... 175

Figure 6.23 Example of Access Timing when RAS Signal Goes Low from

Beginning of T

State (CAST = 0) ....................................................................... 176

Figure 6.24 Example of Timing with One Row Address Output Maintenance State

(RAST = 0, CAST = 0)........................................................................................ 177

Figure 6.25 Example of Timing with Two-State Precharge Cycle (RAST = 0, CAST = 0) ...... 178
Figure 6.26 Example of Wait State Insertion Timing (2-State Column Address Output).......... 180
Figure 6.27 Example of Wait State Insertion Timing (3-State Column Address Output).......... 181
Figure 6.28 2-CAS Control Timing (Upper Byte Write Access: RAST = 0, CAST = 0) ......... 182
Figure 6.29 Example of 2-CAS DRAM Connection ............................................................... 183
Figure 6.30 Operation Timing in Fast Page Mode (RAST = 0, CAST = 0).............................. 184
Figure 6.31 Operation Timing in Fast Page Mode (RAST = 0, CAST = 1).............................. 185
Figure 6.32 Example of Operation Timing in RAS Down Mode (RAST = 0, CAST = 0) ........ 186

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Figure 6.33 Example of Operation Timing in RAS Up Mode (RAST = 0, CAST = 0) .............187
Figure 6.34 RTCNT Operation ..............................................................................................188
Figure 6.35 Compare Match Timing ......................................................................................188
Figure 6.36 CBR Refresh Timing...........................................................................................189
Figure 6.37 CBR Refresh Timing (RCW1 = 0, RCW0 = 1, RLW1 = 0, RLW0 = 0) ................189
Figure 6.38 Example of CBR Refresh Timing (CBRM = 1)....................................................190
Figure 6.39 Self-Refresh Timing............................................................................................191
Figure 6.40 Example of Timing when Precharge Time after Self-Refreshing Is Extended

by 2 States..........................................................................................................192

Figure 6.41 Example of DACK/EDACK Output Timing when DDS = 1 or EDDS = 1

(RAST = 0, CAST = 0)........................................................................................193

Figure 6.42 Example of DACK/EDACK Output Timing when DDS = 0 or EDDS = 0

(RAST = 0, CAST = 1)........................................................................................194

Figure 6.43 Relationship between

and SDRAM

(when PLL frequency multiplication factor is

1 or

2)........................................199

Figure 6.44 Basic Access Timing of Synchronous DRAM (CAS Latency 1)...........................200
Figure 6.45 CAS Latency Control Timing (SDWCD = 0, CAS Latency 3)..............................202
Figure 6.46 Example of Access Timing when Row Address Output Hold State is 1 State

(RCD1 = 0, RCD0 = 1, SDWCD = 0, CAS Latency 2) .........................................204

Figure 6.47 Example of Timing with Two-State Precharge Cycle

(TPC1 = 0, TPC0 = 1, SDWCD = 0, CAS Latency 2)...........................................206

Figure 6.48 Example of Write Access Timing when CAS Latency Control Cycle is Disabled

(SDWCD = 1) .....................................................................................................207

Figure 6.49 DQMU and DQML Control Timing

(Upper Byte Write Access: SDWCD = 0, CAS Latency 2) ...................................208

Figure 6.50 DQMU and DQML Control Timing (Lower Byte Read Access: CAS Latency 2) .209
Figure 6.51 Example of DQMU and DQML Byte Control......................................................210
Figure 6.52 Operation Timing of Burst Access (BE = 1, SDWCD = 0, CAS Latency 2) .........212
Figure 6.53 Example of Operation Timing in RAS Down Mode (BE = 1, CAS Latency 2).....213
Figure 6.54 Auto Refresh Timing...........................................................................................215
Figure 6.55 Auto Refresh Timing (TPC = 1, TPC0 = 1, RCW1 = 0, RCW0 = 1) ....................216
Figure 6.56 Auto Refresh Timing (TPC = 0, TPC0 = 0, RLW1 = 0, RLW0 = 1) ....................217
Figure 6.57 Self-Refresh Timing

(TPC1 = 1, TPC0 = 0, RCW1 = 0, RCW0 = 0, RLW1 = 0, RLW0 = 0).................218

Figure 6.58 Example of Timing when Precharge Time after Self-Refreshing Is Extended

by 2 States (TPCS2 to TPCS0 = H'2, TPC1 = 0, TPC0 = 0, CAS Latency 2)........219

Figure 6.59 Synchronous DRAM Mode Setting Timing .........................................................220
Figure 6.60 Example of DACK/EDACK Output Timing when DDS = 1 or EDDS = 1............222
Figure 6.61 Example of DACK/EDACK Output Timing when DDS = 0 or EDDS = 0............224
Figure 6.62 Example of Timing when the Read Data is Extended by Two States

(DDS = 1, or EDDS = 1, RDXC1 = 0, RDXC0 = 1, CAS Latency 2) ....................225

Figure 6.63 Example of Burst ROM Access Timing (ASTn = 1, 2-State Burst Cycle) .............227
Figure 6.64 Example of Burst ROM Access Timing (ASTn = 0, 1-State Burst Cycle) .............228

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Figure 6.65 Example of Idle Cycle Operation (Consecutive Reads in Different Areas)............ 229
Figure 6.66 Example of Idle Cycle Operation (Write after Read)............................................ 230
Figure 6.67 Example of Idle Cycle Operation (Read after Write)............................................ 231
Figure 6.68 Relationship between Chip Select (CS) and Read (RD)........................................ 232
Figure 6.69 Example of DRAM Full Access after External Read (CAST = 0)......................... 232
Figure 6.70 Example of Idle Cycle Operation in RAS Down Mode

(Consecutive Reads in Different Areas) (IDLC = 0, RAST = 0, CAST = 0) ......... 233

Figure 6.71 Example of Idle Cycle Operation in RAS Down Mode (Write after Read)

(IDLC = 0, RAST = 0, CAST = 0) ...................................................................... 233

Figure 6.72 Example of Synchronous DRAM Full Access after External Read

(CAS Latency 2) ................................................................................................ 234

Figure 6.73 Example of Idle Cycle Operation in RAS Down Mode (Read in Different Area)

(IDLC = 0, CAS Latency 2)................................................................................. 235

Figure 6.74 Example of Idle Cycle Operation in RAS Down Mode (Read in Different Area)

(IDLC = 1, CAS Latency 2)................................................................................. 236

Figure 6.75 Example of Idle Cycle Operation in RAS Down Mode (Write after Read)

(IDLC = 0, CAS Latency 2)................................................................................. 237

Figure 6.76 Example of Idle Cycle Operation after DRAM Access

(Consecutive Reads in Different Areas) (IDLC = 0, RAST = 0, CAST = 0) .......... 238

Figure 6.77 Example of Idle Cycle Operation after DRAM Access (Write after Read)

(IDLC = 0, RAST = 0, CAST = 0) ....................................................................... 238

Figure 6.78 Example of Idle Cycle Operation after DRAM Write Access

(IDLC = 0, ICIS1 = 0, RAST = 0, CAST = 0) ...................................................... 239

Figure 6.79 Example of Idle Cycle Operation after Continuous

Synchronous DRAM Space Read Access (Read between Different Area)
(IDLC = 0, CAS Latency 2)................................................................................. 240

Figure 6.80 Example of Idle Cycle Operation after Continuous

Synchronous DRAM Space Write Access
(IDLC = 0, ICIS1 = 0, SDWCD = 1, CAS Latency 2) ......................................... 241

Figure 6.81 Example of Timing for Idle Cycle Insertion in Case of Consecutive Read and

Write Accesses to DRAM Space in RAS Down Mode ......................................... 243

Figure 6.82 Example of Timing for Idle Cycle Insertion in Case of Consecutive Read and

Write Accesses to Continuous Synchronous DRAM Space in RAS Down Mode
(SDWCD = 1, CAS Latency 2) ............................................................................ 244

Figure 6.83 Example of Timing when Write Data Buffer Function is Used............................. 246
Figure 6.84 Bus Released State Transition Timing ................................................................. 249
Figure 6.85 Bus Release State Transition Timing when Synchronous DRAM Interface .......... 250
Section 7 DMA Controller (DMAC)
Figure 7.1 Block Diagram of DMAC ..................................................................................... 256
Figure 7.2 Areas for Register Re-Setting by DTC (Channel 0A)............................................. 280
Figure 7.3 Operation in Sequential Mode ............................................................................... 287
Figure 7.4 Example of Sequential Mode Setting Procedure .................................................... 288
Figure 7.5 Operation in Idle Mode ......................................................................................... 289

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Figure 7.6 Example of Idle Mode Setting Procedure...............................................................290
Figure 7.7 Operation in Repeat mode .....................................................................................292
Figure 7.8 Example of Repeat Mode Setting Procedure ..........................................................293
Figure 7.9 Operation in Single Address Mode (When Sequential Mode is Specified) ..............295
Figure 7.10 Example of Single Address Mode Setting Procedure

(When Sequential Mode is Specified) ..................................................................296

Figure 7.11 Operation in Normal Mode..................................................................................298
Figure 7.12 Example of Normal Mode Setting Procedure .......................................................299
Figure 7.13 Operation in Block Transfer Mode (BLKDIR = 0) ...............................................301
Figure 7.14 Operation in Block Transfer Mode (BLKDIR = 1) ...............................................302
Figure 7.15 Operation Flow in Block Transfer Mode..............................................................303
Figure 7.16 Example of Block Transfer Mode Setting Procedure ............................................304
Figure 7.17 Example of DMA Transfer Bus Timing...............................................................305
Figure 7.18 Example of Short Address Mode Transfer ...........................................................306
Figure 7.19 Example of Full Address Mode Transfer (Cycle Steal).........................................307
Figure 7.20 Example of Full Address Mode Transfer (Burst Mode) ........................................308
Figure 7.21 Example of Full Address Mode Transfer (Block Transfer Mode) .........................309
Figure 7.22 Example of DREQ Pin Falling Edge Activated Normal Mode Transfer ................310
Figure 7.23 Example of DREQ Pin Falling Edge Activated Block Transfer Mode Transfer.....311
Figure 7.24 Example of DREQ Pin Low Level Activated Normal Mode Transfer ...................312
Figure 7.25 Example of DREQ Pin Low Level Activated Block Transfer Mode Transfer........313
Figure 7.26 Example of Single Address Mode Transfer (Byte Read).......................................314
Figure 7.27 Example of Single Address Mode (Word Read) Transfer .....................................314
Figure 7.28 Example of Single Address Mode Transfer (Byte Write)......................................315
Figure 7.29 Example of Single Address Mode Transfer (Word Write) ....................................316
Figure 7.30 Example of DREQ Pin Falling Edge Activated Single Address Mode Transfer.....317
Figure 7.31 Example of DREQ Pin Low Level Activated Single Address Mode Transfer .......318
Figure 7.32 Example of Dual Address Transfer Using Write Data Buffer Function .................319
Figure 7.33 Example of Single Address Transfer Using Write Data Buffer Function...............320
Figure 7.34 Example of Multi-Channel Transfer ....................................................................321
Figure 7.35 Example of Procedure for Continuing Transfer on Channel Interrupted

by NMI Interrupt .................................................................................................322

Figure 7.36 Example of Procedure for Forcibly Terminating DMAC Operation......................323
Figure 7.37 Example of Procedure for Clearing Full Address Mode........................................324
Figure 7.38 Block Diagram of Transfer End/Transfer Break Interrupt.....................................325
Figure 7.39 DMAC Register Update Timing ..........................................................................326
Figure 7.40 Contention between DMAC Register Update and CPU Read ...............................326
Figure 7.41 Example in Which Low Level is Not Output at TEND Pin...................................328
Section 8 EXDMA Controller
Figure 8.1 Block Diagram of EXDMAC ................................................................................332
Figure 8.2 Example of Timing in Dual Address Mode............................................................347
Figure 8.3 Data Flow in Single Address Mode .......................................................................348
Figure 8.4 Example of Timing in Single Address Mode..........................................................349

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Figure 8.5 Example of Timing in Cycle Steal Mode ............................................................... 351
Figure 8.6 Examples of Timing in Burst Mode....................................................................... 352
Figure 8.7 Examples of Timing in Normal Transfer Mode...................................................... 353
Figure 8.8 Example of Timing in Block Transfer Mode.......................................................... 354
Figure 8.9 Example of Repeat Area Function Operation......................................................... 355
Figure 8.10 Example of Repeat Area Function Operation in Block Transfer Mode.................. 356
Figure 8.11 EDTCR Update Operations in Normal Transfer Mode and Block Transfer Mode 358
Figure 8.12 Procedure for Changing Register Settings in Operating Channel .......................... 359
Figure 8.13 Example of Channel Priority Timing ................................................................... 361
Figure 8.14 Examples of Channel Priority Timing.................................................................. 362
Figure 8.15 Example of Normal Transfer Mode (Cycle Steal Mode) Transfer......................... 363
Figure 8.16 Example of Normal Transfer Mode (Burst Mode) Transfer .................................. 364
Figure 8.17 Example of Block Transfer Mode (Cycle Steal Mode) Transfer ........................... 364
Figure 8.18 Example of Normal Mode Transfer Activated by EDREQ Pin Falling Edge......... 365
Figure 8.19 Example of Block Transfer Mode Transfer Activated

by EDREQ Pin Falling Edge............................................................................... 366

Figure 8.20 Example of Normal Mode Transfer Activated by EDREQ Pin Low Level............ 367
Figure 8.21 Example of Block Transfer Mode Transfer Activated by EDREQ Pin Low Level 368
Figure 8.22 Example of Single Address Mode (Byte Read) Transfer ...................................... 369
Figure 8.23 Example of Single Address Mode (Word Read) Transfer..................................... 369
Figure 8.24 Example of Single Address Mode (Byte Write) Transfer ..................................... 370
Figure 8.25 Example of Single Address Mode (Word Write) Transfer .................................... 370
Figure 8.26 Example of Single Address Mode Transfer Activated

by EDREQ Pin Falling Edge............................................................................... 371

Figure 8.27 Example of Single Address Mode Transfer Activated

by EDREQ Pin Low Level ................................................................................. 372

Figure 8.28 Auto Request/Cycle Steal Mode/Normal Transfer Mode

(No Contention/Dual Address Mode)................................................................... 373

Figure 8.29 Auto Request/Cycle Steal Mode/Normal Transfer Mode

(CPU Cycles/Single Address Mode) .................................................................... 374

Figure 8.30 Auto Request/Cycle Steal Mode/Normal Transfer Mode

(Contention with Another Channel/Single Address Mode) ................................... 374

Figure 8.31 Auto Request/Burst Mode/Normal Transfer Mode

(CPU Cycles/Dual Address Mode/BGUP = 0) ..................................................... 375

Figure 8.32 Auto Request/Burst Mode/Normal Transfer Mode

(CPU Cycles/Dual Address Mode/BGUP = 1) ..................................................... 375

Figure 8.33 Auto Request/Burst Mode/Normal Transfer Mode

(CPU Cycles/Single Address Mode/BGUP = 1) ................................................... 376

Figure 8.34 Auto Request/Burst Mode/Normal Transfer Mode

(Contention with Another Channel/Single Address Mode) ................................... 376

Figure 8.35 External Request/Cycle Steal Mode/Normal Transfer Mode

(No Contention/Dual Address Mode/Low Level Sensing) .................................... 377

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Figure 8.36 External Request/Cycle Steal Mode/Normal Transfer Mode

(CPU Cycles/Single Address Mode/Low Level Sensing) ......................................378

Figure 8.37 External Request/Cycle Steal Mode/Normal Transfer Mode

(No Contention/Single Address Mode/Falling Edge Sensing) ...............................378

Figure 8.38 External Request/Cycle Steal Mode/Normal Transfer Mode Contention

with Another Channel/Dual Address Mode/Low Level Sensing............................379

Figure 8.39 External Request/Cycle Steal Mode/Block Transfer Mode

(No Contention/Dual Address Mode/Low Level Sensing/BGUP = 0) ...................380

Figure 8.40 External Request/Cycle Steal Mode/Block Transfer Mode

(No Contention/Single Address Mode/Falling Edge Sensing/BGUP = 0) ..............381

Figure 8.41 External Request/Cycle Steal Mode/Block Transfer Mode

(CPU Cycles/Single Address Mode/Low Level Sensing/BGUP = 0).....................382

Figure 8.42 External Request/Cycle Steal Mode/Block Transfer Mode

(CPU Cycles/Dual Address Mode/Low Level Sensing/BGUP = 1) .......................383

Figure 8.43 External Request/Cycle Steal Mode/Block Transfer Mode

(CPU Cycles/Single Address Mode/Low Level Sensing/BGUP = 1).....................384

Figure 8.44 External Request/Cycle Steal Mode/Block Transfer Mode

(Contention with Another Channel/Dual Address Mode/Low Level Sensing) .......385

Figure 8.45 Transfer End Interrupt Logic ...............................................................................388
Figure 8.46 Example of Procedure for Restarting Transfer on Channel in

which Transfer End Interrupt Occurred ................................................................389

Section 9 Data Transfer Controller (DTC)
Figure 9.1 Block Diagram of DTC .........................................................................................394
Figure 9.2 Block Diagram of DTC Activation Source Control ................................................399
Figure 9.3 Correspondence between DTC Vector Address and Register Information...............400
Figure 9.4 Flowchart of DTC Operation.................................................................................403
Figure 9.5 Memory Mapping in Normal Mode .......................................................................405
Figure 9.6 Memory Mapping in Repeat Mode ........................................................................406
Figure 9.7 Memory Mapping in Block Transfer Mode............................................................407
Figure 9.8 Operation of Chain Transfer..................................................................................408
Figure 9.9 DTC Operation Timing (Example in Normal Mode or Repeat Mode).....................409
Figure 9.10 DTC Operation Timing

(Example of Block Transfer Mode, with Block Size of 2)....................................409

Figure 9.11 DTC Operation Timing (Example of Chain Transfer) ..........................................409
Figure 9.12 Chain Transfer when Counter = 0 ........................................................................414
Section 11 16-Bit Timer Pulse Unit (TPU)
Figure 11.1 Block Diagram of TPU........................................................................................504
Figure 11.2 Example of Counter Operation Setting Procedure ................................................539
Figure 11.3 Free-Running Counter Operation.........................................................................540
Figure 11.4 Periodic Counter Operation .................................................................................541
Figure 11.5 Example of Setting Procedure for Waveform Output by Compare Match .............541
Figure 11.6 Example of 0 Output/1 Output Operation.............................................................542
Figure 11.7 Example of Toggle Output Operation ..................................................................542

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Figure 11.8 Example of Setting Procedure for Input Capture Operation .................................. 543
Figure 11.9 Example of Input Capture Operation ................................................................... 544
Figure 11.10 Example of Synchronous Operation Setting Procedure....................................... 545
Figure 11.11 Example of Synchronous Operation................................................................... 546
Figure 11.12 Compare Match Buffer Operation ..................................................................... 547
Figure 11.13 Input Capture Buffer Operation ......................................................................... 547
Figure 11.14 Example of Buffer Operation Setting Procedure ................................................ 547
Figure 11.15 Example of Buffer Operation (1) ....................................................................... 548
Figure 11.16 Example of Buffer Operation (2) ....................................................................... 549
Figure 11.17 Cascaded Operation Setting Procedure .............................................................. 550
Figure 11.18 Example of Cascaded Operation (1) .................................................................. 550
Figure 11.19 Example of Cascaded Operation (2) .................................................................. 551
Figure 11.20 Example of PWM Mode Setting Procedure........................................................ 553
Figure 11.21 Example of PWM Mode Operation (1) .............................................................. 554
Figure 11.22 Example of PWM Mode Operation (2) .............................................................. 554
Figure 11.23 Example of PWM Mode Operation (3) .............................................................. 555
Figure 11.24 Example of Phase Counting Mode Setting Procedure......................................... 556
Figure 11.25 Example of Phase Counting Mode 1 Operation.................................................. 557
Figure 11.26 Example of Phase Counting Mode 2 Operation.................................................. 558
Figure 11.27 Example of Phase Counting Mode 3 Operation.................................................. 559
Figure 11.28 Example of Phase Counting Mode 4 Operation.................................................. 560
Figure 11.29 Phase Counting Mode Application Example ...................................................... 561
Figure 11.30 Count Timing in Internal Clock Operation......................................................... 565
Figure 11.31 Count Timing in External Clock Operation........................................................ 565
Figure 11.32 Output Compare Output Timing ........................................................................ 566
Figure 11.33 Input Capture Input Signal Timing .................................................................... 566
Figure 11.34 Counter Clear Timing (Compare Match) ........................................................... 567
Figure 11.35 Counter Clear Timing (Input Capture) ............................................................... 567
Figure 11.36 Buffer Operation Timing (Compare Match)....................................................... 567
Figure 11.37 Buffer Operation Timing (Input Capture) .......................................................... 568
Figure 11.38 TGI Interrupt Timing (Compare Match) ............................................................ 568
Figure 11.39 TGI Interrupt Timing (Input Capture) ................................................................ 569
Figure 11.40 TCIV Interrupt Setting Timing .......................................................................... 569
Figure 11.41 TCIU Interrupt Setting Timing .......................................................................... 570
Figure 11.42 Timing for Status Flag Clearing by CPU ........................................................... 570
Figure 11.43 Timing for Status Flag Clearing by DTC/DMAC Activation .............................. 571
Figure 11.44 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode ............... 572
Figure 11.45 Contention between TCNT Write and Clear Operations ..................................... 573
Figure 11.46 Contention between TCNT Write and Increment Operations.............................. 573
Figure 11.47 Contention between TGR Write and Compare Match......................................... 574
Figure 11.48 Contention between Buffer Register Write and Compare Match......................... 575
Figure 11.49 Contention between TGR Read and Input Capture ............................................. 575
Figure 11.50 Contention between TGR Write and Input Capture ............................................ 576

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Figure 11.51 Contention between Buffer Register Write and Input Capture ............................577
Figure 11.52 Contention between Overflow and Counter Clearing..........................................577
Figure 11.53 Contention between TCNT Write and Overflow ................................................578
Section 12 Programmable Pulse Generator (PPG)
Figure 12.1 Block Diagram of PPG........................................................................................580
Figure 12.2 Overview Diagram of PPG..................................................................................589
Figure 12.3 Timing of Transfer and Output of NDR Contents (Example)................................590
Figure 12.4 Setup Procedure for Normal Pulse Output (Example)...........................................591
Figure 12.5 Normal Pulse Output Example (Five-Phase Pulse Output) ...................................592
Figure 12.6 Non-Overlapping Pulse Output............................................................................593
Figure 12.7 Non-Overlapping Operation and NDR Write Timing ...........................................594
Figure 12.8 Setup Procedure for Non-Overlapping Pulse Output (Example) ...........................594
Figure 12.9 Non-Overlapping Pulse Output Example (Four-Phase Complementary) ...............595
Figure 12.10 Inverted Pulse Output (Example) .......................................................................596
Figure 12.11 Pulse Output Triggered by Input Capture (Example) ..........................................597
Section 13 8-Bit Timers (TMR)
Figure 13.1 Block Diagram of 8-Bit Timer Module ................................................................600
Figure 13.2 Example of Pulse Output.....................................................................................608
Figure 13.3 Count Timing for Internal Clock Input.................................................................608
Figure 13.4 Count Timing for External Clock Input................................................................609
Figure 13.5 Timing of CMF Setting .......................................................................................609
Figure 13.6 Timing of Timer Output ......................................................................................610
Figure 13.7 Timing of Compare Match Clear .........................................................................610
Figure 13.8 Timing of Clearance by External Reset................................................................611
Figure 13.9 Timing of OVF Setting........................................................................................611
Figure 13.10 Contention between TCNT Write and Clear.......................................................614
Figure 13.11 Contention between TCNT Write and Increment................................................615
Figure 13.12 Contention between TCOR Write and Compare Match ......................................616
Section 14 Watchdog Timer
Figure 14.1 Block Diagram of WDT ......................................................................................622
Figure 14.2 Operation in Watchdog Timer Mode ...................................................................627
Figure 14.3 Operation in Interval Timer Mode .......................................................................628
Figure 14.4 Writing to TCNT, TCSR, and RSTCSR..............................................................629
Figure 14.5 Contention between TCNT Write and Increment .................................................630
Figure 14.6 Circuit for System Reset by WDTOVF Signal (Example) ....................................631
Section 15 Serial Communication Interface (SCI, IrDA)
Figure 15.1 Block Diagram of SCI.........................................................................................635
Figure 15.2 Data Format in Asynchronous Communication

(Example with 8-Bit Data, Parity, Two Stop Bits) ................................................661

Figure 15.3 Receive Data Sampling Timing in Asynchronous Mode.......................................663
Figure 15.4 Relation between Output Clock and Transfer Data Phase (Asynchronous Mode) .664
Figure 15.5 Sample SCI Initialization Flowchart ....................................................................665

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Figure 15.6 Example of Operation in Transmission in Asynchronous Mode

(Example with 8-Bit Data, Parity, One Stop Bit) .................................................. 666

Figure 15.7 Sample Serial Transmission Flowchart ................................................................ 667
Figure 15.8 Example of SCI Operation in Reception

(Example with 8-Bit Data, Parity, One Stop Bit) .................................................. 668

Figure 15.9 Sample Serial Reception Data Flowchart (1)........................................................ 670
Figure 15.9 Sample Serial Reception Data Flowchart (2)........................................................ 671
Figure 15.10 Example of Communication Using Multiprocessor Format

(Transmission of Data H'AA to Receiving Station A)......................................... 673

Figure 15.11 Sample Multiprocessor Serial Transmission Flowchart ...................................... 675
Figure 15.12 Example of SCI Operation in Reception

(Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit)............................. 676

Figure 15.13 Sample Multiprocessor Serial Reception Flowchart (1) ...................................... 677
Figure 15.13 Sample Multiprocessor Serial Reception Flowchart (2) ...................................... 678
Figure 15.14 Data Format in Clocked Synchronous Communication (For LSB-First) ............. 679
Figure 15.15 Sample SCI Initialization Flowchart .................................................................. 680
Figure 15.16 Sample SCI Transmission Operation in Clocked Synchronous Mode ................. 682
Figure 15.17 Sample Serial Transmission Flowchart .............................................................. 683
Figure 15.18 Example of SCI Operation in Reception ............................................................ 684
Figure 15.19 Sample Serial Reception Flowchart ................................................................... 685
Figure 15.20 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations ...... 687
Figure 15.21 Schematic Diagram of Smart Card Interface Pin Connections ............................ 688
Figure 15.22 Normal Smart Card Interface Data Format......................................................... 689
Figure 15.23 Direct Convention (SDIR = SINV = O/E = 0).................................................... 689
Figure 15.24 Inverse Convention (SDIR = SINV = O/E = 1) .................................................. 689
Figure 15.25 Receive Data Sampling Timing in Smart Card Mode

(Using Clock of 372 Times the Bit Rate)............................................................ 691

Figure 15.26 Retransfer Operation in SCI Transmit Mode ...................................................... 693
Figure 15.27 TEND Flag Generation Timing in Transmission Operation ................................ 693
Figure 15.28 Example of Transmission Processing Flow........................................................ 694
Figure 15.29 Retransfer Operation in SCI Receive Mode ....................................................... 695
Figure 15.30 Example of Reception Processing Flow............................................................. 696
Figure 15.31 Timing for Fixing Clock Output Level............................................................... 696
Figure 15.32 Clock Halt and Restart Procedure ...................................................................... 697
Figure 15.33 Block Diagram of IrDA..................................................................................... 698
Figure 15.34 IrDA Transmit/Receive Operations ................................................................... 699
Figure 15.35 Example of Synchronous Transmission Using DTC........................................... 704
Figure 15.36 Sample Flowchart for Mode Transition during Transmission ............................. 706
Figure 15.37 Port Pin States during Mode Transition

(Internal Clock, Asynchronous Transmission) .................................................... 707

Figure 15.38 Port Pin States during Mode Transition

(Internal Clock, Synchronous Transmission) ...................................................... 707

Figure 15.39 Sample Flowchart for Mode Transition during Reception .................................. 708

Rev. 2.0, 04/02, page xxxv of xliv

Section 16 A/D Converter
Figure 16.1 Block Diagram of A/D Converter ........................................................................710
Figure 16.2 A/D Conversion Timing ......................................................................................722
Figure 16.3 External Trigger Input Timing.............................................................................724
Figure 16.4 A/D Conversion Accuracy Definitions.................................................................725
Figure 16.5 A/D Conversion Accuracy Definitions.................................................................726
Figure 16.6 Example of Analog Input Circuit .........................................................................727
Figure 16.7 Example of Analog Input Protection Circuit ........................................................729
Figure 16.8 Analog Input Pin Equivalent Circuit ....................................................................729
Section 17 D/A Converter
Figure 17.1 Block Diagram of D/A Converter ........................................................................732
Figure 17.2 Example of D/A Converter Operation..................................................................738
Section 19 Flash Memory (F-ZTAT Version)
Figure 19.1 Block Diagram of Flash Memory........................................................................742
Figure 19.2 Flash Memory State Transitions ..........................................................................743
Figure 19.3 Boot Mode..........................................................................................................744
Figure 19.4 User Program Mode ............................................................................................745
Figure 19.5 384-Kbyte Flash Memory Block Configuration (Modes 3, 4, and 7).....................747
Figure 19.6 256-Kbyte Flash Memory Block Configuration (Modes 4, 7, 10, and 11) .............748
Figure 19.7 Programming/Erasing Flowchart Example in User Program Mode .......................759
Figure 19.8 Flowchart for Flash Memory Emulation in RAM.................................................760
Figure 19.9 Example of RAM Overlap Operation...................................................................761
Figure 19.10 Program/Program-Verify Flowchart ..................................................................763
Figure 19.11 Erase/Erase-Verify Flowchart............................................................................765
Figure 19.12 Power-On/Off Timing (H8S/2678 Series) ..........................................................770
Figure 19.13 Power-On/Off Timing (H8S/2678R Series)........................................................771
Figure 19.14 Mode Transition Timing (Example: Boot Mode

User Mode

User Program Mode) ....................................................................................772

Section 20 Masked ROM
Figure 20.1 Block Diagram of 256-Kbyte Masked ROM (HD6432676)..................................775
Figure 20.2 Block Diagram of 128-Kbyte Masked ROM (HD6432675)..................................775
Figure 20.3 Block Diagram of 64-Kbyte Masked ROM (HD643673)......................................776
Section 21 Clock Pulse Generator
Figure 21.1 Block Diagram of Clock Pulse Generator ............................................................777
Figure 21.2 Connection of Crystal Resonator (Example) ........................................................780
Figure 21.3 Crystal Resonator Equivalent Circuit ...................................................................780
Figure 21.4 External Clock Input (Examples).........................................................................781
Figure 21.5 External Clock Input Timing ...............................................................................782
Figure 21.6 Note on Board Design for Oscillation Circuit.......................................................784
Figure 21.7 Recommended External Circuitry for PLL Circuit ...............................................784
Section 22 Power-Down Modes
Figure 22.1 Mode Transitions ................................................................................................787
Figure 22.2 Software Standby Mode Application Example .....................................................794

Rev. 2.0, 04/02, page xxxvi of xliv

Figure 22.3 Hardware Standby Mode Timing......................................................................... 795
Section 24 Electrical Characteristics
Figure 24.1 Output Load Circuit ............................................................................................ 840
Figure 24.2 System Clock Timing.......................................................................................... 841
Figure 24.3 SDRAM

Timing* ............................................................................................. 842

Figure 24.4 (1) Oscillation Stabilization Timing..................................................................... 842
Figure 24.4 (2) Oscillation Stabilization Timing..................................................................... 843
Figure 24.5 Reset Input Timing ............................................................................................. 844
Figure 24.6 Interrupt Input Timing ........................................................................................ 845
Figure 24.7 Basic Bus Timing: Two-State Access .................................................................. 849
Figure 24.8 Basic Bus Timing: Three-State Access ................................................................ 850
Figure 24.9 Basic Bus Timing: Three-State Access, One Wait................................................ 851
Figure 24.10 Basic Bus Timing: Two-State Access (CS Assertion Period Extended) .............. 852
Figure 24.11 Basic Bus Timing: Three-State Access (CS Assertion Period Extended)............. 853
Figure 24.12 Burst ROM Access Timing: One-State Burst Access ......................................... 854
Figure 24.13 Burst ROM Access Timing: Two-State Burst Access......................................... 855
Figure 24.14 DRAM Access Timing: Two-State Access ........................................................ 856
Figure 24.15 DRAM Access Timing: Two-State Access, One Wait........................................ 857
Figure 24.16 DRAM Access Timing: Two-State Burst Access ............................................... 858
Figure 24.17 DRAM Access Timing: Three-State Access (RAST = 1) ................................... 859
Figure 24.18 DRAM Access Timing: Three-State Access, One Wait ...................................... 860
Figure 24.19 DRAM Access Timing: Three-State Burst Access ............................................. 861
Figure 24.20 CAS-Before-RAS Refresh Timing..................................................................... 862
Figure 24.21 CAS-Before-RAS Refresh Timing (with Wait Cycle Insertion).......................... 862
Figure 24.22 Self-Refresh Timing (Return from Software Standby Mode: RAST = 0) ............ 862
Figure 24.23 Self-Refresh Timing (Return from Software Standby Mode: RAST = 1) ............ 863
Figure 24.24 External Bus Release Timing ............................................................................ 863
Figure 24.25 External Bus Request Output Timing................................................................. 864
Figure 24.26 Synchronous DRAM Basic Access Timing (CAS Latency 2)............................. 865
Figure 24.27 Synchronous DRAM Self-Refresh Timing......................................................... 866
Figure 24.28 Read Data: Two-State Expansion (CAS Latency 2) ........................................... 867
Figure 24.29 DMAC and EXDMAC Single Address Transfer Timing: Two-State Access...... 869
Figure 24.30 DMAC and EXDMAC Single Address Transfer Timing: Three-State Access.... 870
Figure 24.31 DMAC and EXDMAC TEND/ETEND Output Timing...................................... 871
Figure 24.32 DMAC and EXDMAC DREQ/EDREQ Input Timing........................................ 871
Figure 24.33 EXDMAC EDRAK Output Timing ................................................................... 871
Figure 24.34 I/O Port Input/Output Timing ............................................................................ 873
Figure 24.35 PPG Output Timing .......................................................................................... 873
Figure 24.36 TPU Input/Output Timing ................................................................................. 873
Figure 24.37 TPU Clock Input Timing................................................................................... 874
Figure 24.38 8-Bit Timer Output Timing ............................................................................... 874
Figure 24.39 8-Bit Timer Clock Input Timing ........................................................................ 874
Figure 24.40 8-Bit Timer Reset Input Timing......................................................................... 874

Rev. 2.0, 04/02, page xxxix of xliv

Tables

Section 1 Overview
Table 1.1

Pin Arrangement in Each Operating Mode..............................................................7

Table 1.2

Pin Functions .......................................................................................................13

Section 2 CPU
Table 2.1

Instruction Classification ......................................................................................37

Table 2.2

Operation Notation...............................................................................................38

Table 2.3

Data Transfer Instructions ....................................................................................39

Table 2.4

Arithmetic Operations Instructions (1) ..................................................................40

Table 2.4

Arithmetic Operations Instructions (2) ..................................................................41

Table 2.5

Logic Operations Instructions...............................................................................42

Table 2.6

Shift Instructions..................................................................................................42

Table 2.7

Bit Manipulation Instructions (1) ..........................................................................43

Table 2.7

Bit Manipulation Instructions (2) ..........................................................................44

Table 2.8

Branch Instructions ..............................................................................................45

Table 2.9

System Control Instructions..................................................................................46

Table 2.10

Block Data Transfer Instructions ..........................................................................47

Table 2.11

Addressing Modes................................................................................................49

Table 2.12

Absolute Address Access Ranges .........................................................................50

Section 3 MCU Operating Modes
Table 3.1

MCU Operating Mode Selection...........................................................................58

Table 3.2

Pin Functions in Each Operating Mode .................................................................64

Section 4 Exception Handling
Table 4.1

Exception Types and Priority................................................................................75

Table 4.2

Exception Handling Vector Table .........................................................................76

Table 4.3

Status of CCR and EXR after Trace Exception Handling ......................................80

Table 4.4

Status of CCR and EXR after Trap Instruction Exception Handling.......................81

Section 5 Interrupt Controller
Table 5.1

Pin Configuration.................................................................................................87

Table 5.2

Interrupt Sources, Vector Addresses, and Interrupt Priorities...............................103

Table 5.3

Interrupt Control Modes .....................................................................................107

Table 5.4

Interrupt Response Times ...................................................................................112

Table 5.5

Number of States in Interrupt Handling Routine Execution Statuses....................113

Section 6 Bus Controller (BSC)
Table 6.1

Pin Configuration...............................................................................................121

Table 6.2

Bus Specifications for Each Area (Basic Bus Interface) ......................................153

Table 6.3

Data Buses Used and Valid Strobes ....................................................................158

Table 6.4

Relation between Settings of Bits RMTS2 to RMTS0 and DRAM Space ............171

Table 6.5

Relation between Settings of Bits MXC2 to MXC0 and Address Multiplexing ....172

Table 6.6

DRAM Interface Pins.........................................................................................173

Rev. 2.0, 04/02, page xl of xliv

Table 6.7

Relation between Settings of Bits RMTS2 to RMTS0 and
Synchronous DRAM Space................................................................................ 195

Table 6.8

Relation between Settings of Bits MXC2 to MXC0 and Address Multiplexing .... 196

Table 6.9

Synchronous DRAM Interface Pins .................................................................... 198

Table 6.10

Setting CAS Latency.......................................................................................... 201

Table 6.11

Idle Cycles in Mixed Accesses to Normal Space and DRAM Continuous
Synchronous DRAM Space ................................................................................ 242

Table 6.12

Pin States in Idle Cycle ...................................................................................... 245

Table 6.13

Pin States in Bus Released State ......................................................................... 248

Section 7 DMA Controller (DMAC)
Table 7.1

Pin Configuration............................................................................................... 257

Table 7.3

DMAC Activation Sources................................................................................. 282

Table 7.4

DMAC Transfer Modes...................................................................................... 284

Table 7.5

Table 7.6

Table 7.7

Table 7.8

Table 7.9

Table 7.10

Table 7.11

DMAC Channel Priority Order........................................................................... 320

Table 7.12

Interrupt Sources and Priority Order ................................................................... 324

Section 8 EXDMA Controller
Table 8.1

Pin Configuration............................................................................................... 333

Table 8.2

EXDMAC Transfer Modes ................................................................................ 345

Table 8.3

EXDMAC Channel Priority Order...................................................................... 360

Table 8.4

Interrupt Sources and Priority Order ................................................................... 388

Section 9 Data Transfer Controller (DTC)
Table 9.1

Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs ............... 401

Table 9.2

Chain Transfer Conditions.................................................................................. 404

Table 9.3

Table 9.4

Table 9.5

Table 9.6

DTC Execution Status........................................................................................ 410

Table 9.7

Number of States Required for Each Execution Status ........................................ 410

Section 10 I/O Ports
Table 10.1

Port Functions.................................................................................................... 418

Table 10.2

Input Pull-Up MOS States (Port A) .................................................................... 473

Table 10.3

Input Pull-Up MOS States (Port B)..................................................................... 476

Table 10.4

Input Pull-Up MOS States (Port C)..................................................................... 479

Table 10.5

Input Pull-Up MOS States (Port D) .................................................................... 482

Table 10.6

Input Pull-Up MOS States (Port E)..................................................................... 485

Section 11 16-Bit Timer Pulse Unit (TPU)
Table 11.1

TPU Functions................................................................................................... 502

Rev. 2.0, 04/02, page xli of xliv

Table 11.2

Pin Configuration...............................................................................................505

Table 11.3

CCLR2 to CCLR0 (Channels 0 and 3) ................................................................509

Table 11.4

CCLR2 to CCLR0 (Channels 1, 2, 4, and 5) .......................................................509

Table 11.5

TPSC2 to TPSC0 (Channel 0) ............................................................................510

Table 11.6

TPSC2 to TPSC0 (Channel 1) ............................................................................510

Table 11.7

TPSC2 to TPSC0 (Channel 2) ............................................................................511

Table 11.8

TPSC2 to TPSC0 (Channel 3) ............................................................................511

Table 11.9

TPSC2 to TPSC0 (Channel 4) ............................................................................512

Table 11.10 TPSC2 to TPSC0 (Channel 5) ............................................................................512
Table 11.11 MD3 to MD0 .....................................................................................................514
Table 11.12 TIORH_0...........................................................................................................516
Table 11.13 TIORL_0 ...........................................................................................................517
Table 11.14 TIOR_1 .............................................................................................................518
Table 11.15 TIOR_2 .............................................................................................................519
Table 11.16 TIORH_3...........................................................................................................520
Table 11.17 TIORL_3 ...........................................................................................................521
Table 11.18 TIOR_4 .............................................................................................................522
Table 11.19 TIOR_5 .............................................................................................................523
Table 11.20 TIORH_0...........................................................................................................524
Table 11.21 TIORL_0 ...........................................................................................................525
Table 11.22 TIOR_1 .............................................................................................................526
Table 11.23 TIOR_2 .............................................................................................................527
Table 11.24 TIORH_3...........................................................................................................528
Table 11.25 TIORL_3 ...........................................................................................................529
Table 11.26 TIOR_4 .............................................................................................................530
Table 11.27 TIOR_5 .............................................................................................................531
Table 11.28 Register Combinations in Buffer Operation ........................................................546
Table 11.29 Cascaded Combinations .....................................................................................549
Table 11.30 PWM Output Registers and Output Pins .............................................................552
Table 11.31 Clock Input Pins in Phase Counting Mode ..........................................................556
Table 11.32 Up/Down-Count Conditions in Phase Counting Mode 1......................................557
Table 11.33 Up/Down-Count Conditions in Phase Counting Mode 2......................................558
Table 11.34 Up/Down-Count Conditions in Phase Counting Mode 3.....................................559
Table 11.35 Up/Down-Count Conditions in Phase Counting Mode 4......................................560
Table 11.36 TPU Interrupts ...................................................................................................563
Section 12 Programmable Pulse Generator (PPG)
Table 12.1

Pin Configuration...............................................................................................581

Section 13 8-Bit Timers (TMR)
Table 13.1

Pin Configuration...............................................................................................601

Table 13.2

Clock Input to TCNT and Count Condition.........................................................604

Table 13.3

8-Bit Timer Interrupt Sources .............................................................................613

Table 13.4

Timer Output Priorities.......................................................................................616

Table 13.5

Switching of Internal Clock and TCNT Operation...............................................618

Rev. 2.0, 04/02, page xlii of xliv

Section 14 Watchdog Timer
Table 14.1

Pin configuration................................................................................................ 622

Table 14.2

WDT Interrupt Source........................................................................................ 628

Section 15 Serial Communication Interface (SCI, IrDA)
Table 15.1

Pin Configuration............................................................................................... 636

Table 15.2

Relationships between N Setting in BRR and Bit Rate B..................................... 649

Table 15.3

BRR Settings for Various Bit Rates (Asynchronous Mode) (1) ........................... 650

Table 15.3

BRR Settings for Various Bit Rates (Asynchronous Mode) (2) ........................... 651

Table 15.3

BRR Settings for Various Bit Rates (Asynchronous Mode) (3) ........................... 652

Table 15.3

BRR Settings for Various Bit Rates (Asynchronous Mode) (4) ........................... 653

Table 15.4

Maximum Bit Rate for Each Frequency (Asynchronous Mode)........................... 654

Table 15.5

Maximum Bit Rate with External Clock Input (Asynchronous Mode) ................. 654

Table 15.6

BRR Settings for Various Bit Rates (Clocked Synchronous Mode) ..................... 655

Table 15.7

Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode)...... 656

Table 15.8

Examples of Bit Rate for Various BRR Settings

(Smart Card Interface Mode) (when n = 0 and S = 372)..................................... 657

Table 15.9

Maximum Bit Rate at Various Frequencies (Smart Card Interface Mode)

(when S = 372) ................................................................................................. 657

Table 15.10 Serial Transfer Formats (Asynchronous Mode)................................................... 662
Table 15.11 SSR Status Flags and Receive Data Handling ..................................................... 669
Table 15.12 Settings of Bits IrCKS2 to IrCKS0 ..................................................................... 700
Table 15.13 SCI Interrupt Sources......................................................................................... 701
Table 15.14 SCI Interrupt Sources......................................................................................... 702
Section 16 A/D Converter
Table 16.1

A/D Converter Pins............................................................................................ 711

Table 16.2

Analog Input Channels and Corresponding ADDR Registers .............................. 712

Table 16.3

A/D Conversion Time (Single Mode) ................................................................. 722

Table 16.4

A/D Conversion Time (Scan Mode) ................................................................... 723

Table 16.5

A/D Converter Interrupt Source.......................................................................... 724

Table 16.6

Analog Pin Specifications .................................................................................. 729

Section 17 D/A Converter
Table 17.1

Pin Configuration............................................................................................... 733

Table 17.2

Control of D/A Conversion ................................................................................ 735

Table 17.3

Control of D/A Conversion ................................................................................ 737

Section 19 Flash Memory (F-ZTAT Version)
Table 19.1

Differences between Boot Mode and User Program Mode .................................. 743

Table 19.2

Pin Configuration............................................................................................... 749

Table 19.3

Erase Blocks ...................................................................................................... 754

Table 19.4

Setting On-Board Programming Modes .............................................................. 756

Table 19.5

Boot Mode Operation......................................................................................... 758

Table 19.6

System Clock Frequencies for which Automatic Adjustment of

LSI Bit Rate is Possible .................................................................................... 758

Table 19.7

Flash Memory Operating States.......................................................................... 767

Rev. 2.0, 04/02, page xliii of xliv

Section 21 Clock Pulse Generator
Table 21.1

Damping Resistance Value.................................................................................780

Table 21.2

Crystal Resonator Characteristics .......................................................................780

Table 21.3

External Clock Input Conditions.........................................................................782

Section 22 Power-Down Modes
Table 22.1

Operating Modes................................................................................................786

Table 22.2

Oscillation Stabilization Time Settings ...............................................................793

Table 22.3

ø Pin State in Each Processing State ...................................................................796

Section 24 Electrical Characteristics
Table 24.1

Absolute Maximum Ratings ...............................................................................835

Table 24.2

DC Characteristics .............................................................................................836

Table 24.3

DC Characteristics .............................................................................................838

Table 24.4

Permissible Output Currents ...............................................................................839

Table 24.5

Clock Timing .....................................................................................................841

Table 24.6

Control Signal Timing........................................................................................844

Table 24.7

Bus Timing ........................................................................................................846

Table 24.8

Bus Timing ........................................................................................................847

Table 24.9

DMAC and EXDMAC Timing...........................................................................868

Table 24.10 Timing of On-Chip Peripheral Modules..............................................................872
Table 24.11 A/D Conversion Characteristics..........................................................................876
Table 24.12 D/A Conversion Characteristics..........................................................................876
Table 24.13 Flash Memory Characteristics ............................................................................877

Rev. 2.0, 04/02, page 1 of 906

Section 1 Overview

1.1

Features

High-speed H8S/2600 central processing unit with an internal 16-bit architecture

Upward-compatible with H8/300 and H8/300H CPUs on an object level

Sixteen 16-bit general registers

69 basic instructions

Various peripheral functions

DMA controller (DMAC)

EXDMA controller (EXDMAC)

Data transfer controller (DTC)

16-bit timer-pulse unit (TPU)

Programmable pulse generator (PPG)

8-bit timer (TMR)

Watchdog timer (WDT)

Asynchronous or clocked synchronous serial communication interface (SCI)

10-bit A/D converter

8-bit D/A converter

Clock pulse generator

On-chip memory

ROM Type

Model

ROM

RAM

Remarks

Flash memory
Version

HD64F2676

256 kbytes

8 kbytes

Masked ROM

HD6432676

256 kbytes

8 kbytes

version

HD6432675

128 kbytes

8 kbytes

HD6432673

64 kbytes

8 kbytes

ROMless version

HD6412674R

32 kbytes

HD6412670

8 kbytes

General I/O ports

I/O pins: 103

Input-only pins: 12

Supports various power-down states

Compact package

Rev. 2.0, 04/02, page 3 of 906

1.2

Block Diagram

PE7/D7

PE6/D6

PE5/D5

PE4/D4

PE3/D3

PE2/D2

PE1/D1

PE0/D0

Internal data bus

Peripheral address bus

Peripheral data bus

PD7/D15

PD6/D14

PD5/D13

PD4/D12

PD3/D11

PD2/D10

PD1/D9

PD0/D8

Port D

PLLVcc

PLLVss

Vcc

Vss

PA7 / A23
PA6 / A22
PA5 / A21
PA4 / A20
PA3 / A19
PA2 / A18
PA1 / A17
PA0 / A16

PB7 / A15
PB6 / A14
PB5 / A13
PB4 / A12
PB3 / A11
PB2 / A10
PB1 / A9
PB0 / A8

PC7 / A7
PC6 / A6
PC5 / A5
PC4 / A4
PC3 / A3
PC2 / A2
PC1 / A1
PC0 / A0

P35 / SCK1/(

)

P34 / SCK0
P33 / RxD1
P32 / RxD0/IrRxD
P31 / TxD1
P30 / TxD0/IrTxD

P57 / AN15/DA3/
P56 / AN14/DA2/
P55 / AN13/
P54 / AN12/
P53 /

P52 / SCK2/
P51 / RxD2/
P50 / TxD2/

P47

/
AN7

/
DA1

P46

/
AN6

/
DA0

P45

/
AN5

P44

/
AN4

P43

/
AN3

P42

/
AN2

P41

/
AN1

P40

/
AN0

Vref

AVcc

AVss

P20

/PO0

/
TIOCA3/(

)

P21

/PO1

/
TIOCB3/(

)

P22

/PO2

/
TIOCC3

/
(

)

P23

/PO3

/
TIOCD3

/
(

)

P24

/PO4

/
TIOCA4

/
(

)

P25

/PO5

/
TIOCB4

/
(

)

P26

/PO6

/
TIOCA5

)

P27

/PO7

/
TIOCB5

)

P10/

PO8

/
TIOCA0

P11

/
PO9

/
TIOCB0

P12

/
PO10

/
TIOCC0

/
TCLKA

P13

/
PO11

/
TIOCD0

/
TCLKB

P14

/
PO12

/
TIOCA1

P15

/
PO13

/
TIOCB1

/
TCLKC

P16

/
PO14

/
TIOCA2/

P17

/
PO15

/
TIOCB2

/
TCLKD/

P65 /TMO1/

P64 /TMO0/

P63 /TMCI1/

P62 /TMCI0/

P61 /TMRI1/

P60 /TMRI0/

PG6 /

PG5 /

PG4 /

PG3 /
PG2 /
PG1 /
PG0 /

PF7 /ø

PF6 /

PF5 /

PF4 /

PF3 /

PF2/

PF1 /

PF0 /

ROM

(Flash memory

or mask ROM)

RAM

WDT

TPU × 6 channels

TMR × 2 channels

SCI × 3 channels

8-bit D/A converter

10-bit A/D converter

PPG

MD2
MD1
MD0

EXTAL

XTAL

FWE

NMI

H8S/2600 CPU

DTC

Interrupt controller

Port E

Port 4

P75

)

P74

)

P73

)

P72

)

P71

)

P70

)

Port 7

PH3/

)

PH2/

)

PH1/

PH0/

Port H

Port 2

Port 1

DMAC

EXDMAC

Internal address bus

P85 /

)

P84 /

)

P83 /

)

P82 /

)

P81 /

)

P80 /

)

Port 8

Bus controller

Notes:

Port 6

Port G

Port F

Port A

Port B

Port C

Port 3

Port 5

ROM is not supported in the ROMless version.
The FWE pin is used only in the F-ZTAT version. In other versions, this is an NC pin.

PLL

Clock

pulse

generator

Figure 1.1 H8S/2678 Series Internal Block Diagram

Rev. 2.0, 04/02, page 4 of 906

PE7/D7

PE6/D6

PE5/D5

PE4/D4

PE3/D3

PE2/D2

PE1/D1

PE0/D0

PD7/D15

PD6/D14

PD5/D13

PD4/D12

PD3/D11

PD2/D10

PD1/D9

PD0/D8

Vcc

PLLVcc

PLLV

PA7 / A23
PA6 / A22
PA5 / A21
PA4 / A20
PA3 / A19
PA2 / A18
PA1 / A17
PA0 / A16

PB7 / A15
PB6 / A14
PB5 / A13
PB4 / A12
PB3 / A11
PB2 / A10
PB1 / A9
PB0 / A8

PC7 / A7
PC6 / A6
PC5 / A5
PC4 / A4
PC3 / A3
PC2 / A2
PC1 / A1
PC0 / A0

P35 / SCK1/(

)/(CKE)

P34 / SCK0
P33 / RxD1
P32 / RxD0/IrRxD
P31 / TxD1
P30 / TxD0/IrTxD

P57 / AN15/DA3/
P56 / AN14/DA2/
P55 / AN13/
P54 / AN12/
P53 /

P52 / SCK2/
P51 / RxD2/
P50 / TxD2/

P47

/
AN7

/
DA1

P46

/
AN6

/
DA0

P45

/
AN5

P44

/
AN4

P43

/
AN3

P42

/
AN2

P41

/
AN1

P40

/
AN0

Vref

AVcc

AVss

P20

/
PO0

/
TIOCA3/(

)

P21

/
PO1

/
TIOCB3/(

)

P22

/
PO2

/
TIOCC3

/
(

)

P23

/
PO3

/
TIOCD3

/
(

)

P24

/
PO4

/
TIOCA4

/
(

)

P25

/
PO5

/
TIOCB4

/
(

)

P26

/
PO6

/
TIOCA5

)

P27

/
PO7

/
TIOCB5

)

P10/

PO8

/
TIOCA0

P11

/
PO9

/
TIOCB0

P12

/
PO10

/
TIOCC0

/
TCLKA

P13

/
PO11

/TIOCD0

/
TCLKB

P14

/
PO12

/
TIOCA1

P15

/
PO13

/
TIOCB1

/
TCLKC

P16

/
PO14

/
TIOCA2/

P17

/
PO15

/
TIOCB2

/
TCLKD/

P65 /TMO1/

P64 /TMO0/

P63 /TMCI1/

P62 /TMCI0/

P61 / TMRI1/

P60 / TMRI0/

PG6 /

PG5 /

PG4 /

PG3 /

PG2 /

PG1 /
PG0 /

PF7 /

PF6 /

PF5 /

PF4 /

PF3 /

PF2/

/DQML

PF1 /

/DQMU

PF0 /

ROM

(Flash memory)

RAM

WDT

EXDMAC

TPU × 6 channels

Note:

ROM is not supported in the ROMless version.

SCI

× 3 channels

PPG

Port 1

Port 2

Port 4

MD2
MD1
MD0

DCTL

EXTAL

XTAL

NMI

H8S/2600 CPU

Interrupt controller

Port D

Port E

Port A

Port B

Peripheral data bus

Peripheral address bus

Bus controller

Port C

Port 3

Port 5

DTC

P75

)

P74

)

P73

)

P72

)

P71

)

P70

)

PH3/

)/CKE

PH2/

)

PH1/

/SDRAM

PH0/

DMAC

P85 /

)

P84 /

)

P83 /

)

P82 /

)

P81 /

)

P80 /

)

PLL

Clock

pulse

generator

Port 8

Port 6

Port G

Port F

TMR × 2 channels

8-bit D/A converter

10-bit A/D converter

Internal data bus

Internal address bus

Port H

Port 7

Figure 1.2 H8S/2678R Series Internal Block Diagram

Rev. 2.0, 04/02, page 5 of 906

1.3

Pin Description

1.3.1

Pin Arrangement

MD2

P83

)

P84

)

P85

)

Vcc

PC0/A0

PC1/A1

PC2/A2

PC3/A3

PC4/A4

PC5/A5

Vss

PC6/A6

PC7/A7

PB0/A8

PB1/A9

PB2/A10

PB3/A11

Vss

PB4/A12

PB5/A13

PB6/A14

PB7/A15

PA0/A16

PA1/A17

Vss

PA2/A18

PA3/A19

PA4/A20

PA5/A21

PA6/A22

PA7/A23

P70

)

P71

)

P72

)

P51/RxD2/

P50/TxD2/

PH1/

PH0/

PG3/

PG2/

PG1/

PG0/

Vss

XTAL

EXTAL

Vcc

PF7/

PLLVcc

PLLVss

PF6/

PF5/

PF4/

PF3/

PF2/

PF1/

PF0/

P65/TMO1/

P64/TMO0/

P63/TMCI1/

P62/TMCI0/

0/D

1/D

PD2

/
D10

PD3

/
D11

Vss

PD4

/
D12

PD5

/
D13

PD6

/
D14

108

107

106

105

104

103

102

101

100

P52/SCK2/

P53/

PH2/

)

PH3/

)

PG4 /

PG5 /

PG6 /

V c c

P40 / AN0
P41 / AN1
P42 / AN2
P43 / AN3

Vref

AVcc

P44 / AN4
P45 / AN5

P46 / AN6 / DA0
P47 / AN7 / DA1

P54 / AN12/
P55 / AN13/

P56 / AN14/DA2/
P57 / AN15/DA3/

AVss

P35 / SCK1/(

)

P34 / SCK0

P33 / RxD1

Vss

P32 / RxD0/IrRxD

P31 / TxD1

P30 / TxD0/IrTxD

P80 /

/ (

)

P81 /

/ (

)

P82/

)

MD0
MD1

109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144

PD7 / D15
PE0 / D0
PE1 / D1
PE2 / D2
PE3 / D3
Vcc
PE4 / D4
PE5 / D5
PE6 / D6
PE7 / D7
FWE

P61/TMRI1/

P60/TMRI0/

P27/ PO7 / TIOCB5 /

)

P26/ PO6 / TIOCA5 /

)

P25/ PO5 /TIOCB4 /(

)

P24/ PO4 /TIOCA4 /(

)

P23/ PO3 /TIOCD3 /(

)

P22/ PO2 /TIOCC3 /(

)

P21/PO1 /TIOCB3/(

)

P20/PO0 /TIOCA3/(

)

P17/ PO15 /TIOCB2 /TCLKD/
P16/PO14 /TIOCA2/
P15/ PO13 /TIOCB1 /TCLKC
P14/PO12 /TIOCA1
Vss
P13/ PO11 /TIOCD0 /TCLKB
P12/ PO10 /TIOCC0 /TCLKA
P11/ PO9 /TIOCB0
P10/ PO8 /TIOCA0
P75/

)

P74/

)

P73/

)

Vcc
NMI

72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37

FP-144G

(Top view)

Notes: 1. The FWE pin is used only in the F-ZTAT version. In other versions, this is an NC pin.

2. An NC pin should be unconnected.

Figure 1.3 H8S/2678 Series Pin Arrangement

Rev. 2.0, 04/02, page 6 of 906

MD2

P83

)

P84

)

P85

)

Vcc

PC0/A0

PC1/A1

PC2/A2

PC3/A3

PC4/A4

PC5/A5

Vss

PC6/A6

PC7/A7

PB0/A8

PB1/A9

PB2/A10

PB3/A11

Vss

PB4/A12

PB5/A13

PB6/A14

PB7/A15

PA0/A16

PA1/A17

Vss

PA2/A18

PA3/A19

PA4/A20

PA5/A21

PA6/A22

PA7/A23

P70

)

P71

)

P72

)

P51/RxD2/

P50/TxD2/

PH1/

/SDRAM

PH0/

PG3/

PG2/

PG1/

PG0/

Vss

XTAL

EXTAL

Vcc

PF7/

PLLVcc

PLLVss

PF6/

PF5/

PF4/

PF3/

PF2/

/DQML

PF1/

/DQMU

PF0/

P65/TMO1/

P64/TMO0/

P63/TMCI1/

P62/TMCI0/

0/D

1/D

PD2

/
D10

PD3

/
D11

Vss

PD4

/
D12

PD5

/
D13

PD6

/
D14

108

107

106

105

104

103

102

101

100

P52/SCK2/

P53/

PH2/

)

PH3/

)

PG4 /

PG5 /

PG6 /

V c c

P40 / AN0
P41 / AN1
P42 / AN2
P43 / AN3

Vref

AVcc

P44 / AN4
P45 / AN5

P46 / AN6 / DA0
P47 / AN7 / DA1

P54 / AN12/
P55 / AN13/

P56 / AN14/DA2/
P57 / AN15/DA3/

AVss

DCTL

P35 / SCK1/(

)/(CKE)

P34 / SCK0

P33 / RxD1

Vss

P32 / RxD0/IrRxD

P31 / TxD1

P30 / TxD0/IrTxD

P80 /

/ (

)

P81 /

/ (

)

P82/

)

MD0
MD1

109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144

PD7 / D15
PE0 / D0
PE1 / D1
PE2 / D2
PE3 / D3
Vcc
PE4 / D4
PE5 / D5
PE6 / D6
PE7 / D7
Vss
P61/TMRI1/

P60/TMRI0/

P27/ PO7 / TIOCB5 /

)

P26/ PO6 / TIOCA5 /

)

P25/ PO5 /TIOCB4 /(

)

P24/ PO4 /TIOCA4 /(

)

P23/ PO3 /TIOCD3 /(

)

P22/ PO2 /TIOCC3 /(

)

P21/PO1 /TIOCB3/(

)

P20/PO0 /TIOCA3/(

)

P17/ PO15 /TIOCB2 /TCLKD/
P16/PO14 /TIOCA2/
P15/ PO13 /TIOCB1 /TCLKC
P14/PO12 /TIOCA1
Vss
P13/ PO11 /TIOCD0 /TCLKB
P12/ PO10 /TIOCC0 /TCLKA
P11/ PO9 /TIOCB0
P10/ PO8 /TIOCA0
P75/

)

P74/

)

P73/

)

Vcc
NMI

72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37

FP-144H

(Top view)

Note:

An NC pin should be unconnected.

Figure 1.4 H8S/2678R Series Pin Arrangement

Rev. 2.0, 04/02, page 7 of 906

1.3.2

Pin Arrangement in Each Operating Mode

Table 1.1

Pin Arrangement in Each Operating Mode

Pin Name

Pin

No.

Mode 7

Modes 1 and 5

Modes 2 and 6

Mode 4

EXPE = 1

EXPE = 0

Flash Memory

Programmer

Mode

MD2

Vss

P83/

(7(1'

(

,54

)

P83/

(7(1'

(

,54

)

P83/

(7(1'

(

,54

)

P83/

(7(1'

(

,54

)

P83/(

,54

)

P84/

('$&.

(

,54

)

P84/

('$&.

(

,54

)

P84/

('$&.

(

,54

)

P84/

('$&.

(

,54

)

P84/(

,54

)

P85/

('$&.

(

,54

)

P85/

('$&.

(

,54

)

P85/

('$&.

(

,54

)

P85/

('$&.

(

,54

)

P85/(

,54

)

Vcc

PC0/A0

PC0

PC1/A1

PC1

PC2/A2

PC2

PC3/A3

PC3

PC4/A4

PC4

PC5/A5

PC5

Vss

PC6/A6

PC6

PC7/A7

PC7

PB0/A8

PB0

PB1/A9

PB1

A10

PB2/A10

PB2

A10

A11

PB3/A11

PB3

A11

Vss

A12

PB4/A12

PB4

A12

A13

PB5/A13

PB5

A13

A14

PB6/A14

PB6

A14

A15

PB7/A15

PB7

A15

A16

PA0/A16

PA0

A16

A17

PA1/A17

PA1

A17

Vss

A18

PA2/A18

PA2

A18

Rev. 2.0, 04/02, page 8 of 906

Pin Name

Pin

No.

Mode 7

Modes 1 and 5

Modes 2 and 6

Mode 4

EXPE = 1

EXPE = 0

Flash Memory

Programmer

Mode

A19

PA3/A19

PA3

A20

PA4/A20

PA4

PA5/A21

PA5

PA6/A22

PA6

PA7/A23

PA7

P70/

('5(4

(

'5(4

)

P70/

('5(4

(

'5(4

)

P70/

('5(4

(

'5(4

)

P70/

('5(4

(

'5(4

)

P70/(

'5(4

)

P71/

('5(4

(

'5(4

)

P71/

('5(4

(

'5(4

)

P71/

('5(4

(

'5(4

)

P71/

('5(4

(

'5(4

)

P71/(

'5(4

)

P72/

(7(1'

(

7(1'

)

P72/

(7(1'

(

7(1'

)

P72/

(7(1'

(

7(1'

)

P72/

(7(1'

(

7(1'

)

P72/(

7(1'

)

:'729)

NMI

Vcc

P73/

(7(1'

(

7(1'

)

P73/

(7(1'

(

7(1'

)

P73/

(7(1'

(

7(1'

)

P73/

(7(1'

(

7(1'

)

P73/(

7(1'

)

P74/

('$&.

(

'$&.

)

P74/

('$&.

(

'$&.

)

P74/

('$&.

(

'$&.

)

P74/

('$&.

(

'$&.

)

P74/(

'$&.

)

P75/

('$&.

(

'$&.

)

P75/

('$&.

(

'$&.

)

P75/

('$&.

(

'$&.

)

P75/

('$&.

(

'$&.

)

P75/(

'$&.

)

P10/PO8/TIOCA0

P11/PO9/TIOCB0

P12/PO10/

TIOCC0/TCLKA

P12/PO10/

TIOCC0/TCLKA

P12/PO10/

TIOCC0/TCLKA

P12/PO10/

TIOCC0/TCLKA

P12/PO10/

TIOCC0/TCLKA

P13/PO11/

TIOCD0/TCLKB

P13/PO11/

TIOCD0/TCLKB

P13/PO11/

TIOCD0/TCLKB

P13/PO11/

TIOCD0/TCLKB

P13/PO11/

TIOCD0/TCLKB

Vss

P14/PO12/

TIOCA1

P14/PO12/

TIOCA1

P14/PO12/

TIOCA1

P14/PO12/

TIOCA1

P14/PO12/

TIOCA1

P15/PO13/

TIOCB1/TCLKC

P15/PO13/

TIOCB1/TCLKC

P15/PO13/

TIOCB1/TCLKC

P15/PO13/

TIOCB1/TCLKC

P15/PO13/

TIOCB1/TCLKC

P16/PO14/

TIOCA2/

('5$.

P16/PO14/

TIOCA2/

('5$.

P16/PO14/

TIOCA2/

('5$.

P16/PO14/

TIOCA2/

('5$.

P16/PO14/

TIOCA2

Rev. 2.0, 04/02, page 9 of 906

Pin Name

Pin

No.

Mode 7

Modes 1 and 5

Modes 2 and 6

Mode 4

EXPE = 1

EXPE = 0

Flash Memory

Programmer

Mode

P17/PO15/

TIOCB2/TCLKD/

('5$.

P17/PO15/

TIOCB2/TCLKD/

('5$.

P17/PO15/

TIOCB2/TCLKD/

('5$.

P17/PO15/

TIOCB2/TCLKD/

('5$.

P17/PO15/

TIOCB2/TCLKD

P20/PO0/

TIOCA3/(

,54

)

P20/PO0/

TIOCA3/(

,54

)

P20/PO0/

TIOCA3/(

,54

)

P20/PO0/

TIOCA3/(

,54

)

P20/PO0/

TIOCA3/(

,54

)

P21/PO1/

TIOCB3/(

,54

)

P21/PO1/

TIOCB3/(

,54

)

P21/PO1/

TIOCB3/(

,54

)

P21/PO1/

TIOCB3/(

,54

)

P21/PO1/

TIOCB3/(

,54

)

P22/PO2/

TIOCC3/(

,54

)

P22/PO2/

TIOCC3/(

,54

)

P22/PO2/

TIOCC3/(

,54

)

P22/PO2/

TIOCC3/(

,54

)

P22/PO2/

TIOCC3/(

,54

)

P23/PO3/

TIOCD3/(

,54

)

P23/PO3/

TIOCD3/(

,54

)

P23/PO3/

TIOCD3/(

,54

)

P23/PO3/

TIOCD3/(

,54

)

P23/PO3/

TIOCD3/(

,54

)

P24/PO4/

TIOCA4/(

,54

)

P24/PO4/

TIOCA4/(

,54

)

P24/PO4/

TIOCA4/(

,54

)

P24/PO4/

TIOCA4/(

,54

)

P24/PO4/

TIOCA4/(

,54

)

P25/PO5/

TIOCB4/(

,54

)

P25/PO5/

TIOCB4/(

,54

)

P25/PO5/

TIOCB4/(

,54

)

P25/PO5/

TIOCB4/(

,54

)

P25/PO5/

TIOCB4/(

,54

)

Vss

P26/PO6/

TIOCA5/

('5$.

,54

)

P26/PO6/

TIOCA5/

('5$.

,54

)

P26/PO6/

TIOCA5/

('5$.

,54

)

P26/PO6/

TIOCA5/

('5$.

,54

)

P26/PO6/

TIOCA5/(

,54

)

P27/PO7/

TIOCB5/

('5$.

,54

)

P27/PO7/

TIOCB5/

('5$.

,54

)

P27/PO7/

TIOCB5/

('5$.

,54

)

P27/PO7/

TIOCB5/

('5$.

,54

)

P27/PO7/

TIOCB5/(

,54

)

P60/TMRI0/

'5(4

,54

P60/TMRI0/

'5(4

,54

P60/TMRI0/

'5(4

,54

P60/TMRI0/

'5(4

,54

P60/TMRI0/

'5(4

,54

P61/TMRI1/

'5(4

,54

P61/TMRI1/

'5(4

,54

P61/TMRI1/

'5(4

,54

P61/TMRI1/

'5(4

,54

P61/TMRI1/

'5(4

,54

FWE

Vss

FWE

Vss

FWE

Vss

FWE

Vss

FWE

Vss

FWE

Vss

PE7/D7

PE7

PE6/D6

PE6

PE5/D5

PE5

PE4/D4

PE4

Vcc

PE3/D3

PE3

PE2/D2

PE2

PE1/D1

PE1

PE0/D0

PE0

D15

PD7

I/O7

Rev. 2.0, 04/02, page 10 of 906

Pin Name

Pin

No.

Mode 7

Modes 1 and 5

Modes 2 and 6

Mode 4

EXPE = 1

EXPE = 0

Flash Memory

Programmer

Mode

D14

PD6

I/O6

D13

PD5

I/O5

D12

PD4

I/O4

Vss

D11

PD3

I/O3

D10

PD2

I/O2

PD1

I/O1

PD0

I/O0

P62/TMCI0/

7(1'

,54

P62/TMCI0/

7(1'

,54

P62/TMCI0/

7(1'

,54

P62/TMCI0/

7(1'

,54

P62/TMCI0/

7(1'

,54

P63/TMCI1/

7(1'

,54

P63/TMCI1/

7(1'

,54

P63/TMCI1/

7(1'

,54

P63/TMCI1/

7(1'

,54

P63/TMCI1/

7(1'

,54

P64/TMO0/

'$&.

,54

P64/TMO0/

'$&.

,54

P64/TMO0/

'$&.

,54

P64/TMO0/

'$&.

,54

P64/TMO0/

'$&.

,54

P65/TMO1/

'$&.

,54

P65/TMO1/

'$&.

,54

P65/TMO1/

'$&.

,54

P65/TMO1/

'$&.

,54

P65/TMO1/

'$&.

,54

PF0/

:$,7

PF0/

:$,7

PF0/

:$,7

PF0/

:$,7

PF0

PF1/

8&$6

,54

/DQMU

PF1/

8&$6

,54

/DQMU

PF1/

8&$6

,54

/DQMU

PF1/

8&$6

,54

/DQMU

PF1/

,54

PF2/

/&$6

,54

/DQML

PF2/

/&$6

,54

/DQML

PF2/

/&$6

,54

/DQML

PF2/

/&$6

,54

/DQML

PF2/

,54

PF3/

/:5

PF3/

/:5

PF3/

/:5

PF3/

/:5

PF3

+:5

PF4

PF5

PF6/

PF6

PLLVss

Vss

5(6

PLLVcc

Vcc

PF7/

Vcc

EXTAL

XTAL

Vss

100

67%<

Vcc

Rev. 2.0, 04/02, page 11 of 906

Pin Name

Pin

No.

Mode 7

Modes 1 and 5

Modes 2 and 6

Mode 4

EXPE = 1

EXPE = 0

Flash Memory

Programmer

Mode

101

PG0/

PG0

102

PG1/

PG1

103

PG2/

5$6*

PG2/

5$6*

PG2/

5$6*

PG2/

5$6*

PG2

104

PG3/

5$6*

&$6*

PG3/

5$6*

&$6*

PG3/

5$6*

&$6*

PG3/

5$6*

&$6*

PG3

105

PH0/

5$6*

:(*

PH0/

5$6*

:(*

PH0/

5$6*

:(*

PH0/

5$6*

:(*

PH0

106

PH1/

5$6*

SDRAM

PH1/

5$6*

SDRAM

PH1/

5$6*

SDRAM

PH1/

5$6*

SDRAM

PH1

107

P50/TxD2/

,54

P50/TxD2/

,54

P50/TxD2/

,54

P50/TxD2/

,54

P50/TxD2/

,54

Vss

108

P51/RxD2/

,54

P51/RxD2/

,54

P51/RxD2/

,54

P51/RxD2/

,54

P51/RxD2/

,54

Vss

109

P52/SCK2/

,54

P52/SCK2/

,54

P52/SCK2/

,54

P52/SCK2/

,54

P52/SCK2/

,54

Vcc

110

P53/

$'75*

,54

P53/

$'75*

,54

P53/

$'75*

,54

P53/

$'75*

,54

P53/

$'75*

,54

111

PH2/

,54

)

PH2/

,54

)

PH2/

,54

)

PH2/

,54

)

PH2/(

,54

112

PH3/

(

,54

)/CKE

PH3/

(

,54

)/CKE

PH3/

(

,54

)/CKE

PH3/

(

,54

)/CKE

PH3/(

,54

)

113

PG4/

%5(42

PG4/

%5(42

PG4/

%5(42

PG4/

%5(42

PG4

114

PG5/

%$&.

PG5/

%$&.

PG5/

%$&.

PG5/

%$&.

PG5

115

PG6/

%5(4

PG6/

%5(4

PG6/

%5(4

PG6/

%5(4

PG6

116

Vcc

117

P40/AN0

118

P41/AN1

119

P42/AN2

120

P43/AN3

121

Vref

122

AVcc

Vcc

123

P44/AN4

124

P45/AN5

125

P46/AN6/DA0

126

P47/AN7/DA1

127

P54/AN12/

,54

P54/AN12/

,54

P54/AN12/

,54

P54/AN12/

,54

P54/AN12/

,54

Rev. 2.0, 04/02, page 12 of 906

Pin Name

Pin

No.

Mode 7

Modes 1 and 5

Modes 2 and 6

Mode 4

EXPE = 1

EXPE = 0

Flash Memory

Programmer

Mode

128

P55/AN13/

,54

P55/AN13/

,54

P55/AN13/

,54

P55/AN13/

,54

P55/AN13/

,54

129

P56/AN14/DA2/

,54

P56/AN14/DA2/

,54

P56/AN14/DA2/

,54

P56/AN14/DA2/

,54

P56/AN14/DA2/

,54

130

P57/AN15/DA3/

,54

P57/AN15/DA3/

,54

P57/AN15/DA3/

,54

P57/AN15/DA3/

,54

P57/AN15/DA3/

,54

131

AVss

Vss

132

DCTL

Vss

133

P35/SCK1/(

(CKE)

P35/SCK1/(

(CKE)

P35/SCK1/(

(CKE)

P35/SCK1/(

(CKE)

P35/SCK1

134

P34/SCK0

135

P33/RxD1

136

Vss

137

P32/RxD0/IrRxD

Vcc

138

P31/TxD1

139

P30/TxD0/IrTxD

140

P80/

('5(4

(

,54

)

P80/

('5(4

(

,54

)

P80/

('5(4

(

,54

)

P80/

('5(4

(

,54

)

P80/(

,54

)

141

P81/

('5(4

(

,54

)

P81/

('5(4

(

,54

)

P81/

('5(4

(

,54

)

P81/

('5(4

(

,54

)

P81/(

,54

)

142

P82/

(7(1'

(

,54

)

P82/

(7(1'

(

,54

)

P82/

(7(1'

(

,54

)

P82/

(7(1'

(

,54

)

P82/(

,54

)

143

MD0

Vss

144

MD1

Vss

Notes:

1 The FWE pin is used only in the flash memory version of the H8S/2678 Series. In the

masked ROM and ROMless

versions of the H8S/2678 Series, this is an NC pin.

2 Only for the H8S/2678R Series.

3 Only for the H8S/2678 Series.

Rev. 2.0, 04/02, page 13 of 906

1.3.3

Pin Functions

Table 1.2

Pin Functions

Pin No.

Type

Symbol

FP-144G
(H8S/2678
Series)

FP-144H
(H8S/2678R
Series)

I/O

Function

Power

5, 39, 67,
96, 116

Input

For connection to the power supply.
All V

pins should be connected to

the system power supply.

12, 19, 26,
47, 76, 99,
136

Input

For connection to ground. All V

pins should be connected to the
system power supply (0 V).

PLLV

Input

Power supply pin for the on-chip PLL
oscillator.

PLLV

Input

Ground pin for the on-chip PLL
oscillator.

Clock

XTAL

Input

For connection to a crystal oscillator.
See section 21, Clock Pulse
Generator for typical connection
diagrams for a crystal oscillator and
external clock input.

EXTAL

Input

For connection to a crystal oscillator.
The EXTAL pin can also input an
external clock. See section 21, Clock
Pulse Generator for typical
connection diagrams for a crystal
oscillator and external clock input.

Output Supplies the system clock to

external devices.

SDRAM

106

Output When a synchronous DRAM is

connected, this pin is connected to
the CLK pin of the synchronous
DRAM. For details, refer to section
6, Bus Controller.

Operating
mode control

MD2
MD1
MD0

1, 144, 143 1, 144, 143

Input

These pins set the operating mode.
These pins should not be changed
while the MCU is operating.

Rev. 2.0, 04/02, page 14 of 906

Pin No.

Type

Symbol

FP-144G
(H8S/2678
Series)

FP-144H
(H8S/2678R
Series)

I/O

Function

Operating
mode control

DCTL

132

Input

When this pin is driven high,
SDRAM

dedicated to the

synchronous DRAM is output.

When not using the synchronous
DRAM interface, drive this pin low.
The level of this pin must not be
changed during operation.

System control

5(6

Input

When this pin is driven low, the chip
is reset.

67%<

100

Input

When this pin is driven low, a
transition is made to hardware
standby mode.

%5(4

115

Input

Requests chip to release the bus to
an external bus master.

%5(42

113

Output External bus request signal used

when an internal bus master
accesses external space when the
external bus is released.

%$&.

114

Output Indicates that the bus has been

released to an external bus master.

FWE

Input

Enables/disables flash memory. This
pin is only used in the flash memory
version.

Address bus

A23 to A0 32 to 27,

25 to 20,
18 to 13,
11 to 6

32 to 27,
25 to 20,
18 to 13,
11 to 6

Output These pins output an address.

Data bus

D15 to
D0

72 to 75,
77 to 80,
63 to 66,
68 to 71

Input/
output

These pins constitute a bidirectional
data bus.

Bus control

112, 111,
106 to 101

Output Signals that select division areas 7

to 0 in the external address space.

Output When this pin is low, it indicates that

address output on the address bus is
valid.

Output When this pin is low, it indicates that

the external address space is being
read.

Rev. 2.0, 04/02, page 15 of 906

Pin No.

Type

Symbol

FP-144G
(H8S/2678
Series)

FP-144H
(H8S/2678R
Series)

I/O

Function

Bus control

+:5

Output Strobe signal indicating that external

address space is to be written, and
the upper half (D15 to D8) of the
data bus is enabled.

Write enable signal for DRAM
interface space.

/:5

Output Strobe signal indicating that external

address space is to be written, and
the lower half (D7 to D0) of the data
bus is enabled.

8&$6

Output Upper column address strobe signal

for 16-bit DRAM interface space.

Column address strobe signal for 8-
bit DRAM interface space.

/&$6

Output Lower column address strobe signal

for 16-bit DRAM interface space.

DQMU

Output Upper data mask enable signal for

16-bit synchronous DRAM for 16-bit
synchronous DRAM interface.

Data mask enable signal for 8-bit
synchronous DRAM interface space.

DQML

Output Lower-data mask enable signal for

16-bit synchronous DRAM interface
space.

5$6

103 to 106

Output Row address strobe signal for the

synchronous DRAM interface.

5$6

signal is a row address strobe

signal when areas 2 to 5 are set to
the continuous DRAM space.

5$6

103

Row address strobe signal for the
synchronous DRAM of the
synchronous DRAM interface.

&$6

104

Output Column address strobe signal for the

synchronous DRAM of the
synchronous DRAM interface.

105

Output Write enable signal for the

synchronous DRAM of the
synchronous DRAM interface.

Rev. 2.0, 04/02, page 16 of 906

Pin No.

Type

Symbol

FP-144G
(H8S/2678
Series)

FP-144H
(H8S/2678R
Series)

I/O

Function

Bus control

:$,7

Input

Requests insertion of a wait state in
the bus cycle when accessing
external 3-state address space.

(

)

112, 133

Output Output enable signal for DRAM

interface space.

The output pins of

and (

) are

selected by the port function control
register 2 (PFCR2) of port 3.

CKE
(CKE)

112, 133

Output Clock enable signal of the

synchronous DRAM interface space.

The output pins of CKE and (

&.(

)

are selected by the port function
control register 2 (PFCR2) of port 3.

Interrupt
signals

NMI

Input

Nonmaskable interrupt request pin.
Fix high when not used.

,54

87, 86,
84 to 81,
61, 60,
130 to 127,
110 to 107

(

,54

)

to (

,54

)

59 to 52,
112, 111,
4 to 2,
142 to 140

Input

These pins request a maskable
interrupt.

The input pins of

'5(4Q

and

(

'5(4Q

) are selected by the IRQ

pin select register (ITSR) of the
interrupt controller. (n = 0 to 15)

DMA controller
(DMAC)

'5(4

(

'5(4

)

(

'5(4

)

61, 60, 35,
34

Input

These signals request DMAC
activation.

The input pins of

'5(4Q

and

(

'5(4Q

) are selected by the IRQ

pin select register (ITSR) of the
interrupt controller. (n = 0 to 15)

7(1'

(

7(1'

)

(

7(1'

)

82, 81, 40,
36

Output These signals indicate the end of

DMAC data transfer.

The input pins of

7(1'Q

and

(

7(1'Q

) are selected by the port

function control register 2 (PFCR2)
of port 3. (n = 1, 0)

Rev. 2.0, 04/02, page 17 of 906

Pin No.

Type

Symbol

FP-144G
(H8S/2678
Series)

FP-144H
(H8S/2678R
Series)

I/O

Function

DMA controller
(DMAC)

'$&.

(

'$&.

)

(

'$&.

)

84, 83, 42,
41

Output DMAC single address transfer

acknowledge signals.

The input pins of

'$&.Q

and

(

'$&.Q

) are selected by the port

function control register 2 (PFCR2)
of port 3. (n = 1, 0)

EXDMA
controller
(EXDMAC)

('5(4

141, 140,
35, 34

Input

These signals request EXDMAC
activation.

(7(1'

2, 142, 40,
36

Output These signals indicate the end of

EXDMAC data transfer.

('$&.

4, 3, 42, 41 4, 3, 42, 41

Output EXDMAC single address transfer

acknowledge signals.

('5$.

51, 50, 59,
58

Output These signals notify an external

device of acceptance and start of
execution of a DMA transfer request.

16-bit timer
pulse unit
(TPU)

TCLKA
TCLKB
TCLKC
TCLKD

45, 46, 49,
51

Input

External clock input pins.

TIOCA0
TIOCB0
TIOCC0
TIOCD0

43, 44, 45,
46

Input/
output

TGRA_0 to TGRD_0 input capture
input/output compare output/PWM
output pins.

TIOCA1
TIOCB1

48, 49

Input/
output

TGRA_1 and TGRB_1 input capture
input/output compare output/PWM
output pins.

TIOCA2
TIOCB2

50, 51

Input/
output

TGRA_2 and TGRB_2 input capture
input/output compare output/PWM
output pins.

TIOCA3
TIOCB3
TIOCC3
TIOCD3

52, 53, 54,
55

Input/
output

TGRA_3 to TGRD_3 input capture
input/output compare output/PWM
output pins.

TIOCA4
TIOCB4

56, 57

Input/
output

TGRA_4 and TGRB_4 input capture
input/output compare output/PWM
output pins.

Rev. 2.0, 04/02, page 18 of 906

Pin No.

Type

Symbol

FP-144G
(H8S/2678
Series)

FP-144H
(H8S/2678R
Series)

I/O

Function

16-bit timer
pulse unit
(TPU)

TIOCA5,
TIOCB5

58, 59

Input/
output

TGRA_5 and TGRB_5 input capture
input/output compare output/PWM
output pins.

Programmable
pulse
generator
(PPG)

PO15 to
PO0

51 to 48,
46 to 43,
59 to 52

Output Pulse output pins.

8-bit timer

TMO0
TMO1

83, 84

Output Waveform output pins with output

compare function.

TMCI0
TMCI1

81, 82

Input

External event input pins.

TMRI0
TMRI1

60, 61

Input

Counter reset input pins.

Watchdog
timer (WDT)

:'729)

Output Counter overflow signal output pin in

watchdog timer mode.

TxD2
TxD1
TxD0/IrTx
D

107, 138,
139

Output Data output pins.

Serial commu-
nication
interface
(SCI)/smart
card interface
(SCI_0 with
IrDA function)

RxD2
RxD1
RxD0/
IrRxD

108, 135,
137

Input

Data input pins.

SCK2
SCK1
SCK0

109, 133,
134

Input/
output

Clock input/output pins.

A/D converter

AN15 to
AN12,
AN7 to
AN0

130 to 127,
126 to 123,
120 to 117

Input

Analog input pins for the A/D
converter.

$'75*

110

Input

Pin for input of an external trigger to
start A/D conversion.

D/A converter

DA3 to
DA0

130, 129,
126, 125

Output Analog input pins for the D/A

converter.

A/D converter,
D/A converter

122

Input

The analog power-supply pin for the
A/D converter and D/A converter.

When the A/D converter and D/A
converter are not used, this pin
should be connected to the system
power supply (+3 V).

Rev. 2.0, 04/02, page 19 of 906

Pin No.

Type

Symbol

FP-144G
(H8S/2678
Series)

FP-144H
(H8S/2678R
Series)

I/O

Function

A/D converter,
D/A converter

131

Input

The ground pin for the A/D converter
and D/A converter.

This pin should be connected to the
system power supply (0 V).

Vref

121

Input

The reference voltage input pin for
the A/D converter and D/A converter.

When the A/D converter and D/A
converter are not used, this pin
should be connected to the system
power supply (+3 V).

I/O ports

P17 to
P10

51 to 48,
46 to 43

Input/
output

Eight input/output pins.

P27 to
P20

59 to 52

Input/
output

Eight input/output pins.

P35 to
P30

133 to 135,
137 to 139

Input/
output

Six input/output pins.

P47 to
P40

126 to 123,
120 to 117

Input

Eight input pins.

P57 to
P54

130 to 127 130 to 127

Input

Four input pins.

P53 to
P50

110 to 107 110 to 107

Input/
output

Four input/output pins.

P65 to
P60

84 to 81,
61, 60

Input/
output

Six input/output pins.

P75 to
P70

42 to 40,
36 to 34

Input/
output

Six input/output pins.

P85 to
P80

4 to 2,
142 to 140

Input/
output

Six input/output pins.

PA7 to
PA0

32 to 27,
25, 24

Input/
output

Eight input/output pins.

PB7 to
PB0

23 to 20,
18 to 15

Input/
output

Eight input/output pins.

PC7 to
PC0

14, 13,
11 to 6

Input/
output

Eight input/output pins.

Rev. 2.0, 04/02, page 21 of 906

Section 2 CPU

The H8S/2600 CPU is a high-speed central processing unit with an internal 32-bit architecture that
is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2600 CPU has sixteen 16-bit
general registers, can address a 16-Mbyte linear address space, and is ideal for realtime control.
This section describes the H8S/2600 CPU. The usable modes and address spaces differ depending
on the product. For details on each product, refer to section 3, MCU Operating Modes.

2.1

Features

Upward-compatible with H8/300 and H8/300H CPUs

Can execute H8/300 and H8/300H object programs

General-register architecture

Sixteen 16-bit general registers also usable as sixteen 8-bit registers or eight 32-bit registers

Sixty-nine basic instructions

8/16/32-bit arithmetic and logic instructions

Multiply and divide instructions

Powerful bit-manipulation instructions

Multiply-and-accumulate instruction

Eight addressing modes

Absolute address [@aa:8, @aa:16, @aa:24, or @aa:32]

Immediate [#xx:8, #xx:16, or #xx:32]

Program-counter relative [@(d:8,PC) or @(d:16,PC)]

Memory indirect [@@aa:8]

16-Mbyte address space

Program: 16 Mbytes

Data: 16 Mbytes

High-speed operation

All frequently-used instructions execute in one or two states

8/16/32-bit register-register add/subtract: 1 state

8-bit register-register multiply: 3 states

16 ÷ 8-bit register-register divide: 12 states

16-bit register-register multiply: 4 states

32 ÷ 16-bit register-register divide: 20 states

CPUS260A_020020020400

Rev. 2.0, 04/02, page 22 of 906

Two CPU operating modes

Normal mode*

Advanced mode

Power-down state

Transition to power-down state by SLEEP instruction

CPU clock speed selection

Note:

Normal mode is not available in this LSI.

2.1.1

Differences between H8S/2600 CPU and H8S/2000 CPU

The differences between the H8S/2600 CPU and the H8S/2000 CPU are as shown below.

The MAC register is supported only by the H8S/2600 CPU.

Basic instructions

The four instructions MAC, CLRMAC, LDMAC, and STMAC are supported only by the
H8S/2600 CPU.

The number of execution states of the MULXU and MULXS instructions

Execution States

Instruction

Mnemonic

H8S/2600

H8S/2000

MULXU

MULXU.B Rs, Rd

MULXU.W Rs, ERd

MULXS

MULXS.B Rs, Rd

MULXS.W Rs, ERd

In addition, there are differences in address space, CCR and EXR register functions, power-down
modes, etc., depending on the model.

2.1.2

Differences from H8/300 CPU

In comparison to the H8/300 CPU, the H8S/2600 CPU has the following enhancements.

More general registers and control registers

Eight 16-bit expanded registers, and one 8-bit and two 32-bit control registers, have been
added.

Expanded address space

Normal mode supports the same 64-kbyte address space as the H8/300 CPU.

Advanced mode supports a maximum 16-Mbyte address space.

Rev. 2.0, 04/02, page 23 of 906

Enhanced addressing

The addressing modes have been enhanced to make effective use of the 16-Mbyte address
space.

Enhanced instructions

Addressing modes of bit-manipulation instructions have been enhanced.

Signed multiply and divide instructions have been added.

A multiply-and-accumulate instruction has been added.

Two-bit shift and rotate instructions have been added.

Instructions for saving and restoring multiple registers have been added.

A test and set instruction has been added.

Higher speed

Basic instructions execute twice as fast.

Note:

Normal mode is not available in this LSI.

2.1.3

Differences from H8/300H CPU

In comparison to the H8/300H CPU, the H8S/2600 CPU has the following enhancements.

Additional control register

One 8-bit and two 32-bit control registers have been added.

Enhanced instructions

Addressing modes of bit-manipulation instructions have been enhanced.

A multiply-and-accumulate instruction has been added.

Two-bit shift and rotate instructions have been added.

Instructions for saving and restoring multiple registers have been added.

A test and set instruction has been added.

Higher speed

Basic instructions execute twice as fast.

2.2

CPU Operating Modes

The H8S/2600 CPU has two operating modes: normal and advanced. Normal mode supports a
maximum 64-kbyte address space. Advanced mode supports a maximum 16-Mbyte total address
space. The mode is selected by the mode pins.

2.2.1

Normal Mode

The exception vector table and stack have the same structure as in the H8/300 CPU.

Rev. 2.0, 04/02, page 24 of 906

Address Space

The H8S/2600 CPU provides linear access to a maximum 64-kbyte address space.

Extended Registers (En)

The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit
segments of 32-bit registers.

When En is used as a 16-bit register it can contain any value, even when the corresponding
general register (Rn) is used as an address register. If the general register is referenced in the
register indirect addressing mode with pre-decrement (@Rn) or post-increment (@Rn+) and a
carry or borrow occurs, however, the value in the corresponding extended register (En) will be
affected.

Instruction Set

All instructions and addressing modes can be used. Only the lower 16 bits of effective
addresses (EA) are valid.

Exception Vector Table and Memory Indirect Branch Addresses

In normal mode the top area starting at H'0000 is allocated to the exception vector table. One
branch address is stored per 16 bits. The exception vector table in normal mode is shown in
figure 2.1. For details of the exception vector table, see section 4, Exception Handling.

The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions
uses an 8-bit absolute address included in the instruction code to specify a memory operand
that contains a branch address. In normal mode the operand is a 16-bit word operand,
providing a 16-bit branch address. Branch addresses can be stored in the top area from H'0000
to H'00FF. Note that this area is also used for the exception vector table.

Stack Structure

When the program counter (PC) is pushed onto the stack in a subroutine call, and the PC,
condition-code register (CCR), and extended control register (EXR) are pushed onto the stack
in exception handling, they are stored as shown in figure 2.2. EXR is not pushed onto the
stack in interrupt control mode 0. For details, see section 4, Exception Handling.

Note:

Normal mode is not available in this LSI.

Rev. 2.0, 04/02, page 26 of 906

Exception Vector Table and Memory Indirect Branch Addresses

In advanced mode the top area starting at H'00000000 is allocated to the exception vector table
in units of 32 bits. In each 32 bits, the upper 8 bits are ignored and a branch address is stored in
the lower 24 bits (figure 2.3). For details of the exception vector table, see section 4, Exception
Handling.

H'00000000

H'00000003

H'00000004

H'0000000B

H'0000000C

H'00000010

H'00000008

H'00000007

Reserved

Reset exception vector

(Reserved for system use)

Exception vector table

Exception vector 1

Figure 2.3 Exception Vector Table (Advanced Mode)

In advanced mode the operand is a 32-bit longword operand, providing a 32-bit branch
address. The upper 8 bits of these 32 bits are a reserved area that is regarded as H'00. Branch
addresses can be stored in the area from H'00000000 to H'000000FF. Note that the first part of
this range is also used for the exception vector table.

Stack Structure

In advanced mode, when the program counter (PC) is pushed onto the stack in a subroutine
call, and the PC, condition-code register (CCR), and extended control register (EXR) are
pushed onto the stack in exception handling, they are stored as shown in figure 2.4. EXR is not
pushed onto the stack in interrupt control mode 0. For details, see section 4, Exception
Handling.

Rev. 2.0, 04/02, page 29 of 906

2.4

Registers

The H8S/2600 CPU has the internal registers shown in figure 2.6. There are two types of registers:
general registers and control registers. Control registers are a 24-bit program counter (PC), an 8-
bit extended register (EXR), an 8-bit condition code register (CCR), and a 64-bit multiply-
accumulate register (MAC).

I2 I1 I0

EXR

7 6 5 4 3 2 1 0

MACH

MACL

MAC

0 7

R0H

R1H

R2H

R3H

R4H

R5H

R6H

R7H

R0L

R1L

R2L

R3L

R4L

R5L

R6L

R7L

SP
PC
EXR
T
I2 to I0
CCR
I
UI

:Stack pointer
:Program counter
:Extended register
:Trace bit
:Interrupt mask bits
:Condition-code register
:Interrupt mask bit
:User bit or interrupt mask bit

:Half-carry flag
:User bit
:Negative flag
:Zero flag
:Overflow flag
:Carry flag
:Multiply-accumulate register

ER0

ER1

ER2

ER3

ER4

ER5

ER6

ER7 (SP)

I UI H U N Z V C

CCR

7 6 5 4 3 2 1 0

H
U
N
Z
V
C
MAC

General Registers (Rn) and Extended Registers (En)

Control Registers (CR)

Legend

Sign extension

- - - -

Note:

UI cannot be used as an interrupt mask bit in this LSI.

Figure 2.6 CPU Registers

Rev. 2.0, 04/02, page 30 of 906

2.4.1

General Registers

The H8S/2600 CPU has eight 32-bit general registers. These general registers are all functionally
alike and can be used as both address registers and data registers. When a general register is used
as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. Figure 2.7 illustrates the
usage of the general registers. When the general registers are used as 32-bit registers or address
registers, they are designated by the letters ER (ER0 to ER7).

The ER registers divide into 16-bit general registers designated by the letters E (E0 to E7) and R
(R0 to R7). These registers are functionally equivalent, providing a maximum sixteen 16-bit
registers. The E registers (E0 to E7) are also referred to as extended registers.

The R registers divide into 8-bit general registers designated by the letters RH (R0H to R7H) and
RL (R0L to R7L). These registers are functionally equivalent, providing a maximum sixteen 8-bit
registers.

The usage of each register can be selected independently.

General register ER7 has the function of stack pointer (SP) in addition to its general-register
function, and is used implicitly in exception handling and subroutine calls. Figure 2.8 shows the
stack.

· Address registers
· 32-bit registers

· 16-bit registers

· 8-bit registers

ER registers

(ER0 to ER7)

E registers (extended registers)

(E0 to E7)

R registers

(R0 to R7)

RH registers

(R0H to R7H)

RL registers

(R0L to R7L)

Figure 2.7 Usage of General Registers

Rev. 2.0, 04/02, page 31 of 906

SP (ER7)

Free area

Stack area

Figure 2.8 Stack

2.4.2

Program Counter (PC)

This 24-bit counter indicates the address of the next instruction the CPU will execute. The length
of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When an
instruction is fetched, the least significant PC bit is regarded as 0.)

2.4.3

Extended Register (EXR)

EXR is an 8-bit register that can be manipulated by the LDC, STC, ANDC, ORC, and XORC
instructions. When these instructions except for the STC instruction is executed, all interrupts
including NMI will be masked for three states after execution is completed.

Bit

Bit Name

Initial Value

R/W

Description

R/W

Trace Bit

When this bit is set to 1, a trace exception is
started each time an instruction is executed.
When this bit is cleared to 0, instructions are
executed in sequence.

6 to 3

All 1

Reserved

These bits are always read as 1.

2
1
0

I2
I1
I0

1
1
1

R/W
R/W
R/W

These bits designate the interrupt mask level (0 to
7). For details, refer to section 5, Interrupt
Controller.

Rev. 2.0, 04/02, page 32 of 906

2.4.4

Condition-Code Register (CCR)

This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and
half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags.

Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC
instructions. The N, Z, V, and C flags are used as branching conditions for conditional branch
(Bcc) instructions.

Bit

Bit Name

Initial Value

R/W

Description

R/W

Interrupt Mask Bit

Masks interrupts other than NMI when set to 1.
NMI is accepted regardless of the I bit setting.
The I bit is set to 1 by hardware at the start of an
exception-handling sequence. For details, refer to
section 5, Interrupt Controller.

Undefined

R/W

User Bit or Interrupt Mask Bit

Can be written and read by software using the
LDC, STC, ANDC, ORC, and XORC instructions.
This bit cannot be used as an interrupt mask bit in
this LSI.

Undefined

R/W

Half-Carry Flag

When the ADD.B, ADDX.B, SUB.B, SUBX.B,
CMP.B, or NEG.B instruction is executed, this
flag is set to 1 if there is a carry or borrow at bit 3,
and cleared to 0 otherwise. When the ADD.W,
SUB.W, CMP.W, or NEG.W instruction is
executed, the H flag is set to 1 if there is a carry
or borrow at bit 11, and cleared to 0 otherwise.
When the ADD.L, SUB.L, CMP.L, or NEG.L
instruction is executed, the H flag is set to 1 if
there is a carry or borrow at bit 27, and cleared to
0 otherwise.

Undefined

R/W

User Bit

Can be written and read by software using the
LDC, STC, ANDC, ORC, and XORC instructions.

Undefined

R/W

Negative Flag

Stores the value of the most significant bit of data
as a sign bit.

Undefined

R/W

Zero Flag

Set to 1 to indicate zero data, and cleared to 0 to
indicate non-zero data.

Rev. 2.0, 04/02, page 33 of 906

Bit

Bit Name

Initial Value

R/W

Description

Undefined

R/W

Overflow Flag

Set to 1 when an arithmetic overflow occurs, and
cleared to 0 otherwise.

Undefined

R/W

Carry Flag

Set to 1 when a carry occurs, and cleared to 0
otherwise. Used by:

Add instructions, to indicate a carry

Subtract instructions, to indicate a borrow

Shift and rotate instructions, to indicate a

carry

The carry flag is also used as a bit accumulator
by bit manipulation instructions.

2.4.5

Multiply-Accumulate Register (MAC)

This 64-bit register stores the results of multiply-and-accumulate operations. It consists of two 32-
bit registers denoted MACH and MACL. The lower 10 bits of MACH are valid; the upper bits are
a sign extension.

2.4.6

Initial Values of CPU Internal Registers

When the reset exception handling loads the start address from the vector address, PC is
initialized, the T bit in EXR is cleared to 0, and the I bits in EXR and CCR are set to 1. However,
the general registers and the other CCR bits are not initialized. The initial value of SP (ER7) is
undefined. SP should therefore be initialized by using the MOV.L instruction immediately after a
reset.

2.5

Data Formats

The H8S/2600 CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit
(longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2,
..., 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two
digits of 4-bit BCD data.

Rev. 2.0, 04/02, page 37 of 906

2.6

Instruction Set

The H8S/2600 CPU has 69 types of instructions. The instructions are classified by function in
table 2.1.

Table 2.1

Instruction Classification

Function

Instructions

Size

Types

Data transfer

MOV

B/W/L

POP

, PUSH

W/L

LDM, STM

MOVFPE

, MOVTPE

ADD, SUB, CMP, NEG

B/W/L

Arithmetic
operations

ADDX, SUBX, DAA, DAS

INC, DEC

B/W/L

ADDS, SUBS

MULXU, DIVXU, MULXS, DIVXS

B/W

EXTU, EXTS

W/L

TAS

MAC, LDMAC, STMAC, CLRMAC

Logic operations

AND, OR, XOR, NOT

B/W/L

Shift

SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR

B/W/L

Bit manipulation

BSET, BCLR, BNOT, BTST, BLD, BILD, BST, BIST, BAND,
BIAND, BOR, BIOR, BXOR, BIXOR

Branch

Bcc

, JMP, BSR, JSR, RTS

System control

TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP --

Block data transfer EEPMOV

Total: 69

Notes: B: byte size; W: word size; L: longword size.

1. POP.W Rn and PUSH.W Rn are identical to MOV.W @SP+, Rn and MOV.W Rn,

@-SP. POP.L ERn and PUSH.L ERn are identical to MOV.L @SP+, ERn and MOV.L
ERn, @-SP.

2. Bcc is the general name for conditional branch instructions.

3. Cannot be used in this LSI.

4. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.

Rev. 2.0, 04/02, page 38 of 906

2.6.1

Table of Instructions Classified by Function

Tables 2.3 to 2.10 summarize the instructions in each functional category. The notation used in
tables 2.3 to 2.10 is defined below.

Table 2.2 Operation Notation

Symbol

Description

General register (destination)

General register (source)

General register

ERn

General register (32-bit register)

MAC

Multiply-accumulate register (32-bit register)

(EAd)

Destination operand

(EAs)

Source operand

EXR

Extended register

CCR

Condition-code register

N (negative) flag in CCR

Z (zero) flag in CCR

V (overflow) flag in CCR

C (carry) flag in CCR

Program counter

Stack pointer

#IMM

Immediate data

disp

Displacement

Addition

Subtraction

Multiplication

Division

Logical AND

Logical OR

Logical exclusive OR

Move

NOT (logical complement)

:8/:16/:24/:32

8-, 16-, 24-, or 32-bit length

Note: General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0 to

R7, E0 to E7), and 32-bit registers (ER0 to ER7).

Rev. 2.0, 04/02, page 40 of 906

Table 2.4

Arithmetic Operations Instructions (1)

Instruction

Size

Function

ADD
SUB

B/W/L

Rd ± Rs

Rd, Rd ± #IMM

Performs addition or subtraction on data in two general registers, or on
immediate data and data in a general register. (Immediate byte data
cannot be subtracted from byte data in a general register. Use the SUBX
or ADD instruction.)

ADDX
SUBX

Rd ± Rs ± C

Rd, Rd ± #IMM ± C

Performs addition or subtraction with carry or borrow on byte data in two
general registers, or on immediate data and data in a general register.

INC
DEC

B/W/L

Rd ± 1

Rd, Rd ± 2

Increments or decrements a general register by 1 or 2. (Byte operands
can be incremented or decremented by 1 only.)

ADDS
SUBS

Rd ± 1

Rd, Rd ± 2

Rd, Rd ± 4

Adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit register.

DAA
DAS

Rd (decimal adjust)

Decimal-adjusts an addition or subtraction result in a general register by
referring to the CCR to produce 4-bit BCD data.

MULXU

B/W

Performs unsigned multiplication on data in two general registers:
either 8 bits

8 bits

16 bits or 16 bits

16 bits

32 bits.

MULXS

B/W

Performs signed multiplication on data in two general registers:
either 8 bits

8 bits

16 bits or 16 bits

16 bits

32 bits.

DIVXU

B/W

Rd ÷ Rs

Performs unsigned division on data in two general registers:
either 16 bits ÷ 8 bits

8-bit quotient and 8-bit remainder or

32 bits ÷ 16 bits

16-bit quotient and 16-bit remainder.

Note: Size refers to the operand size.

B: Byte

W: Word

L: Longword

Rev. 2.0, 04/02, page 41 of 906

Table 2.4

Arithmetic Operations Instructions (2)

Instruction

Size

Function

DIVXS

B/W

Rd ÷ Rs

Performs signed division on data in two general registers:
either 16 bits ÷ 8 bits

8-bit quotient and 8-bit remainder or

32 bits ÷ 16 bits

16-bit quotient and 16-bit remainder.

CMP

B/W/L

Rd Rs, Rd #IMM
Compares data in a general register with data in another general register
or with immediate data, and sets CCR bits according to the result.

NEG

B/W/L

0 Rd

Takes the two's complement (arithmetic complement) of data in a
general register.

EXTU

W/L

Rd (zero extension)

Extends the lower 8 bits of a 16-bit register to word size, or the lower 16
bits of a 32-bit register to longword size, by padding with zeros on the
left.

EXTS

W/L

Rd (sign extension)

Extends the lower 8 bits of a 16-bit register to word size, or the lower 16
bits of a 32-bit register to longword size, by extending the sign bit.

TAS

@ERd 0, 1

(<bit 7> of @ERd)

Tests memory contents, and sets the most significant bit (bit 7) to 1.

MAC

(EAs)

(EAd) + MAC

MAC

Performs signed multiplication on memory contents and adds the result
to the multiply-accumulate register. The following operations can be
performed:
16 bits

16 bits + 32 bits

32 bits, saturating

16 bits

16 bits + 42 bits

42 bits, non-saturating

CLRMAC

MAC

Clears the multiply-accumulate register to zero.

LDMAC
STMAC

MAC, MAC

Transfers data between a general register and a multiply-accumulate
register.

Note: 1

Size refers to the operand size.

B: Byte

W: Word

L: Longword

2. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.

Rev. 2.0, 04/02, page 42 of 906

Table 2.5

Logic Operations Instructions

Instruction

Size

Function

AND

B/W/L

Rd, Rd

#IMM

Performs a logical AND operation on a general register and another
general register or immediate data.

B/W/L

Rd, Rd

#IMM

Performs a logical OR operation on a general register and another
general register or immediate data.

XOR

B/W/L

Rd, Rd

#IMM

Performs a logical exclusive OR operation on a general register and
another general register or immediate data.

NOT

B/W/L

¬ (Rd)

(Rd)

Takes the one's complement (logical complement) of general register
contents.

Note: Size refers to the operand size.

B: Byte

W: Word

L: Longword

Table 2.6

Shift Instructions

Instruction

Size

Function

SHAL
SHAR

B/W/L

Rd (shift)

Performs an arithmetic shift on general register contents.
1-bit or 2-bit shift is possible.

SHLL
SHLR

B/W/L

Rd (shift)

Performs a logical shift on general register contents.
1-bit or 2-bit shift is possible.

ROTL
ROTR

B/W/L

Rd (rotate)

Rotates general register contents.
1-bit or 2-bit rotation is possible.

ROTXL
ROTXR

B/W/L

Rd (rotate)

Rotates general register contents through the carry flag.
1-bit or 2-bit rotation is possible.

Note: Size refers to the operand size.

B: Byte

W: Word

L: Longword

Rev. 2.0, 04/02, page 43 of 906

Table 2.7

Bit Manipulation Instructions (1)

Instruction

Size

Function

BSET

(<bit-No.> of <EAd>)

Sets a specified bit in a general register or memory operand to 1. The bit
number is specified by 3-bit immediate data or the lower three bits of a
general register.

BCLR

(<bit-No.> of <EAd>)

Clears a specified bit in a general register or memory operand to 0. The
bit number is specified by 3-bit immediate data or the lower three bits of a
general register.

BNOT

¬ (<bit-No.> of <EAd>)

(<bit-No.> of <EAd>)

Inverts a specified bit in a general register or memory operand. The bit
number is specified by 3-bit immediate data or the lower three bits of a
general register.

BTST

¬ (<bit-No.> of <EAd>)

Tests a specified bit in a general register or memory operand and sets or
clears the Z flag accordingly. The bit number is specified by 3-bit
immediate data or the lower three bits of a general register.

BAND

BIAND

(<bit-No.> of <EAd>)

ANDs the carry flag with a specified bit in a general register or memory
operand and stores the result in the carry flag.

¬ (<bit-No.> of <EAd>)

ANDs the carry flag with the inverse of a specified bit in a general
register or memory operand and stores the result in the carry flag.
The bit number is specified by 3-bit immediate data.

BOR

BIOR

(<bit-No.> of <EAd>)

ORs the carry flag with a specified bit in a general register or memory
operand and stores the result in the carry flag.

¬ (<bit-No.> of <EAd>)

ORs the carry flag with the inverse of a specified bit in a general register
or memory operand and stores the result in the carry flag.
The bit number is specified by 3-bit immediate data.

Note: Size refers to the operand size.

B: Byte

Rev. 2.0, 04/02, page 44 of 906

Table 2.7

Bit Manipulation Instructions (2)

Instruction

Size

Function

BXOR

BIXOR

(<bit-No.> of <EAd>)

Exclusive-ORs the carry flag with a specified bit in a general register or
memory operand and stores the result in the carry flag.

¬ (<bit-No.> of <EAd>)

Exclusive-ORs the carry flag with the inverse of a specified bit in a
general register or memory operand and stores the result in the carry
flag.
The bit number is specified by 3-bit immediate data.

BLD

BILD

(<bit-No.> of <EAd>)

Transfers a specified bit in a general register or memory operand to the
carry flag.

¬ (<bit-No.> of <EAd>)

Transfers the inverse of a specified bit in a general register or memory
operand to the carry flag.
The bit number is specified by 3-bit immediate data.

BST

BIST

(<bit-No.> of <EAd>)

Transfers the carry flag value to a specified bit in a general register or
memory operand.

¬ C

(<bit-No.> of <EAd>)

Transfers the inverse of the carry flag value to a specified bit in a general
register or memory operand.
The bit number is specified by 3-bit immediate data.

Note: Size refers to the operand size.

B: Byte

Rev. 2.0, 04/02, page 46 of 906

Table 2.9

System Control Instructions

Instruction

Size

Function

TRAPA

Starts trap-instruction exception handling.

RTE

Returns from an exception-handling routine.

SLEEP

Causes a transition to a power-down state.

LDC

B/W

(EAs)

CCR, (EAs)

EXR

Moves the contents of a general register or memory, or immediate data
to CCR or EXR. Although CCR and EXR are 8-bit registers, word-size
transfers are performed between them and memory. The upper 8 bits are
valid.

STC

B/W

CCR

(EAd), EXR

(EAd)

Transfers CCR or EXR contents to a general register or memory.
Although CCR and EXR are 8-bit registers, word-size transfers are
performed between them and memory. The upper 8 bits are valid.

ANDC

CCR

#IMM

CCR, EXR

#IMM

EXR

Logically ANDs the CCR or EXR contents with immediate data.

ORC

CCR

#IMM

CCR, EXR

#IMM

EXR

Logically ORs the CCR or EXR contents with immediate data.

XORC

CCR

#IMM

CCR, EXR

#IMM

EXR

Logically exclusive-ORs the CCR or EXR contents with immediate data.

NOP

PC + 2

Only increments the program counter.

Note: Size refers to the operand size.

B: Byte

W: Word

Rev. 2.0, 04/02, page 48 of 906

Operation Field

Indicates the function of the instruction, the addressing mode, and the operation to be carried
out on the operand. The operation field always includes the first four bits of the instruction.
Some instructions have two operation fields.

Specifies a general register. Address registers are specified by 3 bits, data registers by 3 bits or
4 bits. Some instructions have two register fields. Some have no register field.

Effective Address Extension

8, 16, or 32 bits specifying immediate data, an absolute address, or a displacement.

Condition Field

Specifies the branching condition of Bcc instructions.

r n

r m

NOP, RTS, etc.

ADD.B Rn, Rm, etc.

MOV.B @(d:16, Rn), Rm, etc.

r n

r m

EA (disp)

BRA d:16, etc.

(1) Operation field only

(2) Operation field and register fields

(3) Operation field, register fields, and effective address extension

(4) Operation field, effective address extension, and condition field

Figure 2.11 Instruction Formats (Examples)

2.7

Addressing Modes and Effective Address Calculation

The H8S/2600 CPU supports the eight addressing modes listed in table 2.11. The usable address
modes are different in each instruction.

Arithmetic and logic instructions can use the register direct and immediate modes. Data transfer
instructions can use all addressing modes except program-counter relative and memory indirect.
Bit manipulation instructions use register direct, register indirect, or absolute addressing mode to
specify an operand, and register direct (BSET, BCLR, BNOT, and BTST instructions) or
immediate (3-bit) addressing mode to specify a bit number in the operand.

Rev. 2.0, 04/02, page 49 of 906

Table 2.11

Addressing Modes

No.

Addressing Mode

Symbol

@ERn

@(d:16,ERn)/@(d:32,ERn)

@ERn+
@ERn

Absolute address

@aa:8/@aa:16/@aa:24/@aa:32

Immediate

#xx:8/#xx:16/#xx:32

Program-counter relative

@(d:8,PC)/@(d:16,PC)

Memory indirect

@@aa:8

2.7.1

Register Direct--Rn

The register field of the instruction code specifies an 8-, 16-, or 32-bit general register containing
the operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0 to R7 and E0 to
E7 can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit registers.

2.7.2

Register Indirect--@ERn

The register field of the instruction code specifies an address register (ERn) which contains the
address of the operand on memory. If the address is a program instruction address, the lower 24
bits are valid and the upper 8 bits are all assumed to be 0 (H'00).

2.7.3

Register Indirect with Displacement--@(d:16, ERn) or @(d:32, ERn)

A 16-bit or 32-bit displacement contained in the instruction is added to an address register (ERn)
specified by the register field of the instruction code, and the sum gives the address of a memory
operand. A 16-bit displacement is sign-extended when added.

2.7.4

Register Indirect with Post-Increment or Pre-Decrement--@ERn+ or @-ERn

Register indirect with post-increment--@ERn+: The register field of the instruction code
specifies an address register (ERn) which contains the address of a memory operand. After the
operand is accessed, 1, 2, or 4 is added to the address register contents and the sum is stored in the
address register. The value added is 1 for byte access, 2 for word transfer instruction, or 4 for
longword transfer instruction. For word or longword transfer instruction, the register value should
be even.

Rev. 2.0, 04/02, page 50 of 906

Register indirect with pre-decrement--@-ERn: The value 1, 2, or 4 is subtracted from an
address register (ERn) specified by the register field in the instruction code, and the result
becomes the address of a memory operand. The result is also stored in the address register. The
value subtracted is 1 for byte access, 2 for word transfer instruction, or 4 for longword transfer
instruction. For word or longword transfer instruction, the register value should be even.

2.7.5

Absolute Address--@aa:8, @aa:16, @aa:24, or @aa:32

The instruction code contains the absolute address of a memory operand. The absolute address
may be 8 bits long (@aa:8), 16 bits long (@aa:16), 24 bits long (@aa:24), or 32 bits long
(@aa:32). Table 2.12 indicates the accessible absolute address ranges.

To access data, the absolute address should be 8 bits (@aa:8), 16 bits (@aa:16), or 32 bits
(@aa:32) long. For an 8-bit absolute address, the upper 24 bits are all assumed to be 1 (H'FFFF).
For a 16-bit absolute address, the upper 16 bits are a sign extension. A 32-bit absolute address can
access the entire address space.

A 24-bit absolute address (@aa:24) indicates the address of a program instruction. The upper 8
bits are all assumed to be 0 (H'00).

Table 2.12

Absolute Address Access Ranges

Absolute Address

Normal Mode

Advanced Mode

Data address

8 bits (@aa:8)

H'FF00 to H'FFFF

H'FFFF00 to H'FFFFFF

16 bits (@aa:16)

H'0000 to H'FFFF

H'000000 to H'007FFF,
H'FF8000 to H'FFFFFF

32 bits (@aa:32)

H'000000 to H'FFFFFF

Program instruction
address

24 bits (@aa:24)

Note: Not available in this LSI.

2.7.6

Immediate--#xx:8, #xx:16, or #xx:32

The instruction code contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as
an operand.

The ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. Some bit
manipulation instructions contain 3-bit immediate data in the instruction code, specifying a bit
number. The TRAPA instruction contains 2-bit immediate data in its instruction code, specifying a
vector address.

Rev. 2.0, 04/02, page 51 of 906

2.7.7

Program-Counter Relative--@(d:8, PC) or @(d:16, PC)

This mode is used in the Bcc and BSR instructions. An 8-bit or 16-bit displacement contained in
the instruction code is sign-extended and added to the 24-bit PC contents to generate a branch
address. Only the lower 24 bits of this branch address are valid; the upper 8 bits are all assumed to
be 0 (H'00). The PC value to which the displacement is added is the address of the first byte of the
next instruction, so the possible branching range is 126 to +128 bytes (63 to +64 words) or
32766 to +32768 bytes (16383 to +16384 words) from the branch instruction. The resulting value
should be an even number.

2.7.8

Memory Indirect--@@aa:8

This mode can be used by the JMP and JSR instructions. The instruction code contains an 8-bit
absolute address specifying a memory operand. This memory operand contains a branch address.
The upper bits of the absolute address are all assumed to be 0, so the address range is 0 to 255
(H'0000 to H'00FF in normal mode, H'000000 to H'0000FF in advanced mode).

In normal mode the memory operand is a word operand and the branch address is 16 bits long. In
advanced mode the memory operand is a longword operand, the first byte of which is assumed to
be all 0 (H'00). Note that the first part of the address range is also the exception vector area. For
further details, refer to section 4, Exception Handling.

If an odd address is specified in word or longword memory access, or as a branch address, the
least significant bit is regarded as 0, causing data to be accessed or instruction code to be fetched
at the address preceding the specified address. (For further information, see section 2.5.2, Memory
Data Formats.)

Note: Normal mode is not available in this LSI.

Specified
by @aa:8

Branch address

Reserved

(a) Normal Mode

(a) Advanced Mode

Note:

Normal mode is not available in this LSI.

Figure 2.12 Branch Address Specification in Memory Indirect Mode

Rev. 2.0, 04/02, page 52 of 906

2.7.9

Effective Address Calculation

Table 2.13 indicates how effective addresses are calculated in each addressing mode. In normal
mode the upper 8 bits of the effective address are ignored in order to generate a 16-bit address.

Note: Normal mode is not available in this LSI.

Table 2.13

Effective Address Calculation (1)

Offset

1
2
4

disp

Don't care

disp

Don't care

Addressing Mode and Instruction Format

Effective Address Calculation

Effective Address (EA)

General register contents

Sign extension

·Register indirect with pre-decrement @-ERn

1, 2, or 4

Operand Size

Byte

Word

Longword

Operand is general register contents.

Rev. 2.0, 04/02, page 54 of 906

2.8

Processing States

The H8S/2600 CPU has five main processing states: the reset state, exception handling state,
program execution state, bus-released state, and program stop state. Figure 2.13 indicates the state
transitions.

Reset State

The CPU and on-chip peripheral modules are all initialized and stop. When the

#$ input goes

low, all current processing stops and the CPU enters the reset state. All interrupts are masked
in the reset state. Reset exception handling starts when the

#$ signal changes from low to

high. For details, refer to section 4, Exception Handling.

The reset state can also be entered by a watchdog timer overflow.

Exception-Handling State

The exception-handling state is a transient state that occurs when the CPU alters the normal
processing flow due to an exception source, such as, a reset, trace, interrupt, or trap instruction.
The CPU fetches a start address (vector) from the exception vector table and branches to that
address. For further details, refer to section 4, Exception Handling.

Program Execution State

In this state the CPU executes program instructions in sequence.

Bus-Released State

In a product which has a bus master other than the CPU, such as a direct memory access
controller (DMAC) and a data transfer controller (DTC), the bus-released state occurs when
the bus has been released in response to a bus request from a bus master other than the CPU.
While the bus is released, the CPU halts operations.

Program stop state

This is a power-down state in which the CPU stops operating. The program stop state occurs
when a SLEEP instruction is executed or the CPU enters hardware standby mode. For further
details, refer to section 22, Power-Down Modes.

Rev. 2.0, 04/02, page 55 of 906

Exception

handling state

Bus-released state

Software standby

mode

Reset state

Sleep mode

Power down state

Program execution state

End of bus request

Bus request

= High

= High,

= Low

Reset state

Hardware standby

mode

End of bus request

Bus request

Request for exception handling

Interrupt request

External interrupt request

SSBY = 0

SLEEP

instruction

SSBY = 1

SLEEP instruction

End of exception handling

Notes: 1. From any state except hardware standby mode, a transition to the reset state occurs whenever

goes low.

A transition can also be made to the reset state when the watchdog timer overflows.

2. In every state, when the STBY pin becomes low, the hardware standby mode is entered.
3. For details, refer to section 22, Power-Down Modes.

Figure 2.13 State Transitions

2.9

Usage Note

2.9.1

Usage Notes on Bit-wise Operation Instructions

The BSET, BCLR, BNOT, BST, and BIST instructions are used to read data in byte-wise, operate
the data in bit-wise, and write the result of the bit-wise operation in bit-wise again. Therefore,
special care is necessary to use these instructions for the registers and the ports that include write-
only bit.

The BCLR instruction can be used to clear the flags in the internal I/O registers to 0. In this time,
if it is obvious that the flag has been set to 1 in the interrupt handler, there is no need to read the
flag beforehand.

Rev. 2.0, 04/02, page 57 of 906

Section 3 MCU Operating Modes

3.1

Operating Mode Selection

The H8S/2678 Series has twelve operating modes (modes 1, 2, 4 to 7, and 10 to 15). All operating
modes are available for the flash memory version. Modes 1, 2, and 4 to 7 are available in the
masked ROM version. Modes 1 and 2 are available in the ROMless version.

The H8S/2678R Series has seven operating modes (modes 1 to 7). All operating modes are
available for the flash memory version. Modes 1 and 2 are available in the ROMless version.

These modes are determined by the mode pin (MD2 to MD0) setting.

Modes 1, 2, and 4 to 6 are externally expanded modes in which the CPU can access an external
memory and peripheral devices. In the externally expanded mode, each area can be switched to 8-
bit or 16-bit address space by the bus controller. If one of areas is set to 16-bit address space, the
bus mode is 16 bits. If all areas are set to 8-bit address space, the bus mode is 8 bits.

Mode 7 is a single-chip activation externally expanded mode in which the CPU can switch to
access an external memory and peripheral devices at the beginning of a program execution.

Modes 3, 10, and 11 are boot modes in which the flash memory can be accessed.

Modes 12 to 15 are user program modes in which the flash memory can be accessed.

For details, refer to section 19, Flash Memory.

Do not change the FWE and MD2 to MD0 pin settings during operation.

Rev. 2.0, 04/02, page 58 of 906

Table 3.1

MCU Operating Mode Selection

External Data
Bus

MCU
Operating
Mode

FWE

MD2

MD1

MD0

CPU
Operating
Mode

Description

On-Chip
ROM

Initial
Width

Max.
Value

Advanced

Expanded mode with
on-chip ROM disabled

Disabled

16 bits

Advanced

Expanded mode with
on-chip ROM disabled

Disabled

8 bits

16 bits

Advanced

Boot mode

Enabled

16 bits

Advanced

Expanded mode with
on-chip ROM enabled

Enabled

8 bits

16 bits

Advanced

Expanded mode with
on-chip ROM enabled

Enabled

16 bits

Advanced

Expanded mode with
on-chip ROM enabled

Enabled

8 bits

16 bits

Advanced

Single-chip mode

Enabled

16 bits

Advanced

Boot mode

Enabled

8 bits

16 bits

Advanced

Boot mode

Enabled

16 bits

Advanced

User program mode

Enabled

8 bits

16 bits

Advanced

User program mode

Enabled

16 bits

Advanced

User program mode

Enabled

8 bits

16 bits

Advanced

User program mode

Enabled

16 bits

Notes: 1. Modes 1, 2, 4 to 7, and 10 to 15 are supported in the H8S/2678 Series.

Modes 1 to 7 are supported in the H8S/2678R Series.

2. The FWE pin setting is available only in the H8S/2678 Series. The FWE pin is not

available in the H8S/2678R Series.

Rev. 2.0, 04/02, page 59 of 906

3.2

Register Descriptions

The following registers are related to the operating mode.

Mode control register (MDCR)

System control register (SYSCR)

3.2.1

Mode Control Register (MDCR)

MDCR monitors the current operating mode of the H8S/2678 Series chip.

Bit

Bit Name

Initial Value

R/W

Descriptions

7 to
3

All 0

Reserved
These bits are always read as 0 and cannot be
modified.

2
1
0

MDS2
MDS1
MDS0

R
R
R

Mode Select 2 to 0
These bits indicate the input levels at pins MD2 to MD0
(the current operating mode). Bits MDS2 to MDS0
correspond to MD2 to MD0. MDS2 to MDS0 are read-
only bits and they cannot be written to. The mode pin
(MD2 to MD0) input levels are latched into these bits
when MDCR is read. These latches are canceled by a
reset.

Note: Determined by pins MD2 to MD0.

3.2.2

System Control Register (SYSCR)

SYSCR selects saturating or non-saturating calculation for the MAC instruction, controls CPU
access to the flash memory control registers (FLMCR1, FLMCR2, EBR1, and EBR2), sets
external bus mode, and enables or disables on-chip RAM.

Rev. 2.0, 04/02, page 60 of 906

Bit

Bit Name

Initial Value

R/W

Descriptions

7
6

1
1

R/W
R/W

Reserved
The initial value should not be modified.

MACS

R/W

MAC Saturation
Selects either saturating or non-saturating calculation
for the MAC instruction.
0: Non-saturating calculation for MAC instruction
1: Saturating calculation for MAC instruction

R/W

Reserved
The initial value should not be modified.

FLSHE

R/W

Flash Memory Control Register Enable
Controls CPU access to the flash memory control
registers (FLMCR1, FLMCR2, EBR1, and EBR2). If
this bit is set to 1, the flash memory control registers
can be read/written to. If this bit is cleared to 0, the
flash memory control registers are not selected. At this
time, the contents of the flash memory control registers
are maintained. This bit should be written to 0 other
than flash memory version.

0: Flash memory control registers are not selected for

area H'FFFFC8 to H'FFFFCB

1: Flash memory control registers are selected for area

H'FFFFC8 to H'FFFFCB

Reserved
This bit is always read as 0 and cannot be modified.

EXPE

R/W

External Bus Mode Enable
Sets external bus mode.
In modes 1, 2, and 4 to 6, this bit is fixed at 1 and
cannot be modified. In mode 3

and 7, this bit has an

initial value of 0, and can be read and written.
Writing of 0 to EXPE when its value is 1 should only be
carried out when an external bus cycle is not being
executed.
0: External bus disabled
1: External bus enabled

RAME

R/W

RAM Enable
Enables or disables the on-chip RAM. The RAME bit is
initialized when the reset status is released.
0: On-chip RAM is disabled
1: On-chip RAM is enabled

Note: Mode 3 is available only in the F-ZTAT version of H8S/2678R Series.

Rev. 2.0, 04/02, page 61 of 906

3.3

Operating Mode Descriptions

3.3.1

Mode 1

The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is disabled.
Ports A, B, and C function as an address bus, ports D and E function as a data bus, and parts of
ports F, G, and H carry bus control signals.

The initial bus mode after a reset is 16 bits, with 16-bit access to all areas. However, if 8-bit access
is designated for all areas by the bus controller, the bus mode switches to 8 bits.

3.3.2

Mode 2

The initial bus mode after a reset is 8 bits, with 8-bit access to all areas. However, if 16-bit access
is designated for all areas by the bus controller, the bus mode switches to 16 bits and port E
functions as a data bus.

3.3.3

Mode 3

This mode is a boot mode of the flash memory. This mode is the same as mode 7, except for
accessing to the flash memory. Mode 3 is available only in the flash memory version of the
H8S/2678R Series.

3.3.4

Mode 4

The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled.
The program in the on-chip ROM connected to the first half of area 0 is executed.

Ports A, B, and C function as input ports immediately after a reset, but can be set to function as an
address bus. For details, see section 10, I/O Ports. Ports D and E function as a data bus, and parts
of ports F, G, and H carry bus control signals.

The initial bus mode after a reset is 8 bits, with 8-bit access to all areas. However, if 16-bit access
is designated for any area by the bus controller, the bus mode switches to 16 bits and port E
functions as a data bus. In the flash memory version, user program mode is entered by setting 1 to
the SWE bit of FLMCR1.

Rev. 2.0, 04/02, page 62 of 906

3.3.5

Mode 5

The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled.
The program in an external ROM connected to the first half of area 0 is executed.

Ports A, B, and C function as an address bus, ports D and E function as a data bus, and parts of
ports F, G and H carry bus control signals.

The initial bus mode after a reset is 16 bits, with 16-bit access to all areas. However, if 8-bit access
is designated for any area by the bus controller, the bus mode switches to 8 bits.

In the flash memory version, user program mode is entered by setting 1 to the SWE bit of
FLMCR1.

3.3.6

Mode 6

The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled.
The program in an external ROM connected to the first half of area 0 is executed.

Ports A, B, and C function as an address bus, ports D and E function as a data bus, and parts of
ports F, G, and H carry bus control signals.

In the flash memory version, user program mode is entered by setting 1 to the SWE bit of
FLMCR1.

3.3.7

Mode 7

The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled,
and the chip starts up in single-chip mode. External addresses cannot be used in single-chip mode.

The initial mode after a reset is single-chip mode, with all I/O ports available for use as
input/output ports. However, the mode can be switched to externally expanded mode by setting 1
to the EXPE bit of SYSCR and then the external address space is enabled. When externally
expanded mode is selected, all areas are initially designated as 16-bit access space. The function of
pins in ports A to H is the same as in externally expanded mode with on-chip ROM enabled.

In the flash memory version, user program mode is entered by setting 1 to the SWE bit of
FLMCR1.

Rev. 2.0, 04/02, page 63 of 906

3.3.8

Mode 10

This is flash memory boot mode. This mode is the same as mode 4, except for accessing to the
flash memory. Mode 10 is available only in the flash memory version of the H8S/2678 Series.

3.3.9

Mode 11

This is flash memory boot mode. This mode is the same as mode 7, except for accessing to the
flash memory. Mode 11 is available only in the flash memory version of the H8S/2678 Series.

3.3.10

Mode 12

This is flash memory user program mode. This mode is the same as mode 4, except for accessing
to the flash memory. Mode 12 is available only in the flash memory version of the H8S/2678
Series.

3.3.11

Mode 13

This is flash memory user program mode. This mode is the same as mode 5, except for accessing
to the flash memory. Mode 13 is available only in the flash memory version of the H8S/2678
Series.

3.3.12

Mode 14

This is flash memory user program mode. This mode is the same as mode 6, except for accessing
to the flash memory. Mode 14 is available only in the flash memory version of the H8S/2678
Series.

3.3.13

Mode 15

This is flash memory user program mode. This mode is the same as mode 7, except for accessing
to the flash memory. Mode 15 is available only in the flash memory version of the H8S/2678
Series.

3.3.14

Pin Functions

The pin functions of ports A to H are switched according to operating mode. Table 3.2 shows the
pin functions in each operating mode.

Rev. 2.0, 04/02, page 64 of 906

Table 3.2

Pin Functions in Each Operating Mode

Port

Mode
1

Mode
2

Mode
3

Mode
4

Mode
5

Mode
6

Mode
7

Mode
10

Mode
11

Mode
12

Mode
13

Mode
14

Mode
15

PA7 to
PA5

Port A

PA4 to
PA0

Port B

Port C

Port D

Port E

P/D

PF7,
PF6

P/C

PF5,
PF4

PF3

P/C

Port F

PF2 to
PF0

PG6 to
PG1

Port G

PG0

P/C

Port H

Legend: P: I/O port

A: Address bus output

D: Data bus input/output

C: Control signals, clock input/output

Note: After reset

Rev. 2.0, 04/02, page 66 of 906

H'000000

H'FFA000

H'FFC000

H'000000

H'FFA000

H'FFC000

H'FFFC00

External

address space

On-chip RAM/external

address space

External

address space

External address space

Internal I/O registers

External address space

Internal I/O registers

On-chip ROM

On-chip RAM/external

address space

External address

space/reserved area

External address

space/reserved area

Internal I/O registers

H'FFFFFF

H'FFFC00

H'FFFF00

H'FFFF20

H'FFFFFF

H'FFFF00

H'FFFF20

H'040000

H'100000

H'140000

External address

space/reserved area

On-chip ROM

ROM : 256 kbytes

RAM : 8 kbytes

Modes 5 and 6

(external ROM activation

expanded modes

with on-chip ROM enabled)

ROM : 256 kbytes

RAM : 8 kbytes

Mode 7

(single-chip activation

expanded mode

with on-chip ROM enabled)

Notes: 1. This area is specified as an external address area by clearing the RAME bit of SYSCR to 0.

2. When EXPE = 1, external address space; when EXPE = 0, reserved area.
3. When EXPE = 1, external address space when RAME = 0, on-chip RAM when RAME = 1.

When EXPE = 0, on-chip RAM area.

Figure 3.1 H8S/2676 Memory Map (2)

Rev. 2.0, 04/02, page 68 of 906

H'000000

H'FFA000

H'FFC000

H'000000

H'FFA000

H'FFC000

H'FFFC00

On-chip RAM

External

address space

External address space

Internal I/O registers

External address space

Internal I/O registers

On-chip ROM

On-chip RAM

External address

space/reserved area

External address

space/reserved area

Internal I/O registers

H'FFFFFF

H'FFFC00

H'FFFF00

H'FFFF20

H'FFFFFF

H'FFFF00

H'FFFF20

H'040000

External address

space/reserved area

On-chip ROM

ROM : 256 kbytes

RAM : 8k bytes

Mode 12 User program mode

(expanded mode

with on-chip ROM enabled)

ROM : 256 kbytes

RAM : 8 kbytes

Mode 15 User program mode

(single-chip activation

expanded mode

with on-chip ROM enabled)

Notes: 1. When EXPE = 1, external address space; when EXPE = 0, reserved area.

2. On-chip RAM is used for flash memory programming. Do not clear the RAME bit in SYSCR to 0.

H'000000

H'FFA000

H'FFC000

External

address space

On-chip RAM

External

address space

External address space

Internal I/O registers

External address space

Internal I/O registers

H'FFFFFF

H'FFFC00

H'FFFF00

H'FFFF20

H'100000

H'140000

On-chip ROM

ROM : 256 kbytes

RAM : 8 kbytes

Modes 13 and 14 User program mode

(external ROM activation

expanded modes

with on-chip ROM enabled)

Figure 3.1 H8S/2676 Memory Map (4)

Rev. 2.0, 04/02, page 70 of 906

H'000000

H'FFA000

H'FFC000

H'000000

H'FFA000

H'FFC000

H'FFFC00

External

address space

On-chip RAM/external

address space

External

address space

External address space

Internal I/O registers

External address space

Internal I/O registers

On-chip ROM

On-chip RAM/external

address space

External address

space/reserved area

External address

space/reserved area

Internal I/O registers

H'FFFFFF

H'FFFC00

H'FFFF00

H'FFFF20

H'FFFFFF

H'FFFF00

H'FFFF20

H'020000

H'100000

H'120000

External address

space/reserved area

On-chip ROM

ROM : 128 kbytes

RAM : 8 kbytes

Modes 5 and 6

(external ROM activation

expanded modes

with on-chip ROM enabled)

ROM : 128 kbytes

RAM : 8 kbytes

Mode 7

(single-chip activation

expanded mode

with on-chip ROM enabled)

Notes: 1. This area is specified as an external address area by clearing the RAME bit of SYSCR to 0.

2. When EXPE = 1, external address space; when EXPE = 0, reserved area.
3. When EXPE = 1, external address space when RAME = 0, on-chip RAM when RAME = 1.

When EXPE = 0, on-chip RAM area.

Figure 3.2 H8S/2675 Memory Map (2)

Rev. 2.0, 04/02, page 72 of 906

H'000000

H'FFA000

H'FFC000

H'000000

H'FFA000

H'FFC000

H'FFFC00

External

address space

On-chip RAM/external

address space

External

address space

External address space

Internal I/O registers

External address space

Internal I/O registers

On-chip ROM

On-chip RAM/external

address space

External address

space/reserved area

External address

space/reserved area

Internal I/O registers

H'FFFFFF

H'FFFC00

H'FFFF00

H'FFFF20

H'FFFFFF

H'FFFF00

H'FFFF20

H'010000

H'100000

H'110000

External address

space/reserved area

On-chip ROM

ROM : 64 kbytes

RAM : 8 kbytes

Modes 5 and 6

(external ROM activation

expanded modes

with on-chip ROM enabled)

ROM : 64 kbytes

RAM : 8 kbytes

Mode 7

(single-chip activation

expanded mode

with on-chip ROM enabled)

Notes: 1. This area is specified as an external address area by clearing the RAME bit of SYSCR to 0.

2. When EXPE = 1, external address space; when EXPE = 0, reserved area.
3. When EXPE = 1, external address space when RAME = 0, on-chip RAM when RAME = 1.

When EXPE = 0, on-chip RAM area.

Figure 3.3 H8S/2673 Memory Map (2)

Rev. 2.0, 04/02, page 75 of 906

Section 4 Exception Handling

4.1

Exception Handling Types and Priority

As table 4.1 indicates, exception handling may be caused by a reset, trace, interrupt, or trap
instruction. Exception handling is prioritized as shown in table 4.1. If two or more exceptions
occur simultaneously, they are accepted and processed in order of priority. Exception sources, the
stack structure, and operation of the CPU vary depending on the interrupt control mode. For
details on the interrupt control mode, refer to section 5, Interrupt Controller.

Table 4.1

Exception Types and Priority

Priority

Exception Type

Start of Exception Handling

High

Reset

Starts immediately after a low-to-high transition at the

pin, or when the watchdog timer overflows. The CPU enters
the reset state when the

pin is low.

Trace

Starts when execution of the current instruction or exception
handling ends, if the trace (T) bit in the EXR is set to 1.

Direct transition

Starts when the direct transition occurs by execution of the
SLEEP instruction.

Interrupt

Starts when execution of the current instruction or exception
handling ends, if an interrupt request has been issued.

Low

Trap instruction

Started by execution of a trap instruction (TRAPA)

Notes: 1. Traces are enabled only in interrupt control mode 2. Trace exception handling is not

executed after execution of an RTE instruction.

2. Not available in this LSI.

3. Interrupt detection is not performed on completion of ANDC, ORC, XORC, or LDC

instruction execution, or on completion of reset exception handling.

4. Trap instruction exception handling requests are accepted at all times in program

execution state.

4.2

Exception Sources and Exception Vector Table

Different vector addresses are assigned to different exception sources. Table 4.2 lists the exception
sources and their vector addresses. Since the usable modes differ depending on the product, for
details on each product, refer to section 3, MCU Operating Modes.

Rev. 2.0, 04/02, page 76 of 906

Table 4.2

Exception Handling Vector Table

Vector Address

Exception Source

Vector Number

Normal Mode

Advanced Mode

Power-on reset

H'0000 to H'0001

H'0000 to H'0003

Manual reset

H'0002 to H'0003

H'0004 to H'0007

Reserved for system use

H'0004 to H'0005

H'0008 to H'000B

H'0006 to H'0007

H'000C to H'000F

H'0008 to H'0019

H'0010 to H'0013

Trace

H'000A to H'000B

H'0014 to H'0017

Interrupt (direct transition)

H'000C to H'000D

H'0018 to H'001B

Interrupt (NMI)

H'000E to H'000F

H'001C to H'001F

Trap instruction (#0)

H'0010 to H'0011

H'0020 to H'0023

(#1)

H'0012 to H'0013

H'0024 to H'0027

(#2)

H'0014 to H'0015

H'0028 to H'002B

(#3)

H'0016 to H'0017

H'002C to H'002F

Reserved for system use

H'0018 to H'0019

H'0030 to H'0033

H'001A to H'001B

H'0034 to H'0037

H'001C to H'001D

H'0038 to H'003B

H'001E to H'001F

H'003C to H'003F

External interrupt

IRQ0

H'0020 to H'0021

H'0040 to H'0043

IRQ1

H'0022 to H'0023

H'0044 to H'0047

IRQ2

H'0024 to H'0025

H'0048 to H'004B

IRQ3

H'0026 to H'0027

H'004C to H'004F

IRQ4

H'0028 to H'0029

H'0050 to H'0053

IRQ5

H'002A to H'002B

H'0054 to H'0057

IRQ6

H'002C to H'002D

H'0058 to H'005B

IRQ7

H'002E to H'002F

H'005C to H'005F

IRQ8

H'0030 to H'0031

H'0060 to H'0063

IRQ9

H'0032 to H'0033

H'0064 to H'0067

IRQ10

H'0034 to H'0035

H'0068 to H'006B

IRQ11

H'0036 to H'0037

H'006C to H'006F

IRQ12

H'0038 to H'0039

H'0070 to H'0073

IRQ13

H'003A to H'003B

H'0074 to H'0077

IRQ14

H'003C to H'003D

H'0078 to H'007B

IRQ15

H'003E to H'003F

H'007C to H'007F

Rev. 2.0, 04/02, page 77 of 906

Vector Address

Exception Source

Vector Number

Normal Mode

Advanced Mode

Internal interrupt

H'0040 to H'0041

H'00C6 to H'00C7

H'0080 to H'0083

H'018C to H'018F

Notes: 1. Lower 16 bits of the address.

2. Not available in this LSI.

3. For details of internal interrupt vectors, see section 5.5, Interrupt Exception Handling

Vector Table.

4.3

Reset

A reset has the highest exception priority. When the

#$ pin goes low, all processing halts and

this LSI enters the reset. To ensure that this LSI is reset, hold the

#$ pin low for at least 20 ms at

power-up. To reset the chip during operation, hold the

#$ pin low for at least 20 states. A reset

initializes the internal state of the CPU and the registers of on-chip peripheral modules.

The chip can also be reset by overflow of the watchdog timer. For details see section 14,
Watchdog Timer.

The interrupt control mode is 0 immediately after reset.

4.3.1

Reset exception handling

When the

#$ pin goes high after being held low for the necessary time, this LSI starts reset

exception handling as follows:

1. The internal state of the CPU and the registers of the on-chip peripheral modules are

initialized, the T bit is cleared to 0 in EXR, and the I bit is set to 1 in EXR and CCR.

2. The reset exception handling vector address is read and transferred to the PC, and program

execution starts from the address indicated by the PC.

Figures 4.1 and 4.2 show examples of the reset sequence.

Rev. 2.0, 04/02, page 79 of 906

D15 to D0

High

Address bus

Vector fetch

Internal
processing

Prefetch of first
program instruction

(1)

(2)

(4)

(6)

(3)

(5)

(1)(3) Reset exception handling vector address (when reset, (1)=H'000000, (3)=H'000002)
(2)(4) Start address (contents of reset exception handling vector address)
(5) Start address ((5)=(2)(4))
(6) First program instruction

Note:

Seven program wait states are inserted.

Figure 4.2 Reset Sequence (Advanced Mode with On-chip ROM Disabled)

4.3.2

Interrupts after Reset

If an interrupt is accepted after a reset but before the stack pointer (SP) is initialized, the PC and
CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests,
including NMI, are disabled immediately after a reset. Since the first instruction of a program is
always executed immediately after the reset state ends, make sure that this instruction initializes
the stack pointer (example: MOV.L #xx: 32, SP).

4.3.3

On-Chip Peripheral Functions after Reset Release

After reset release, MSTPCR is initialized to H'0FFF and all modules except the DMAC,
EXDMAC and the DTC enter module stop mode.

Consequently, on-chip peripheral module registers cannot be read or written to. Register reading
and writing is enabled when module stop mode is exited.

Rev. 2.0, 04/02, page 80 of 906

4.4

Traces

Traces are enabled in interrupt control mode 2. Trace mode is not activated in interrupt control
mode 0, irrespective of the state of the T bit. For details on interrupt control modes, see section 5,
Interrupt Controller.

If the T bit in EXR is set to 1, trace mode is activated. In trace mode, a trace exception occurs on
completion of each instruction. Trace mode is not affected by interrupt masking. Table 4.3 shows
the state of CCR and EXR after execution of trace exception handling. Trace mode is canceled by
clearing the T bit in EXR to 0. The T bit saved on the stack retains its value of 1, and when control
is returned from the trace exception handling routine by the RTE instruction, trace mode resumes.
Trace exception handling is not carried out after execution of the RTE instruction.

Interrupts are accepted even within the trace exception handling routine.

Table 4.3

Status of CCR and EXR after Trace Exception Handling

CCR

EXR

Interrupt Control Mode

I2 to I0

Trace exception handling cannot be used.

Legend:

Set to 1

0: Cleared to 0

--: Retains value prior to execution.

4.5

Interrupts

Interrupts are controlled by the interrupt controller. The interrupt controller has two interrupt
control modes and can assign interrupts other than NMI to eight priority/mask levels to enable
multiplexed interrupt control. The source to start interrupt exception handling and the vector
address differ depending on the product. For details, refer to section 5, Interrupt Controller.

The interrupt exception handling is as follows:

1. The values in the program counter (PC), condition code register (CCR), and extended register

(EXR) are saved in the stack.

2. The interrupt mask bit is updated and the T bit is cleared to 0.

3. A vector address corresponding to the interrupt source is generated, the start address is loaded

from the vector table to the PC, and program execution starts from that address.

Rev. 2.0, 04/02, page 81 of 906

4.6

Trap Instruction

Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction
exception handling can be executed at all times in the program execution state.

The trap instruction exception handling is as follows:

1. The values in the program counter (PC), condition code register (CCR), and extended register

(EXR) are saved in the stack.

2. The interrupt mask bit is updated and the T bit is cleared to 0.

3. A vector address corresponding to the interrupt source is generated, the start address is loaded

from the vector table to the PC, and program execution starts from that address.

The TRAPA instruction fetches a start address from a vector table entry corresponding to a vector
number from 0 to 3, as specified in the instruction code.

Table 4.4 shows the status of CCR and EXR after execution of trap instruction exception handling.

Table 4.4

Status of CCR and EXR after Trap Instruction Exception Handling

CCR

EXR

Interrupt Control Mode

I2 to I0

Legend:

Set to 1

Cleared to 0

--: Retains value prior to execution.

Rev. 2.0, 04/02, page 83 of 906

4.8

Usage Note

When accessing word data or longword data, this LSI assumes that the lowest address bit is 0. The
stack should always be accessed by word transfer instruction or longword transfer instruction, and
the value of the stack pointer (SP, ER7) should always be kept even. Use the following
instructions to save registers:

PUSH.W Rn (or MOV.W Rn, @-SP)

PUSH.L ERn (or MOV.L ERn, @-SP)

Use the following instructions to restore registers:

POP.W Rn (or MOV.W @SP+, Rn)

POP.L ERn (or MOV.L @SP+, ERn)

Setting SP to an odd value may lead to a malfunction. Figure 4.4 shows an example of operation
when the SP value is odd.

CCR :

PC :

R1L :

SP :

Condition code register

Program counter

General register R1L

Stack pointer

CCR

R1L

H'FFFEFA

H'FFFEFB

H'FFFEFC

H'FFFEFD

H'FFFEFE

H'FFFEFF

TRAP instruction executed

SP set to H'FFFEFF

Data saved above SP

MOV.B R1L, @-ER7

Contents of CCR lost

Address

Legend

Note: This diagram illustrates an example in which the interrupt control mode is 0, in advanced mode.

Figure 4.4 Operation when SP Value Is Odd

Rev. 2.0, 04/02, page 85 of 906

Section 5 Interrupt Controller

5.1

Features

Two interrupt control modes

Any of two interrupt control modes can be set by means of the INTM1 and INTM0 bits in the
interrupt control register (INTCR).

Priorities settable with IPR

An interrupt priority register (IPR) is provided for setting interrupt priorities. Eight priority
levels can be set for each module for all interrupts except NMI. NMI is assigned the highest
priority level of 8, and can be accepted at all times.

Independent vector addresses

All interrupt sources are assigned independent vector addresses, making it unnecessary for the
source to be identified in the interrupt handling routine.

Seventeen external interrupts

NMI is the highest-priority interrupt, and is accepted at all times. Rising edge or falling edge
can be selected for NMI. Falling edge, rising edge, or both edge detection, or level sensing, can
be selected for

,54 to ,54.

DTC and DMAC control

DTC and DMAC activations are performed by means of interrupts.

Rev. 2.0, 04/02, page 87 of 906

Table 5.1

Pin Configuration

Name

I/O

Function

NMI

Input

Nonmaskable external interrupt

Rising or falling edge can be selected.

,54

Input

Maskable external interrupts

Rising, falling, or both edges, or level sensing, can be
selected.

5.3

Register Descriptions

The interrupt controller has the following registers.

Interrupt control register (INTCR)

IRQ sense control register H (ISCRH)

IRQ sense control register L (ISCRL)

IRQ enable register (IER)

IRQ status register (ISR)

IRQ pin select register (ITSR)

Software standby release IRQ enable register (SSIER)

Interrupt priority register A (IPRA)

Interrupt priority register B (IPRB)

Interrupt priority register C (IPRC)

Interrupt priority register D (IPRD)

Interrupt priority register E (IPRE)

Interrupt priority register F (IPRF)

Interrupt priority register G (IPRG)

Interrupt priority register H (IPRH)

Interrupt priority register I (IPRI)

Interrupt priority register J (IPRJ)

Interrupt priority register K (IPRK)

5.3.1

Interrupt Control Register (INTCR)

INTCR selects the interrupt control mode, and the detected edge for NMI.

Rev. 2.0, 04/02, page 88 of 906

Bit

Bit Name

Initial Value

R/W

Description

7
6

0
0

R/W
R/W

Reserved

These bits can be read from or written to.
However, the write value should always be 0.

5
4

INTM1
INTM0

0
0

R/W
R/W

Interrupt Control Select Mode 1 and 0

These bits select either of two interrupt control
modes for the interrupt controller.

00: Interrupt control mode 0

Interrupts are controlled by I bit.

01: Setting prohibited.

10: Interrupt control mode 2

Interrupts are controlled by bits I2 to I0, and
IPR.

11: Setting prohibited.

NMIEG

R/W

NMI Edge Select

Selects the input edge for the NMI pin.

0: Interrupt request generated at falling edge of
NMI input

1: Interrupt request generated at rising edge of
NMI input

2 to 0

All 0

R/W

Reserved

These bits can be read from or written to.
However, the write value should always be 0.

5.3.2

Interrupt Priority Registers A to K (IPRA to IPRK)

IPR are eleven 16-bit readable/writable registers that set priorities (levels 7 to 0) for interrupts
other than NMI.

The correspondence between interrupt sources and IPR settings is shown in table 5.2 (Interrupt
Sources, Vector Addresses, and Interrupt Priorities). Setting a value in the range from H'0 to H'7
in the 3-bit groups of bits 14 to 12, 10 to 8, 6 to 4, and 2 to 0 sets the priority of the corresponding
interrupt. IPR should be read in word size.

Rev. 2.0, 04/02, page 89 of 906

Bit

Bit Name

Initial Value

R/W

Description

Reserved

This bit is always read as 0 and cannot be
modified.

14
13
12

IPR14
IPR13
IPR12

1
1
1

R/W
R/W
R/W

Sets the priority of the corresponding interrupt
source.

000: Priority level 0 (Lowest)

001: Priority level 1

010: Priority level 2

011: Priority level 3

100: Priority level 4

101: Priority level 5

110: Priority level 6

111: Priority level 7 (Highest)

Reserved

This bit is always read as 0 and cannot be
modified.

10
9
8

IPR10
IPR9
IPR8

1
1
1

R/W
R/W
R/W

Sets the priority of the corresponding interrupt
source.

000: Priority level 0 (Lowest)

001: Priority level 1

010: Priority level 2

011: Priority level 3

100: Priority level 4

101: Priority level 5

110: Priority level 6

111: Priority level 7 (Highest)

Reserved

This bit is always read as 0 and cannot be
modified.

6
5
4

IPR6
IPR5
IPR4

1
1
1

R/W
R/W
R/W

Sets the priority of the corresponding interrupt
source.

000: Priority level 0 (Lowest)

001: Priority level 1

010: Priority level 2

011: Priority level 3

100: Priority level 4

101: Priority level 5

110: Priority level 6

111: Priority level 7 (Highest)

Rev. 2.0, 04/02, page 90 of 906

Bit

Bit Name

Initial Value

R/W

Description

Reserved

This bit is always read as 0 and cannot be
modified.

2
1
0

IPR2
IPR1
IPR0

1
1
1

R/W
R/W
R/W

Sets the priority of the corresponding interrupt
source.

000: Priority level 0 (Lowest)

001: Priority level 1

010: Priority level 2

011: Priority level 3

100: Priority level 4

101: Priority level 5

110: Priority level 6

111: Priority level 7 (Highest)

5.3.3

IRQ Enable Register (IER)

IER controls enabling and disabling of interrupt requests IRQ15 to IRQ0.

Bit

Bit Name

Initial Value

R/W

Description

IRQ15E

R/W

IRQ15 Enable

The IRQ15 interrupt request is enabled when
this bit is 1.

IRQ14E

R/W

IRQ14 Enable

The IRQ14 interrupt request is enabled when
this bit is 1.

IRQ13E

R/W

IRQ13 Enable

The IRQ13 interrupt request is enabled when
this bit is 1.

IRQ12E

R/W

IRQ12 Enable

The IRQ12 interrupt request is enabled when
this bit is 1.

IRQ11E

R/W

IRQ11 Enable

The IRQ11 interrupt request is enabled when
this bit is 1.

IRQ10E

R/W

IRQ10 Enable

The IRQ10 interrupt request is enabled when
this bit is 1.

Rev. 2.0, 04/02, page 92 of 906

5.3.4

IRQ Sense Control Registers H and L (ISCRH, ISCRL)

ISCR select the source that generates an interrupt request at pins

,54 to ,54.

ISCRH

Bit

Bit Name

Initial Value

R/W

Description

15
14

IRQ15SCB
IRQ15SCA

0
0

R/W
R/W

IRQ15 Sense Control B
IRQ15 Sense Control A

00: Interrupt request generated at

,54

input

low level

01: Interrupt request generated at falling edge

,54

input

10: Interrupt request generated at rising edge of

,54

input

11: Interrupt request generated at both falling

and rising edges of

,54

input

13
12

IRQ14SCB
IRQ14SCA

0
0

R/W
R/W

IRQ14 Sense Control B
IRQ14 Sense Control A

00: Interrupt request generated at

,54

input

low level

01: Interrupt request generated at falling edge

,54

input

10: Interrupt request generated at rising edge of

,54

input

11: Interrupt request generated at both falling

and rising edges of

,54

input

11
10

IRQ13SCB
IRQ13SCA

0
0

R/W
R/W

IRQ13 Sense Control B
IRQ13 Sense Control A

00: Interrupt request generated at

,54

input

low level

01: Interrupt request generated at falling edge

,54

input

10: Interrupt request generated at rising edge of

,54

input

11: Interrupt request generated at both falling

and rising edges of

,54

input

Rev. 2.0, 04/02, page 93 of 906

Bit

Bit Name

Initial Value

R/W

Description

9
8

IRQ12SCB
IRQ12SCA

0
0

R/W
R/W

IRQ12 Sense Control B
IRQ12 Sense Control A

00: Interrupt request generated at

,54

input

low level

01: Interrupt request generated at falling edge

,54

input

10: Interrupt request generated at rising edge of

,54

input

11: Interrupt request generated at both falling

and rising edges of

,54

input

7
6

IRQ11SCB
IRQ11SCA

0
0

R/W
R/W

IRQ11 Sense Control B
IRQ11 Sense Control A

00: Interrupt request generated at

,54

input

low level

01: Interrupt request generated at falling edge

,54

input

10: Interrupt request generated at rising edge of

,54

input

11: Interrupt request generated at both falling

and rising edges of

,54

input

5
4

IRQ10SCB
IRQ10SCA

0
0

R/W
R/W

IRQ10 Sense Control B
IRQ10 Sense Control A

00: Interrupt request generated at

,54

input

low level

01: Interrupt request generated at falling edge

,54

input

10: Interrupt request generated at rising edge of

,54

input

11: Interrupt request generated at both falling

and rising edges of

,54

input

3
2

IRQ9SCB
IRQ9SCA

0
0

R/W
R/W

IRQ9 Sense Control B
IRQ9 Sense Control A

00: Interrupt request generated at

,54

input

low level

01: Interrupt request generated at falling edge

,54

input

10: Interrupt request generated at rising edge of

,54

input

11: Interrupt request generated at both falling

and rising edges of

,54

input

Rev. 2.0, 04/02, page 94 of 906

Bit

Bit Name

Initial Value

R/W

Description

1
0

IRQ8SCB
IRQ8SCA

0
0

R/W
R/W

IRQ8 Sense Control B
IRQ8 Sense Control A

00: Interrupt request generated at

,54

input

low level

01: Interrupt request generated at falling edge

,54

input

10: Interrupt request generated at rising edge of

,54

input

11: Interrupt request generated at both falling

and rising edges of

,54

input

ISCRL

Bit

Bit Name

Initial Value

R/W

Description

15
14

IRQ7SCB
IRQ7SCA

0
0

R/W
R/W

IRQ7 Sense Control B
IRQ7 Sense Control A

00: Interrupt request generated at

,54

input

low level

01: Interrupt request generated at falling edge

,54

input

10: Interrupt request generated at rising edge of

,54

input

11: Interrupt request generated at both falling

and rising edges of

,54

input

13
12

IRQ6SCB
IRQ6SCA

0
0

R/W
R/W

IRQ6 Sense Control B
IRQ6 Sense Control A

00: Interrupt request generated at

,54

input

low level

01: Interrupt request generated at falling edge

,54

input

10: Interrupt request generated at rising edge of

,54

input

11: Interrupt request generated at both falling

and rising edges of

,54

input

Rev. 2.0, 04/02, page 95 of 906

Bit

Bit Name

Initial Value

R/W

Description

11
10

IRQ5SCB
IRQ5SCA

0
0

R/W
R/W

IRQ5 Sense Control B
IRQ5 Sense Control A

00: Interrupt request generated at

,54

input

low level

01: Interrupt request generated at falling edge

,54

input

10: Interrupt request generated at rising edge of

,54

input

11: Interrupt request generated at both falling

and rising edges of

,54

input

9
8

IRQ4SCB
IRQ4SCA

0
0

R/W
R/W

IRQ4 Sense Control B
IRQ4 Sense Control A

00: Interrupt request generated at

,54

input

low level

01: Interrupt request generated at falling edge

,54

input

10: Interrupt request generated at rising edge of

,54

input

11: Interrupt request generated at both falling

and rising edges of

,54

input

7
6

IRQ3SCB
IRQ3SCA

0
0

R/W
R/W

IRQ3 Sense Control B
IRQ3 Sense Control A

00: Interrupt request generated at

,54

input

low level

01: Interrupt request generated at falling edge

,54

input

10: Interrupt request generated at rising edge of

,54

input

11: Interrupt request generated at both falling

and rising edges of

,54

input

5
4

IRQ2SCB
IRQ2SCA

0
0

R/W
R/W

IRQ2 Sense Control B
IRQ2 Sense Control A

00: Interrupt request generated at

,54

input

low level

01: Interrupt request generated at falling edge

,54

input

10: Interrupt request generated at rising edge of

,54

input

11: Interrupt request generated at both falling

and rising edges of

,54

input

Rev. 2.0, 04/02, page 97 of 906

5.3.5

IRQ Status Register (ISR)

ISR is an IRQ15 to IRQ0 interrupt request flag register.

Bit

Bit Name

Initial Value

R/W

Description

15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0

IRQ15F
IRQ14F
IRQ13F
IRQ12F
IRQ11F
IRQ10F
IRQ9F
IRQ8F
IRQ7F
IRQ6F
IRQ5F
IRQ4F
IRQ3F
IRQ2F
IRQ1F
IRQ0F

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

R/(W)

[Setting conditions]

When the interrupt source selected by ISCR
occurs

[Clearing conditions]

Cleared by reading IRQnF flag when IRQnF

= 1, then writing 0 to IRQnF flag

When interrupt exception handling is

executed when low-level detection is set

and

,54Q

input is high

When IRQn interrupt exception handling is

executed when falling, rising, or both-edge

detection is set

When the DTC is activated by an IRQn

interrupt, and the DISEL bit in MRB of the

DTC is cleared to 0

(n=15 to 0)

Note: Only 0 can be written, to clear the flag.

Rev. 2.0, 04/02, page 100 of 906

5.3.7

Software Standby Release IRQ Enable Register (SSIER)

SSIER selects the

,54 pins used to recover from the software standby state.

Bit

Bit Name

Initial Value

R/W

Description

15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0

SSI15
SSI14
SSI13
SSI12
SSI11
SSI10
SSI9
SSI8
SSI7
SSI6
SSI5
SSI4
SSI3
SSI2
SSI1
SSI0

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W

Software Standby Release IRQ Setting

These bits select the

,54Q

pins used to recover

from the software standby state.

0: IRQn requests are not sampled in the
software standby state (Initial value when n =
15 to 3)

1: When an IRQn request occurs in the software
standby state, the chip recovers from the
software standby state after the elapse of the
oscillation settling time (Initial value when n = 2
to 0)

(n = 15 to 0)

5.4

Interrupt Sources

5.4.1

External Interrupts

There are seventeen external interrupts: NMI and IRQ15 to IRQ0. These interrupts can be used to
restore the chip from software standby mode.

NMI Interrupt: Nonmaskable interrupt request (NMI) is the highest-priority interrupt, and is
always accepted by the CPU regardless of the interrupt control mode or the status of the CPU
interrupt mask bits. The NMIEG bit in INTCR can be used to select whether an interrupt is
requested at a rising edge or a falling edge on the NMI pin.

IRQ15 to IRQ0 Interrupts: Interrupts IRQ15 to IRQ0 are requested by an input signal at pins
,54 to ,54. Interrupts IRQ15 to IRQ0 have the following features:

Using ISCR, it is possible to select whether an interrupt is generated by a low level, falling
edge, rising edge, or both edges, at pins

,54 to ,54.

Enabling or disabling of interrupt requests IRQ15 to IRQ0 can be selected with IER.

The interrupt priority level can be set with IPR.

The status of interrupt requests IRQ15 to IRQ0 is indicated in ISR. ISR flags can be cleared to
0 by software.

Rev. 2.0, 04/02, page 101 of 906

When IRQ15 to IRQ0 interrupt requests occur at low level of

,54Q, the corresponding ,54 should

be held low until an interrupt handling starts. Then the corresponding

,54 should be set to high in

the interrupt handling routine and clear the IRQnF bit (n = 0 to 15) in ISR to 0. Interrupts may not
be executed when the corresponding

,54 is set to high before the interrupt handling starts.

Detection of IRQ15 to IRQ0 interrupts does not depend on whether the relevant pin has been set
for input or output. However, when a pin is used as an external interrupt input pin, do not clear the
corresponding DDR to 0 and use the pin as an I/O pin for another function.

A block diagram of interrupts IRQ15 to IRQ0 is shown in figure 5.2.

IRQn interrupt
request

IRQnE

IRQnF

Clear signal

Edge/

level detection

circuit

IRQnSCA, IRQnSCB

input

Note: n = 15 to 0

Figure 5.2 Block Diagram of Interrupts IRQ15 to IRQ0

5.4.2

Internal Interrupts

The sources for internal interrupts from on-chip peripheral modules have the following features:

For each on-chip peripheral module there are flags that indicate the interrupt request status,
and enable bits that select enabling or disabling of these interrupts. They can be controlled
independently. When the enable bit is set to 1, an interrupt request is issued to the interrupt
controller.

The interrupt priority level can be set by means of IPR.

The DMAC and DTC can be activated by a TPU, SCI, or other interrupt request.

When the DMAC or DTC is activated by an interrupt request, it is not affected by the interrupt
control mode or CPU interrupt mask bit.

Rev. 2.0, 04/02, page 103 of 906

Table 5.2

Interrupt Sources, Vector Addresses, and Interrupt Priorities

Vector
Address

Interrupt
Source

Origin of
Interrupt

Source

Vector
Number

Advanced
Mode

IPR

Priority

DTC
Activation

DMAC
Activation

External

NMI

H'001C

High

IRQ0

H'0040

IPRA14 to IPRA12

IRQ1

H'0044

IPRA10 to IPRA8

IRQ2

H'0048

IPRA6 to IPRA4

IRQ3

H'004C

IPRA2 to IPRA0

IRQ4

H'0050

IPRB14 to IPRB12

IRQ5

H'0054

IPRB10 to IPRB8

IRQ6

H'0058

IPRB6 to IPRB4

IRQ7

H'005C

IPRB2 to IPRB0

IRQ8

H'0060

IPRC14 to IPRC12

IRQ9

H'0064

IPRC10 to IPRC8

IRQ10

H'0068

IPRC6 to IPRC4

IRQ11

H'006C

IPRC2 to IPRC0

IRQ12

H'0070

IPRD14 to IPRD12

IRQ13

H'0074

IPRD10 to IPRD8

IRQ14

H'0078

IPRD6 to IPRD4

IRQ15

H'007C

IPRD2 to IPRD0

DTC

SWDTEND

H'0080

IPRE14 to IPRE12

WDT

WOVI

H'0084

IPRE10 to IPRE8

Reserved for
system use

H'0088

IPRE6 to IPRE4

Refresh
controller

CMI

H'008C

IPRE2 to IPRE0

H'0090

Reserved for

system use

H'0094

IPRF14 to IPRF12

A/D

ADI

H'0098

IPRF10 to IPRF8

Reserved for
system use

H'009C

TPU_0

TGI0A

H'00A0

IPRF6 to IPRF4

TGI0B

H'00A4

TGI0C

H'00A8

Low

Rev. 2.0, 04/02, page 104 of 906

Vector
Address

Interrupt
Source

Origin of

Interrupt
Source

Vector
Number

Advanced

Mode

IPR

Priority

DTC
Activation

DMAC
Activation

TPU_0

TGI0D

H'00AC

High

TCI0V

H'00B0

H'00B4

H'00B8

Reserved for
system use

H'00BC

IPRF6 to IPRF4

TPU_1

TGI1A

H'00C0

IPRF2 to IPRF0

TGI1B

H'00C4

TCI1V

H'00C8

TCI1U

H'00CC

TPU_2

TGI2A

H'00D0

IPRG14 to IPRG12

TGI2B

H'00D4

TCI2V

H'00D8

TCI2U

H'00DC

TPU_3

TGI3A

H'00E0

IPRG10 to IPRG8

TGI3B

H'00E4

TGI3C

H'00E8

TGI3D

H'00EC

TCI3V

H'00F0

H'00F4

H'00F8

Reserved for

system use

H'00FC

TPU_4

TGI4A

H'0100

IPRG6 to IPRG4

TGI4B

H'0104

TCI4V

H'0108

TCI4U

H'010C

TPU_5

TGI5A

H'0110

IPRG2 to IPRG0

TGI5B

H'0114

TCI5V

H'0118

TCI5U

H'011C

TMR_0

CMIA0

H'0120

IPRH14 to IPRH12

CMIB0

H'0124

OVI0

H'0128

Low

Rev. 2.0, 04/02, page 105 of 906

Vector
Address

Interrupt
Source

Origin of

Interrupt
Source

Vector
Number

Advanced

Mode

IPR

Priority

DTC
Activation

DMAC
Activation

Reserved for
system use

H'012C

High

TMR_1

CMIA1

H'0130

IPRH10 to IPRH8

CMIB1

H'0134

OVI1

H'0138

Reserved for
system use

H'013C

DMAC

DMTEND0A

H'0140

IPRH6 to IPRH4

DMTEND0B

H'0144

DMTEND1A

H'0148

DMTEND1B

H'014C

EXDMAC

EXDMTEND0

H'0150

IPRH0 to IPRH0

EXDMTEND1

H'0154

IPRI14 to IPRI12

EXDMTEND2

H'0158

IPRI10 to IPRI8

EXDMTEND3

H'015C

IPRI6 to IPRI4

SCI_0

ERI0

H'0160

IPRI2 to IPRI0

RXI0

H'0164

TXI0

H'0168

TEI0

H'016C

SCI_1

ERI1

H'0170

IPRJ14 to IPRJ12

RXI1

H'0174

TXI1

H'0178

TEI1

H'017C

SCI_2

ERI2

H'0180

IPRJ10 to IPRJ8

RXI2

H'0184

TXI2

H'0188

TEI2

H'018C

Reserved for
system use

100

H'0190

IPRJ6 to IPRJ4

101

H'0194

102

H'0198

103

H'019C

Low

Rev. 2.0, 04/02, page 107 of 906

5.6

Interrupt Control Modes and Interrupt Operation

The interrupt controller has two modes: interrupt control mode 0 and interrupt control mode 2.
Interrupt operations differ depending on the interrupt control mode. The interrupt control mode is
selected by INTCR. Table 5.3 shows the differences between interrupt control mode 0 and
interrupt control mode 2.

Table 5.3

Interrupt Control Modes

Interrupt

Priority Setting

Interrupt

Control Mode Registers

Mask Bits Description

Default

The priorities of interrupt sources are fixed at
the default settings.
Interrupt sources except for NMI is masked by
the I bit.

IPR

I2 to I0

8 priority levels except for NMI can be set with
IPR.
8-level interrupt mask control is performed by
bits I2 to I0.

5.6.1

Interrupt Control Mode 0

In interrupt control mode 0, interrupt requests except for NMI is masked by the I bit of CCR in the
CPU. Figure 5.3 shows a flowchart of the interrupt acceptance operation in this case.

1. If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an

interrupt request is sent to the interrupt controller.

2. If the I bit is set to 1, only an NMI interrupt is accepted, and other interrupt requests are held

pending. If the I bit is cleared, an interrupt request is accepted.

3. Interrupt requests are sent to the interrupt controller, the highest-ranked interrupt according to

the priority system is accepted, and other interrupt requests are held pending.

4. When the CPU accepts an interrupt request, it starts interrupt exception handling after

execution of the current instruction has been completed.

5. The PC and CCR are saved to the stack area by interrupt exception handling. The PC saved on

the stack shows the address of the first instruction to be executed after returning from the
interrupt handling routine.

6. Next, the I bit in CCR is set to 1. This masks all interrupts except NMI.

7. The CPU generates a vector address for the accepted interrupt and starts execution of the

interrupt handling routine at the address indicated by the contents of the vector address in the
vector table.

Rev. 2.0, 04/02, page 109 of 906

5.6.2

Interrupt Control Mode 2

In interrupt control mode 2, mask control is done in eight levels for interrupt requests except for
NMI by comparing the EXR interrupt mask level (I2 to I0 bits) in the CPU and the IPR setting.
Figure 5.4 shows a flowchart of the interrupt acceptance operation in this case.

1. If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an

interrupt request is sent to the interrupt controller.

2. When interrupt requests are sent to the interrupt controller, the interrupt with the highest

priority according to the interrupt priority levels set in IPR is selected, and lower-priority
interrupt requests are held pending. If a number of interrupt requests with the same priority are
generated at the same time, the interrupt request with the highest priority according to the
priority system shown in table 5.2 is selected.

3. Next, the priority of the selected interrupt request is compared with the interrupt mask level set

in EXR. An interrupt request with a priority no higher than the mask level set at that time is
held pending, and only an interrupt request with a priority higher than the interrupt mask level
is accepted.

4. When the CPU accepts an interrupt request, it starts interrupt exception handling after

execution of the current instruction has been completed.

5. The PC, CCR, and EXR are saved to the stack area by interrupt exception handling. The PC

saved on the stack shows the address of the first instruction to be executed after returning from
the interrupt handling routine.

6. The T bit in EXR is cleared to 0. The interrupt mask level is rewritten with the priority level of

the accepted interrupt.

If the accepted interrupt is NMI, the interrupt mask level is set to H'7.

7. The CPU generates a vector address for the accepted interrupt and starts execution of the

interrupt handling routine at the address indicated by the contents of the vector address in the
vector table.

Rev. 2.0, 04/02, page 112 of 906

5.6.4

Interrupt Response Times

Table 5.4 shows interrupt response times - the interval between generation of an interrupt request
and execution of the first instruction in the interrupt handling routine. The execution status
symbols used in table 5.4 are explained in table 5.5.

This LSI is capable of fast word transfer to on-chip memory, and have the program area in on-chip
ROM and the stack area in on-chip RAM, enabling high-speed processing.

Table 5.4

Interrupt Response Times

Normal Mode

Advanced Mode

No.

Execution Status

Interrupt
control
mode 0

Interrupt
control
mode 2

Interrupt
control
mode 0

Interrupt
control
mode 2

Interrupt priority determination

Number of wait states until executing
instruction ends

1 to 19 +2·S

1 to 19+2·S

PC, CCR, EXR stack save

2·S

3·S

2·S

3·S

Vector fetch

2·S

Instruction fetch

2·S

Internal processing

Total (using on-chip memory)

11 to 31

12 to 32

13 to 33

Notes: 1. Two states in case of internal interrupt.

2. Refers to MULXS and DIVXS instructions.

3. Prefetch after interrupt acceptance and interrupt handling routine prefetch.

4. Internal processing after interrupt acceptance and internal processing after vector fetch.

5. Not available in this LSI.

Rev. 2.0, 04/02, page 114 of 906

DMAC

Selection

circuit

DTCER

DTVECR

Control logic

Determination of

priority

CPU

DTC

Select

signal

IRQ
interrupt

On-chip
supporting
module

Disable

signal

Clear signal

Interrupt controller

I, I2 to I0

Interrupt source

clear signal

Interrupt

request

DTC activation
request vector
number

CPU interrupt
request vector
number

SWDTE

clear signal

Clear signal

Figure 5.6 DTC, DMAC, and Interrupt Controller

(1) Selection of Interrupt Source: The activation factors for each channel of DMAC are selected
by DTF3 to DTF0 bits of DMACR. The DTA bit of DMABCR can be used to select whether the
selected activation factors are managed by DMAC. By setting the DTA bit to 1, the interrupt
factor which were the activation factor for that DMAC do not act as the DTC activation factor or
the CPU interrupt factor.

Interrupt factors other than the interrupts managed by the DMAC are selected as DTC activation
source or CPU interrupt source by the DTCE bit of DTCERA to DTCERF of DTC.

By specifying the DISEL bit of the DTC's MRB, it is possible to clear the DTCE bit to 0 after
DTC data transfer, and request a CPU interrupt.

If DTC carries out the designate number of data transfers and the transfer counter reads 0, after
DTC data transfer, the DTCE bit is also cleared to 0, and an interrupt is requested to the CPU.

(2) Determination of Priority: The DTC activation source is selected in accordance with the
default priority order, and is not affected by mask or priority levels. See table 9.1 for the respective
priority. DMAC inputs activation factor directly to each channel.

Rev. 2.0, 04/02, page 115 of 906

(3) Operation Order: If the same interrupt is selected as a DTC activation source and a CPU
interrupt source, the DTC data transfer is performed first, followed by CPU interrupt exception
handling.

If the same interrupt is selected as the DMAC activation factor and as the DTC activation factor or
CPU interrupt factor, these operate independently.

Table 5.6 shows the interrupt factor clear control and selection of interrupt factors by specification
of the DTA bit of DMAC's DMABCR, the DTCE bit of DTC's DTCERA to DTCERH, and the
DISEL bit of DTC's MRB.

Table 5.6

Interrupt Source Selection and Clearing Control

Settings

DMAC

DTC

Interrupt Sources Selection/Clearing Control

DTA

DTCE

DISEL

DMAC

DTC

CPU

Legend

: The relevant interrupt is used. Interrupt source clearing is performed.

(The CPU should clear the source flag in the interrupt handling routine.)

: The relevant interrupt is used. The interrupt source is not cleared.

X : The relevant interrupt cannot be used.

: Don't care

Note: The SCI or A/D converter interrupt source is cleared when the DMAC or DTC reads or

writes to the prescribed register, and is not dependent upon the DTA bit or DISEL bit.

Rev. 2.0, 04/02, page 116 of 906

5.7

Usage Notes

5.7.1

Contention between Interrupt Generation and Disabling

When an interrupt enable bit is cleared to 0 to mask interrupts, the masking becomes effective
after execution of the instruction.

When an interrupt enable bit is cleared to 0 by an instruction such as BCLR or MOV, if an
interrupt is generated during execution of the instruction, the interrupt concerned will still be
enabled on completion of the instruction, and so interrupt exception handling for that interrupt will
be executed on completion of the instruction. However, if there is an interrupt request of higher
priority than that interrupt, interrupt exception handling will be executed for the higher-priority
interrupt, and the lower-priority interrupt will be ignored. The same also applies when an interrupt
source flag is cleared to 0. Figure 5.7 shows an example in which the TCIEV bit in the TPU's
TIER_0 register is cleared to 0. The above contention will not occur if an enable bit or interrupt
source flag is cleared to 0 while the interrupt is masked.

Internal
address bus

Internal
write signal

TCIEV

TCFV

TCIV
interrupt signal

TIER_0 write cycle by CPU

TCIV exception handling

TIER_0 address

Figure 5.7 Contention between Interrupt Generation and Disabling

Rev. 2.0, 04/02, page 117 of 906

5.7.2

Instructions that Disable Interrupts

Instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these
instructions is executed, all interrupts including NMI are disabled and the next instruction is
always executed. When the I bit is set by one of these instructions, the new value becomes valid
two states after execution of the instruction ends.

5.7.3

Times when Interrupts are Disabled

There are times when interrupt acceptance is disabled by the interrupt controller.

The interrupt controller disables interrupt acceptance for a 3-state period after the CPU has
updated the mask level with an LDC, ANDC, ORC, or XORC instruction.

5.7.4

Interrupts during Execution of EEPMOV Instruction

Interrupt operation differs between the EEPMOV.B instruction and the EEPMOV.W instruction.

With the EEPMOV.B instruction, an interrupt request (including NMI) issued during the transfer
is not accepted until the transfer is completed.

With the EEPMOV.W instruction, if an interrupt request is issued during the transfer, interrupt
exception handling starts at a break in the transfer cycle. The PC value saved on the stack in this
case is the address of the next instruction. Therefore, if an interrupt is generated during execution
of an EEPMOV.W instruction, the following coding should be used.

L1: EEPMOV.W

MOV.W R4,R4

BNE L1

5.7.5

Change of IRQ Pin Select Register (ITSR) Setting

When the ITSR setting is changed, an edge occurs internally and the IRQnF bit (n = 0 to 15) of
ISR may be set to 1 at the unintended timing if the selected pin level before the change is different
from the selected pin level after the change. If the IRQn interrupt request (n = 0 to 15) is enabled,
the interrupt exception handling is executed. To prevent the unintended interrupt, ITSR setting
should be changed while the IRQn interrupt request is disabled, then the IRQnF bit should be
cleared to 0.

Rev. 2.0, 04/02, page 119 of 906

Section 6 Bus Controller (BSC)

This LSI has an on-chip bus controller (BSC) that manages the external address space divided into
eight areas.

The bus controller also has a bus arbitration function, and controls the operation of the internal bus
mastership--the CPU, DMA controller (DMAC), EXDMA controller (EXDMAC), and data
transfer controller (DTC).

6.1

Features

Manages external address space in area units

Manages the external address space divided into eight areas of 2 Mbytes

Bus specifications can be set independently for each area

Burst ROM, DRAM, or synchronous DRAM* interface can be set

Basic bus interface

Chip select signals (

&6 to &6) can be output for areas 0 to 7

8-bit access or 16-bit access can be selected for each area

2-state access or 3-state access can be selected for each area

Program wait states can be inserted for each area

Burst ROM interface

Burst ROM interface can be set independently for areas 0 and 1

DRAM interface

DRAM interface can be set for areas 2 to 5

Synchronous DRAM interface

Continuous synchronous DRAM space can be set for areas 2 to 5

Bus arbitration function

Includes a bus arbiter that arbitrates bus mastership between the CPU, DMAC, and DTC

Note: The Synchronous DRAM interface is not supported in the H8S/2678 Series.

BSCS202A_010020020400

Rev. 2.0, 04/02, page 120 of 906

A block diagram of the bus controller is shown in figure 6.1.

Area decoder

Internal address bus

EXDMAC address bus

External bus
control signals

Internal bus control signals

Internal data bus

Control registers

Address

selector

External bus

arbiter

External bus controller

Internal bus

arbiter

Internal bus controller

Internal bus master bus request signal

EXDMAC bus request signal

Internal bus master bus acknowledge signal

EXDMAC bus acknowledge signal

CPU bus request signal

DTC bus request signal

DMAC bus request signal

CPU bus acknowledge signal

DTC bus acknowledge signal

DMAC bus acknowledge signal

ABWCR

ASTCR

WTCRAH WTCRAL

WTCRBH WTCRBL

RDNCR

DRAMCR

Legend
ABWCR

: Bus width control register

ASTCR

: Access state control register

WTCRAH, WTCRAL,
WTCRBH, and WTCRBL : Wait control registers AH, AL, BH, and BL
RDNCR

: Read strobe timing control register

CSACRH and CSACRL : CS assertion period control registers
BROMCRH

: Area 0 burst ROM interface control register

Note:

DRACCR is an 8-bit register in the H8S/2678 Series and a 16-bit register in the H8S/2678R Series.

BROMCRL : Area 1 burst ROM interface control register
BCR

: Bus control register

DRAMCR : DRAM control register
DRACCR

: DRAM access control register

REFCR

: Refresh control register

RTCNT

: Refresh timer counter

RTCOR

: Refresh time constant register

REFCR

RTCNT

RTCOR

CSACRH

CSACRL

BROMCRH BROMCRL

BCR

DRACCR

Figure 6.1 Block Diagram of Bus Controller

Rev. 2.0, 04/02, page 121 of 906

6.2

Input/Output Pins

Table 6.1 shows the pin configuration of the bus controller.

Table 6.1

Pin Configuration

Name

Symbol

I/O

Function

Address strobe

Output

Strobe signal indicating that basic bus
interface space is accessed and address
output on address bus is enabled.

Read

Output

Strobe signal indicating that basic bus
interface space is being read.

High write/write enable

+:5

Output

Strobe signal indicating that basic bus
interface space is written to, and upper half
(D15 to D8) of data bus is enabled or
DRAM interface space write enable signal.

Low write

/:5

Output

Strobe signal indicating that basic bus
interface space is written to, and lower half
(D7 to D0) of data bus is enabled.

Chip select 0

Output

Strobe signal indicating that area 0 is
selected.

Chip select 1

Output

Strobe signal indicating that area 1 is
selected

Chip select 2/row address
strobe 2/row address strobe

5$6

5$6*

Output

Strobe signal indicating that area 2 is
selected, DRAM row address strobe signal
when area 2 is DRAM interface space or
areas 2 to 5 are set as continuous DRAM
interface space, or row address strobe
signal of the synchronous DRAM when the
synchronous DRAM interface is selected.

Chip select 3/row address
strobe 3/column address
strobe

5$6

&$6*

Output

Strobe signal indicating that area 3 is
selected, DRAM row address strobe signal
when area 3 is DRAM interface space, or
column address strobe signal of the
synchronous DRAM when the synchronous
DRAM interface is selected.

Rev. 2.0, 04/02, page 122 of 906

Name

Symbol

I/O

Function

Chip select 4/row address
strobe 4/write enable

5$6

:(*

Output

Strobe signal indicating that area 4 is
selected, DRAM row address strobe signal
when area 4 is DRAM interface space, or
write enable signal of the synchronous
DRAM when the synchronous DRAM
interface is selected.

Chip select 5/row address
strobe 5/SDRAM

5$6

SDRAM

Output

Strobe signal indicating that area 5 is
selected, DRAM row address strobe signal
when area 5 is DRAM interface space, or
dedicated clock signal for the synchronous
DRAM when the synchronous DRAM
interface is selected.

Chip select 6

Output

Strobe signal indicating that area 6 is
selected.

Chip select 7

Output

Strobe signal indicating that area 7 is
selected.

Upper column address
strobe/upper data mask enable

8&$6

'408*

Output

16-bit DRAM interface space upper column
address strobe signal, 8-bit DRAM interface
space column address strobe signal, upper
data mask signal of 16-bit synchronous
DRAM interface space, or data mask signal
of 8-bit synchronous DRAM interface
space.

Lower column address strobe/
lower data mask enable

/&$6

'40/*

Output

16-bit DRAM interface space lower column
address strobe signal or lower data mask
signal for the 16-bit synchronous DRAM
interface space.

Output enable/clock enable

/CKE

Output

Output enable signal for the DRAM
interface space or clock enable signal for
the synchronous DRAM interface space.

Wait

:$,7

Input

Wait request signal when accessing
external space.

Bus request

%5(4

Input

Request signal for release of bus to
external bus master.

Bus request acknowledge

%$&.

Output

Acknowledge signal indicating that bus has
been released to external bus master.

Rev. 2.0, 04/02, page 123 of 906

Name

Symbol

I/O

Function

Bus request output

%5(42

Output

External bus request signal used when
internal bus master accesses external
address space when external bus is
released.

Data transfer acknowledge
1 (DMAC)

'$&.

Output

Data transfer acknowledge signal for single
address transfer by DMAC channel 1.

Data transfer acknowledge
0 (DMAC)

'$&.

Data transfer acknowledge signal for single
address transfer by DMAC channel 0.

Data transfer acknowledge
3 (EXDMAC)

('$&.

Output

Data transfer acknowledge signal for single
address transfer by EXDMAC channel 3.

Data transfer acknowledge
2 (EXDMAC)

('$&.

Output

Data transfer acknowledge signal for single
address transfer by EXDMAC channel 2.

Data transfer acknowledge
1 (EXDMAC)

('$&.

Output

Data transfer acknowledge signal for single
address transfer by EXDMAC channel 1.

Data transfer acknowledge
0 (EXDMAC)

('$&.

Output

Data transfer acknowledge signal for single
address transfer by EXDMAC channel 0.

Note: These pins are not supported in the H8S/2678 Series.

6.3

Register Descriptions

The bus controller has the following registers.

Bus width control register (ABWCR)

Access state control register (ASTCR)

Wait control register AH (WTCRAH)

Wait control register AL (WTCRAL)

Wait control register BH (WTCRBH)

Wait control register BL (WTCRBL)

Read strobe timing control register (RDNCR)

&6 assertion period control register H (CSACRH)

&6 assertion period control register L (CSACRL)

Area 0 burst ROM interface control register (BROMCRH)

Area 1 burst ROM interface control register (BROMCRL)

Bus control register (BCR)

DRAM control register (DRAMCR)

DRAM access control register (DRACCR)

Refresh control register (REFCR)

Refresh timer counter (RTCNT)

Rev. 2.0, 04/02, page 124 of 906

Refresh time constant register (RTCOR)

6.3.1

Bus Width Control Register (ABWCR)

ABWCR designates each area in the external address space as either 8-bit access space or 16-bit
access space.

Bit

Bit Name

Initial Value

R/W

Description

7
6
5
4
3
2
1
0

ABW7
ABW6
ABW5
ABW4
ABW3
ABW2
ABW1
ABW0

1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0

R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W

Area 7 to 0 Bus Width Control

These bits select whether the corresponding
area is to be designated as 8-bit access space
or 16-bit access space.

0: Area n is designated as 16-bit access space

1: Area n is designated as 8-bit access space

(n = 7 to 0)

Note: In modes 2, 4, and 6, ABWCR is initialized to 1. In modes 1, 5, and 7, ABWCR is initialized

to 0.

6.3.2

Access State Control Register (ASTCR)

ASTCR designates each area in the external address space as either 2-state access space or 3-state
access space.

Bit

Bit Name

Initial Value

R/W

Description

7
6
5
4
3
2
1
0

AST7
AST6
AST5
AST4
AST3
AST2
AST1
AST0

1
1
1
1
1
1
1
1

R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W

Area 7 to 0 Access State Control

These bits select whether the corresponding
area is to be designated as 2-state access
space or 3-state access space. Wait state
insertion is enabled or disabled at the same
time.

0: Area n is designated as 2-state access space

Wait state insertion in area n access is disabled

1: Area n is designated as 3-state access space

Wait state insertion in area n access is enabled

(n = 7 to 0)

Rev. 2.0, 04/02, page 126 of 906

Bit

Bit Name

Initial Value

R/W

Description

10
9
8

W62
W61
W60

1
1
1

R/W
R/W
R/W

Area 6 Wait Control 2 to 0

These bits select the number of program wait
states when accessing area 6 while AST6 bit in
ASTCR = 1.

000: Program wait not inserted

001: 1 program wait state inserted

010: 2 program wait states inserted

011: 3 program wait states inserted

100: 4 program wait states inserted

101: 5 program wait states inserted

110: 6 program wait states inserted

111: 7 program wait states inserted

WTARAL

Bit

Bit Name

Initial Value

R/W

Description

Reserved

This bit is always read as 0 and cannot be
modified.

6
5
4

W52
W51
W50

1
1
1

R/W
R/W
R/W

Area 5 Wait Control 2 to 0

These bits select the number of program wait
states when accessing area 5 while AST5 bit in
ASTCR = 1.

000: Program wait not inserted

001: 1 program wait state inserted

010: 2 program wait states inserted

011: 3 program wait states inserted

100: 4 program wait states inserted

101: 5 program wait states inserted

110: 6 program wait states inserted

111: 7 program wait states inserted

Rev. 2.0, 04/02, page 127 of 906

Bit

Bit Name

Initial Value

R/W

Description

Reserved

This bit is always read as 0 and cannot be
modified.

2
1
0

W42
W41
W40

1
1
1

R/W
R/W
R/W

Area 4 Wait Control 2 to 0

These bits select the number of program wait
states when accessing area 4 while AST4 bit in
ASTCR = 1.

000: Program wait not inserted

001: 1 program wait state inserted

010: 2 program wait states inserted

011: 3 program wait states inserted

100: 4 program wait states inserted

101: 5 program wait states inserted

110: 6 program wait states inserted

111: 7 program wait states inserted

WTCRBH

Bit

Bit Name

Initial Value

R/W

Description

Reserved

This bit is always read as 0 and cannot be
modified.

14
13
12

W32
W31
W30

1
1
1

R/W
R/W
R/W

Area 3 Wait Control 2 to 0

These bits select the number of program wait
states when accessing area 3 while AST3 bit in
ASTCR = 1.

000: Program wait not inserted

001: 1 program wait state inserted

010: 2 program wait states inserted

011: 3 program wait states inserted

100: 4 program wait states inserted

101: 5 program wait states inserted

110: 6 program wait states inserted

111: 7 program wait states inserted

Reserved

This bit is always read as 0 and cannot be
modified.

Rev. 2.0, 04/02, page 128 of 906

Bit

Bit Name

Initial Value

R/W

Description

10
9
8

W22
W21
W20

1
1
1

R/W
R/W
R/W

Area 2 Wait Control 2 to 0

These bits select the number of program wait
states when accessing area 2 while AST2 bit in
ASTCR = 1.

A CAS latency is set when the synchronous
DRAM is connected

. The setting of area 2 is

reflected to the setting of areas 2 to 5. A CAS
latency can be set regardless of whether or not
an ASTCR wait state insertion is enabled.

000: Program wait not inserted

001: 1 program wait state inserted

010: 2 program wait states inserted

011: 3 program wait states inserted

100: 4 program wait states inserted

101: 5 program wait states inserted

110: 6 program wait states inserted

111: 7 program wait states inserted

000: Synchronous DRAM of CAS latency 1 is
connected to areas 2 to 5.

001: Synchronous DRAM of CAS latency 2 is
connected to areas 2 to 5.

010: Synchronous DRAM of CAS latency 3 is
connected to areas 2 to 5.

011: Synchronous DRAM of CAS latency 4 is
connected to areas 2 to 5.

1XXX: Setting prohibited.

Note: The synchronous DRAM interface is not supported in the H8S/2678 Series.

Legend x: Don't care.

Rev. 2.0, 04/02, page 129 of 906

WTCRBL

Bit

Bit Name

Initial Value

R/W

Description

Reserved

This bit is always read as 0 and cannot be
modified.

6
5
4

W12
W11
W10

1
1
1

R/W
R/W
R/W

Area 1 Wait Control 2 to 0

These bits select the number of program wait
states when accessing area 1 while AST1 bit in
ASTCR = 1.

000: Program wait not inserted

001: 1 program wait state inserted

010: 2 program wait states inserted

011: 3 program wait states inserted

100: 4 program wait states inserted

101: 5 program wait states inserted

110: 6 program wait states inserted

111: 7 program wait states inserted

Reserved

This bit is always read as 0 and cannot be
modified.

2
1
0

W02
W01
W00

1
1
1

R/W
R/W
R/W

Area 0 Wait Control 2 to 0

These bits select the number of program wait
states when accessing area 0 while AST0 bit in
ASTCR = 1.

000: Program wait not inserted

001: 1 program wait state inserted

010: 2 program wait states inserted

011: 3 program wait states inserted

100: 4 program wait states inserted

101: 5 program wait states inserted

110: 6 program wait states inserted

111: 7 program wait states inserted

Rev. 2.0, 04/02, page 130 of 906

6.3.4

Read Strobe Timing Control Register (RDNCR)

RDNCR selects the read strobe signal (

5') negation timing in a basic bus interface read access.

Bit

Bit Name

Initial Value

R/W

Description

7
6
5
4
3
2
1
0

RDN7
RDN6
RDN5
RDN4
RDN3
RDN2
RDN1
RDN0

0
0
0
0
0
0
0
0

R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W

Read Strobe Timing Control 7 to 0

These bits set the negation timing of the read
strobe in a corresponding area read access.

As shown in figure 6.2, the read strobe for an
area for which the RDNn bit is set to 1 is
negated one half-state earlier than that for an
area for which the RDNn bit is cleared to 0. The
read data setup and hold time specifications are
also one half-state earlier.

0: In an area n read access, the

is negated

at the end of the read cycle

1: In an area n read access, the

is negated

one half-state before the end of the read cycle

(n = 7 to 0)

Bus cycle

Data

RDNn = 0

RDNn = 1

Figure 6.2 Read Strobe Negation Timing (Example of 3-State Access Space)

Rev. 2.0, 04/02, page 131 of 906

6.3.5

$ Assertion Period Control Registers H, L (CSACRH, CSACRL)

CSACRH and CSACRL select whether or not the assertion period of the basic bus interface chip
select signals (

&6Q) and address signals is to be extended. Extending the assertion period of the

&6Q and address signals allows flexible interfacing to external I/O devices.

CSACRH

Bit

Bit Name

Initial Value

R/W

Description

7
6
5
4
3
2
1
0

CSXH7
CSXH6
CSXH5
CSXH4
CSXH3
CSXH2
CSXH1
CSXH0

0
0
0
0
0
0
0
0

R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W

and Address Signal Assertion Period

Control 1

These bits specify whether or not the T

cycle is

to be inserted (see figure 6.3). When an area for
which the CSXHn bit is set to 1 is accessed, a
one-state T

cycle, in which only the

&6Q

and

address signals are asserted, is inserted before
the normal access cycle.

0: In area n basic bus interface access, the

&6Q

and address assertion period (T

) is not

extended

1: In area n basic bus interface access, the

&6Q

and address assertion period (T

) is extended

(n = 7 to 0)

CSACRL

Bit

Bit Name

Initial Value

R/W

Description

7
6
5
4
3
2
1
0

CSXT7
CSXT6
CSXT5
CSXT4
CSXT3
CSXT2
CSXT1
CSXT0

0
0
0
0
0
0
0
0

R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W

and Address Signal Assertion Period

Control 2

These bits specify whether or not the T

cycle

shown in figure 6.3 is to be inserted. When an
area for which the CSXTn bit is set to 1 is
accessed, a one-state T

cycle, in which only the

&6Q

and address signals are asserted, is

inserted before the normal access cycle.

0: In area n basic bus interface access, the

&6Q

and address assertion period (T

) is not

extended

1: In area n basic bus interface access, the

&6Q

and address assertion period (T

) is extended

(n = 7 to 0)

Rev. 2.0, 04/02, page 133 of 906

6.3.6

Area 0 Burst ROM Interface Control Register (BROMCRH)

Area 1 Burst ROM Interface Control Register (BROMCRL)

BROMCRH and BROMCRL are used to make burst ROM interface settings. Area 0 and area 1
burst ROM interface settings can be made independently in BROMCRH and BROMCRL,
respectively.

Bit

Bit Name

Initial Value

R/W

Description

BSRMn

R/W

Burst ROM Interface Select

Selects the basic bus interface or burst ROM
interface.

0: Basic bus interface space

1: Burst ROM interface space

6
5
4

BSTSn2
BSTSn1
BSTSn0

0
0
0

R/W
R/W
R/W

Burst Cycle Select

These bits select the number of burst cycle
states.

000: 1 state

001: 2 states

010: 3 states

011: 4 states

100: 5 states

101: 6 states

110: 7 states

111: 8 states

3
2

0
0

R/W
R/W

Reserved

These bits are always read as 0. The initial
value should not be changed.

1
0

BSWDn1
BSWDn0

0
0

R/W
R/W

Burst Word Number Select

These bits select the number of words that can
be burst-accessed on the burst ROM interface.

00: Maximum 4 words

01: Maximum 8 words

10: Maximum 16 words

11: Maximum 32 words

(n = 1 or 0)

Rev. 2.0, 04/02, page 134 of 906

6.3.7

Bus Control Register (BCR)

BCR is used for idle cycle settings, selection of the external bus released state protocol, enabling
or disabling of the write data buffer function, and enabling or disabling of

:$,7 pin input.

Bit

Bit Name

Initial Value

R/W

Description

BRLE

R/W

External Bus Release Enable

Enables or disables external bus release.

0: External bus release disabled

%5(4

%$&.

, and

%5(42

pins can be used

as I/O ports

1: External bus release enabled

BREQOE

R/W

%5(42

Pin Enable

Controls outputting the bus request signal
(BREQO) to the external bus master in the
external bus released state, when an internal
bus master performs an external address space
access, or when a refresh request is generated.

%5(42

output disabled

%5(42

pin can be used as I/O port

%5(42

output enabled

R/W

Reserved

This bit can be read from or written to. However,
the write value should always be 0.

IDLC

R/W

Idle Cycle State Number Select

Specifies the number of states in the idle cycle
set by ICIS2, ICIS1, and ICIS0.

0: Idle cycle comprises 1 state

1: Idle cycle comprises 2 states

ICIS1

R/W

Idle Cycle Insert 1

When consecutive external read cycles are
performed in different areas, an idle cycle can
be inserted between the bus cycles.

0: Idle cycle not inserted

1: Idle cycle inserted

Rev. 2.0, 04/02, page 135 of 906

Bit

Bit Name

Initial Value

R/W

Description

ICIS0

R/W

Idle Cycle Insert 0

When an external read cycle and external write
cycle are performed consecutively, an idle cycle
can be inserted between the bus cycles.

0: Idle cycle not inserted

1: Idle cycle inserted

WDBE

R/W

Write Data Buffer Enable

The write data buffer function can be used for
an external write cycle or DMAC single address
transfer cycle.

0: Write data buffer function not used

1: Write data buffer function used

WAITE

R/W

:$,7

Pin Enable

Selects enabling or disabling of wait input by the

:$,7

pin.

0: Wait input by

:$,7

pin disabled

:$,7

pin can be used as I/O port

1: Wait input by

:$,7

pin enabled

7
to
3

R/W

Reserved

These are readable/writable bits, but the write
value should always be 0.

ICIS2

R/W

Idle Cycle Insert 2

When an external write cycle and external read
cycle are performed consecutively, an idle cycle
can be inserted between the bus cycles.

0: Idle cycle not inserted

1: Idle cycle inserted

Note: Bit 2 is a reserved bit in the H8S/2678

Series. This bit is readable/writable, but
the write value should always be 0.

1
to
0

R/W

Reserved

These bits can be read from or written to.
However, the write value should always be 0.

Rev. 2.0, 04/02, page 136 of 906

6.3.8

DRAM Control Register (DRAMCR)

DRAMCR is used to make DRAM/synchronous DRAM* interface settings.

Note:

The synchronous DRAM interface is not supported in the H8S/2678 Series.

Bit

Bit Name

Initial Value

R/W

Description

OEE

R/W

Output Enable

The OE signal used when EDO page mode
DRAM is connected can be output from the
(OE) pin. The

signal is common to all areas

designated as DRAM space.

When the synchronous DRAM is connected, the
CKE signal can be output from the (OE) pin.
The CKE signal is common to the continuous
synchronous DRAM space.

/CKE signal output disabled

(

)/(CKE) pin can be used as I/O port

/CKE signal output enabled

RAST

R/W

5$6

Assertion Timing Select

Selects whether, in DRAM access, the

5$6

signal is asserted from the start of the T

cycle

(rising edge of ø) or from the falling edge of ø.

Figure 6.4 shows the relationship between the
RAST bit setting and the

5$6

assertion timing.

The setting of this bit applies to all areas
designated as DRAM space.

5$6

is asserted from ø falling edge in T

cycle

5$6

is asserted from start of T

cycle

R/W

Reserved

This bit can be read from or written to. However,
the write value should always be 0.

Rev. 2.0, 04/02, page 137 of 906

Bit

Bit Name

Initial Value

R/W

Description

CAST

R/W

Column Address Output Cycle Number Select

Selects whether the column address output
cycle in DRAM access comprises 3 states or 2
states. The setting of this bit applies to all areas
designated as DRAM space.

0: 2 states

1: 3 states

R/W

Reserved

This bit can be read from or written to. However,
the write value should always be 0.

10
9
8

RMTS2
RMTS1
RMTS0

0
0
0

R/W
R/W
R/W

DRAM/Continuous Synchronous DRAM Space
Select

These bits designate DRAM/continuous
synchronous DRAM space for areas 2 to 5.

When continuous DRAM space is set, it is
possible to connect large-capacity DRAM
exceeding 2 Mbytes per area. In this case, the

5$6

signal is output from the

pin.

When continuous synchronous DRAM space is
set, it is possible to connect large-capacity
synchronous DRAM exceeding 2 Mbytes per
area. In this case, the

5$6

&$6

, and

signals are output from

, and

pins, respectively. When synchronous DRAM
mode is set, the mode registers of the
synchronous DRAM can be set.

000: Normal space

001: Normal space in areas 3 to 5

DRAM space in area 2

010: Normal space in areas 4 and 5

DRAM space in areas 2 and 3

011: DRAM space in areas 2 to 5

100: Continuous synchronous DRAM space
(setting prohibited in the H8S/2678 Series)

101: Synchronous DRAM mode setting (setting
prohibited in the H8S/2678 Series)

110: Setting prohibited

111: Continuous DRAM space in areas 2 to 5

Rev. 2.0, 04/02, page 138 of 906

Bit

Bit Name

Initial Value

R/W

Description

R/W

Burst Access Enable

Selects enabling or disabling of burst access to
areas designated as DRAM/continuous
synchronous DRAM space. DRAM/continuous
synchronous DRAM space burst access is
performed in fast page mode. When using EDO
page mode DRAM, the

signal must be

connected.

0: Full access

1: Access in fast page mode

RCDM

R/W

5$6

Down Mode

When access to DRAM space is interrupted by
an access to normal bus space, an access to an
internal I/O register, etc., this bit selects whether
the

5$6

signal is held low while waiting for the

next DRAM access (

5$6

down mode), or is

driven high again (

5$6

up mode). The setting

of this bit is valid only when the BE bit is set to
1.

If this bit is cleared to 0 when set to 1 in the

5$6

down state, the

5$6

down state is cleared

at that point, and

5$6

goes high.

When continuous synchronous DRAM space is
set, reading from and writing to this bit is
enabled. However, the setting does not affect
the operation.

5$6

up mode selected for DRAM space

access

5$6

down mode selected for DRAM space

access

Rev. 2.0, 04/02, page 139 of 906

Bit

Bit Name

Initial Value

R/W

Description

DDS

R/W

DMAC Single Address Transfer Option

Selects whether full access is always performed
or burst access is enabled when DMAC single
address transfer is performed on the
DRAM/synchronous DRAM interface.

When the BE bit is cleared to 0 in DRAMCR,
disabling DRAM/synchronous DRAM burst
access, DMAC single address transfer is
performed in full access mode regardless of the
setting of this bit.

This bit has no effect on other bus master
external accesses or DMAC dual address
transfers.

0: Full access is always executed

1: Burst access is enabled

EDDS

R/W

EXDMAC Single Address Transfer Option

Selects whether full access is always performed
or burst access is enabled when EXDMAC
single address transfer is performed on the
DRAM/synchronous DRAM interface.

When the BE bit is cleared to 0 in DRAMCR,
disabling DRAM/synchronous DRAM burst
access, EXDMAC single address transfer is
performed in full access mode regardless of the
setting of this bit.

This bit has no effect on other bus master
external accesses or EXDMAC dual address
transfers.

0: Full access is always executed

1: Burst access is enabled

R/W

Reserved

This bit can be read from or written to. However,
the write value should always be 0.

Rev. 2.0, 04/02, page 140 of 906

Bit

Bit Name

Initial Value

R/W

Description

2
1
0

MXC2
MXC1
MXC0

0
0
0

R/W
R/W
R/W

Address Multiplex Select

These bits select the size of the shift toward the
lower half of the row address in row
address/column address multiplexing. In burst
operation on the DRAM/synchronous DRAM
interface, these bits also select the row address
bits to be used for comparison.

When the MXC2 bit is set to 1 while continuous
synchronous DRAM space is set, the address
precharge setting command (Precharge-sel) is
output to the upper column address. For details,
refer to sections 6.6.2 and 6.7.2, Address
Multiplexing.

DRAM interface

000: 8-bit shift

When 8-bit access space is designated:

Row address bits A23 to A8 used for
comparison

When 16-bit access space is designated:

Row address bits A23 to A9 used for
comparison

001: 9-bit shift

When 8-bit access space is designated:

Row address bits A23 to A9 used for
comparison

When 16-bit access space is designated:

Row address bits A23 to A10 used for
comparison

010: 10-bit shift

When 8-bit access space is designated:

Row address bits A23 to A10 used for
comparison

When 16-bit access space is designated:

Row address bits A23 to A11 used for
comparison

Rev. 2.0, 04/02, page 141 of 906

Bit

Bit Name

Initial Value

R/W

Description

011: 11-bit shift

When 8-bit access space is designated:

Row address bits A23 to A11 used for
comparison

When 16-bit access space is designated:

Row address bits A23 to A12 used for
comparison

Synchronous DRAM interface

100: 8-bit shift

When 8-bit access space is designated:

Row address bits A23 to A8 used for
comparison

When 16-bit access space is designated:

Row address bits A23 to A9 used for
comparison

The precharge-sel is A15 to A9 of the
column address.

101: 9-bit shift

When 8-bit access space is designated:

Row address bits A23 to A9 used for
comparison

When 16-bit access space is designated:

Row address bits A23 to A10 used for
comparison

The precharge-sel is A15 to A10 of the
column address.

110: 10-bit shift

When 8-bit access space is designated:

Row address bits A23 to A10 used for
comparison

When 16-bit access space is designated:

Row address bits A23 to A11 used for
comparison

The precharge-sel is A15 to A11 of the
column address.

Rev. 2.0, 04/02, page 143 of 906

6.3.9

DRAM Access Control Register (DRACCR)

DRACCR is used to set the DRAM/synchronous DRAM interface bus specifications.

Note:

The synchronous DRAM interface is not supported in the H8S/2678 Series.

H8S/2678 Series

Bit

Bit Name

Initial Value

R/W

Description

DRMI

R/W

Idle Cycle Insertion

An idle cycle can be inserted after a DRAM read
cycle when a continuous normal space access
cycle follows a DRAM read cycle. Idle cycle
insertion conditions, setting of number of states,
etc., comply with settings of bits ICIS1, ICIS0,
and IDLC in BCR register

0: Idle cycle not inserted

1: Idle cycle inserted

R/W

Reserved

This bit can be read from or written to. However,
the write value should always be 0.

5
4

TPC1
TPC0

0
0

R/W
R/W

Precharge State Control

These bits select the number of states in the
RAS precharge cycle in normal access and
refreshing.

00: 1 state

01: 2 states

10: 3 states

11: 4 states

3
2

0
0

R/W
R/W

Reserved

These bits can be read from or written to.
However, the write value should always be 0.

1
0

RCD1
RCD0

0
0

R/W
R/W

RAS-CAS Wait Control

These bits select a wait cycle to be inserted
between the

5$6

assert cycle and

&$6

assert

cycle.

00: Wait cycle not inserted

01: 1-state wait cycle inserted

10: 2-state wait cycle inserted

11: 3-state wait cycle inserted

Rev. 2.0, 04/02, page 144 of 906

H8S/2678R Series

Bit

Bit Name

Initial Value

R/W

Description

DRMI

R/W

Idle Cycle Insertion

An idle cycle can be inserted after a
DRAM/synchronous DRAM access cycle when
a continuous normal space access cycle follows
a DRAM/synchronous DRAM access cycle. Idle
cycle insertion conditions, setting of number of
states, etc., comply with settings of bits ICIS2,
ICIS1, ICIS0, and IDLC in BCR register

0: Idle cycle not inserted

1: Idle cycle inserted

R/W

Reserved

This bit can be read from or written to. However,
the write value should always be 0.

13
12

TPC1
TPC0

0
0

R/W
R/W

Precharge State Control

These bits select the number of states in the
RAS precharge cycle in normal access and
refreshing.

00: 1 state

01: 2 states

10: 3 states

11: 4 states

SDWCD

R/W

CAS Latency Control Cycle Disabled during
Continuous Synchronous DRAM Space Write
Access

Disables CAS latency control cycle (Tc1)
inserted by WTCR settings during synchronous
DRAM write access (see figure 6.5).

0: Enables CAS latency control cycle

1: Disables CAS latency control cycle

R/W

Reserved

This bit can be read from or written to. However,
the write value should always be 0.

Rev. 2.0, 04/02, page 145 of 906

Bit

Bit Name

Initial Value

R/W

Description

9
8

RCD1
RCD0

0
0

R/W
R/W

RAS-CAS Wait Control

These bits select a wait cycle to be inserted
between the

5$6

assert cycle and

&$6

assert

cycle. A 1- to 4-state wait cycle can be inserted.

00: Wait cycle not inserted

01: 1-state wait cycle inserted

10: 2-state wait cycle inserted

11: 3-state wait cycle inserted

7 to 4

R/W

Reserved

These bits can be read from or written to.
However, the write value should always be 0.

CKSPE

R/W

Clock Suspend Enable

Enables clock suspend mode for extend read
data during DMAC and EXDMAC single
address transfer with the synchronous DRAM
interface.

0: Disables clock suspend mode

1: Enables clock suspend mode

R/W

Reserved

This bit can be read from or written to. However,
the write value should always be 0.

1
0

RDXC1
RDXC0

0
0

R/W
R/W

Read Data Extension Cycle Number Selection

Selects the number of read data extension cycle
(Tsp) insertion state in clock suspend mode.
These bits are valid when the CKSPE bit is set
to 1.

00: Inserts 1state

01: Inserts 2state

10: Inserts 3state

11: Inserts 4state

Rev. 2.0, 04/02, page 147 of 906

6.3.10

Refresh Control Register (REFCR)

REFCR specifies DRAM/synchronous DRAM interface refresh control.

Note:

The synchronous DRAM interface is not supported in the H8S/2678 Series.

Bit

Bit Name

Initial Value

R/W

Description

CMF

R/(W)

Compare Match Flag

Status flag that indicates a match between the
values of RTCNT and RTCOR.

[Clearing conditions]

When 0 is written to CMF after reading CMF

= 1 while the RFSHE bit is cleared to 0

When CBR refreshing is executed while the

RFSHE bit is set to 1

[Setting condition]

When RTCOR = RTCNT

CMIE

R/W

Compare Match Interrupt Enable

Enables or disables interrupt requests (CMI) by
the CMF flag when the CMF flag is set to 1.

This bit is valid when refresh control is not
performed. When the refresh control is
performed, this bit is always cleared to 0 and
cannot be modified.

0: Interrupt request by CMF flag disabled

1: Interrupt request by CMF flag enabled

13
12

RCW1
RCW0

0
0

R/W
R/W

&$6

5$6

Wait Control

These bits select the number of wait cycles to
be inserted between the

&$6

assert cycle and

5$6

assert cycle in a DRAM/synchronous

DRAM

refresh cycle.

00: Wait state not inserted

01: 1 wait state inserted

10: 2 wait states inserted

11: 3 wait states inserted

Note: Only 0 can be written, to clear the flag.

Rev. 2.0, 04/02, page 148 of 906

Bit

Bit Name

Initial Value

R/W

Description

R/W

Reserved

This bit can be read from or written to. However,
the write value should always be 0.

10
9
8

RTCK2
RTCK1
RTCK0

0
0
0

R/W
R/W
R/W

Refresh Counter Clock Select

These bits select the clock to be used to
increment the refresh counter. When the input
clock is selected with bits RTCK2 to RTCK0, the
refresh counter begins counting up.

000: Count operation halted

001: Count on ø/2

010: Count on ø/8

011: Count on ø/32

100: Count on ø/128

101: Count on ø/512

110: Count on ø/2048

111: Count on ø/4096

RFSHE

R/W

Refresh Control

Refresh control can be performed. When
refresh control is not performed, the refresh
timer can be used as an interval timer.

0: Refresh control is not performed

1: Refresh control is performed

CBRM

R/W

CBR Refresh Control

Selects CBR refreshing performed in parallel
with other external accesses, or execution of
CBR refreshing alone.

When the continuous synchronous DRAM
space is set, this bit can be read/written, but the
setting contents do not affect operations.

0: External access during CAS-before-RAS
refreshing is enabled

1: External access during CAS-before-RAS
refreshing is disabled

Rev. 2.0, 04/02, page 149 of 906

Bit

Bit Name

Initial Value

R/W

Description

5
4

RLW1
RLW0

0
0

R/W
R/W

Refresh Cycle Wait Control

These bits select the number of wait states to
be inserted in a DRAM interface CAS-before-
RAS refresh cycle/synchronous DRAM interface
auto-refresh cycle. This setting applies to all
areas designated as DRAM/continuous
synchronous DRAM space.

00: No wait state inserted

01: 1 wait state inserted

10: 2 wait states inserted

11: 3 wait states inserted

SLFRF

R/W

Self-Refresh Enable

If this bit is set to 1, DRAM/synchronous DRAM
self-refresh mode is selected when a transition
is made to the software standby state. This bit is
valid when the RFSHE bit is set to 1, enabling
refresh operations. It is cleared after recovery
from software standby mode.

0: Self-refreshing is disabled

1: Self-refreshing is enabled

2
1
0

TPCS2
TPCS1
TPCS0

0
0
0

R/W
R/W
R/W

Self-Refresh Precharge Cycle Control

These bits select the number of states in the
precharge cycle immediately after self-
refreshing.

The number of states in the precharge cycle
immediately after self-refreshing are added to
the number of states set by bits TPC1 and
TPC0 in DRACCR.

000: [TPC set value] states

001: [TPC set value + 1] states

010: [TPC set value + 2] states

011: [TPC set value + 3] states

100: [TPC set value + 4] states

101: [TPC set value + 5] states

110: [TPC set value + 6] states

111: [TPC set value + 7] states

Rev. 2.0, 04/02, page 150 of 906

6.3.11

Refresh Timer Counter (RTCNT)

RTCNT is an 8-bit readable/writable up-counter. RTCNT counts up using the internal clock
selected by bits RTCK2 to RTCK0 in REFCR.

When RTCNT matches RTCOR (compare match), the CMF flag in REFCR is set to 1 and
RTCNT is cleared to H'00. If the RFSHE bit in REFCR is set to 1 at this time, a refresh cycle is
started. If the RFSHE bit is cleared to 0 and the CMIE bit in REFCR is set to 1, a compare match
interrupt (CMI) is generated.

RTCNT is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in
software standby mode.

6.3.12

Refresh Time Constant Register (RTCOR)

RTCOR is an 8-bit readable/writable register that sets the period for compare match operations
with RTCNT.

The values of RTCOR and RTCNT are constantly compared, and if they match, the CMF flag in
REFCR is set to 1 and RTCNT is cleared to H'00.

RTCOR is initialized to H'FF by a reset and in hardware standby mode. It is not initialized in
software standby mode.

6.4

Bus Control

6.4.1

Area Division

The bus controller divides the 16-Mbyte address space into eight areas, 0 to 7, in 2-Mbyte units,
and performs bus control for external address space in area units. Chip select signals (

&6 to &6)

can be output for each area. In normal mode, a part of area 0, 64-kbyte address space, is
controlled. Figure 6.6 shows an outline of the memory map.

Note:

Normal mode is not available in this LSI.

Rev. 2.0, 04/02, page 152 of 906

6.4.2

Bus Specifications

The external address space bus specifications consist of five elements: bus width, number of
access states, number of program wait states, read strobe timing, and chip select (

&6) assertion

period extension states. The bus width and number of access states for on-chip memory and
internal I/O registers are fixed, and are not affected by the bus controller.

Bus Width: A bus width of 8 or 16 bits can be selected with ABWCR. An area for which an 8-bit
bus is selected functions as an 8-bit access space, and an area for which a 16-bit bus is selected
functions as a 16-bit access space. If all areas are designated as 8-bit access space, 8-bit bus mode
is set; if any area is designated as 16-bit access space, 16-bit bus mode is set.

Number of Access States: Two or three access states can be selected with ASTCR. An area for
which 2-state access is selected functions as a 2-state access space, and an area for which 3-state
access is selected functions as a 3-state access space. With the DRAM or synchronous DRAM
interface and burst ROM interface, the number of access states may be determined without regard
to the setting of ASTCR.

When 2-state access space is designated, wait insertion is disabled. When 3-state access space is
designated, it is possible to insert program waits by means of the WTCRA and WTCRB, and
external waits by means of the

:$,7 pin.

Note:

The synchronous DRAM interface is not supported in the H8S/2678 Series.

Number of Program Wait States: When 3-state access space is designated by ASTCR, the
number of program wait states to be inserted automatically is selected with WTCRA and WTCRB.
From 0 to 7 program wait states can be selected. Table 6.2 shows the bus specifications (bus
width, and number of access states and program wait states) for each basic bus interface area.

Rev. 2.0, 04/02, page 153 of 906

Table 6.2

Bus Specifications for Each Area (Basic Bus Interface)

ABWCR

ASTCR

WTCRA, WTCRB

Bus Specifications (Basic Bus Interface)

ABWn

ASTn

Wn2

Wn1

Wn0

Bus Width

Access
States

Program Wait
States

(n = 0 to 7)

Read Strobe Timing: RDNCR can be used to select either of two negation timings (at the end of
the read cycle or one half-state before the end of the read cycle) for the read strobe (

5') used in

the basic bus interface space.

Chip Select (

$) Assertion Period Extension States: Some external I/O devices require a setup

time and hold time between address and

&6 signals and strobe signals such as 5', +:5, and

/:5. CSACR can be used to insert states in which only the &6, $6, and address signals are
asserted before and after a basic bus space access cycle.

6.4.3

Memory Interfaces

The memory interfaces in this LSI comprise a basic bus interface that allows direct connection of
ROM, SRAM, and so on; a DRAM interface that allows direct connection of DRAM; a
synchronous DRAM interface* that allows direct connection of synchronous DRAM; and a burst

Rev. 2.0, 04/02, page 154 of 906

ROM interface that allows direct connection of burst ROM. The interface can be selected
independently for each area.

An area for which the basic bus interface is designated functions as normal space, an area for
which the DRAM interface is designated functions as DRAM space, an area for which the
synchronous DRAM interface is designated functions as continuous synchronous DRAM space,
and an area for which the burst ROM interface is designated functions as burst ROM space.

The initial state of each area is basic bus interface, 3-state access space. The initial bus width is
selected according to the operating mode.

Note:

The synchronous DRAM interface is not supported in the H8S/2678 Series.

Area 0: Area 0 includes on-chip ROM in expanded mode with on-chip ROM enabled and the
space excluding on-chip ROM is external address space, and in expanded mode with on-chip
ROM disabled, all of area 0 is external address space.

When area 0 external space is accessed, the

&6 signal can be output.

Either basic bus interface or burst ROM interface can be selected for area 0.

Area 1: In externally expanded mode, all of area 1 is external address space.

When area 1 external address space is accessed, the

&6 signal can be output.

Either basic bus interface or burst ROM interface can be selected for area 1.

Areas 2 to 5: In externally expanded mode, areas 2 to 5 are all external address space.

When area 2 to 5 external space is accessed, signals

&6 to &6 can be output.

Basic bus interface, DRAM interface, or synchronous DRAM interface can be selected for areas 2
to 5. With the DRAM interface, signals

&6 to &6 are used as 5$6 signals.

If areas 2 to 5 are designated as continuous DRAM space, large-capacity (e.g. 64-Mbit) DRAM
can be connected. In this case, the

&6 signal is used as the 5$6 signal for the continuous DRAM

space.

If areas 2 to 5 are designated as continuous synchronous DRAM space, large-capacity (e.g. 64-
Mbit) synchronous DRAM can be connected. In this case, the

&6, &6, &6, and &6 pins are

used as the

5$6, &$6, :(, and CLK signals for the continuous synchronous DRAM space. The

2( pin is used as the CKE signal.

Area 6: In externally expanded mode, all of area 6 is external space.

When area 6 external space is accessed, the

&6 signal can be output.

Rev. 2.0, 04/02, page 155 of 906

Only the basic bus interface can be used for area 6.

Area 7: Area 7 includes the on-chip RAM and internal/O registers. In externally expanded mode,
the space excluding the on-chip RAM and internal I/O registers is external address space. The on-
chip RAM is enabled when the RAME bit is set to 1 in the system control register (SYSCR); when
the RAME bit is cleared to 0, the on-chip RAM is disabled and the corresponding addresses are in
external address space.

When area 7 external address space is accessed, the

&6 signal can be output.

Only the basic bus interface can be used for the area 7 memory interface.

6.4.4

Chip Select Signals

This LSI can output chip select signals (

&6 to &6) for areas 0 to 7. The signal outputs low when

the corresponding external space area is accessed. Figure 6.7 shows an example of

&6 to &6

signals output timing.

Enabling or disabling of

&6 to &6 signals output is set by the data direction register (DDR) bit

for the port corresponding to the

&6 to &6 pins.

In expanded mode with on-chip ROM disabled, the

&6 pin is placed in the output state after a

reset. Pins

&6 to &6 are placed in the input state after a reset and so the corresponding DDR bits

should be set to 1 when outputting signals

&6 to &6.

In expanded mode with on-chip ROM enabled, pins

&6 to &6 are all placed in the input state

after a reset and so the corresponding DDR bits should be set to 1 when outputting signals

&6 to

&6.

When areas 2 to 5 are designated as DRAM space, outputs

&6 to &6 are used as 5$6 signals.

When areas 2 to 5 are designated as continuous synchronous DRAM space in the H8S/2678R
Series, outputs

&6, &6, &6, and &6 are used as 5$6, &$6, :(, and CLK signals.

Rev. 2.0, 04/02, page 156 of 906

Bus cycle

Area n external address

Address bus

Figure 6.7

$33 Signal Output Timing (n = 0 to 7)

6.5

Basic Bus Interface

The basic bus interface enables direct connection of ROM, SRAM, and so on.

6.5.1

Data Size and Data Alignment

Data sizes for the CPU and other internal bus masters are byte, word, and longword. The bus
controller has a data alignment function, and when accessing external address space, controls
whether the upper data bus (D15 to D8) or lower data bus (D7 to D0) is used according to the bus
specifications for the area being accessed (8-bit access space or 16-bit access space) and the data
size.

8-Bit Access Space: Figure 6.8 illustrates data alignment control for the 8-bit access space. With
the 8-bit access space, the upper data bus (D15 to D8) is always used for accesses. The amount of
data that can be accessed at one time is one byte: a word access is performed as two byte accesses,
and a longword access, as four byte accesses.

Rev. 2.0, 04/02, page 157 of 906

D15

D8 D7

Upper data bus

Lower data bus

Byte size

Word size

1st bus cycle

2nd bus cycle

Longword
size

1st bus cycle

2nd bus cycle

3rd bus cycle

4th bus cycle

Figure 6.8 Access Sizes and Data Alignment Control (8-Bit Access Space)

16-Bit Access Space: Figure 6.9 illustrates data alignment control for the 16-bit access space.
With the 16-bit access space, the upper data bus (D15 to D8) and lower data bus (D7 to D0) are
used for accesses. The amount of data that can be accessed at one time is one byte or one word,
and a longword access is executed as two word accesses.

In byte access, whether the upper or lower data bus is used is determined by whether the address is
even or odd. The upper data bus is used for an even address, and the lower data bus for an odd
address.

D15

D8 D7

Upper data bus

Lower data bus

Byte size

Word size

1st bus cycle

2nd bus cycle

Longword
size

· Even address

Byte size

· Odd address

Figure 6.9 Access Sizes and Data Alignment Control (16-bit Access Space)

Rev. 2.0, 04/02, page 158 of 906

6.5.2

Valid Strobes

Table 6.3 shows the data buses used and valid strobes for the access spaces.

In a read, the

5' signal is valid for both the upper and the lower half of the data bus. In a write,

the

+:5 signal is valid for the upper half of the data bus, and the /:5 signal for the lower half.

Table 6.3

Data Buses Used and Valid Strobes

Area

Access
Size

Read/
Write

Address

Valid
Strobe

Upper Data Bus
(D15 to D8)

Lower Data Bus
(D7 to D0)

8-bit access

Byte

Read

Valid

Invalid

space

Write

+:5

Hi-Z

16-bit access

Byte

Read

Even

Valid

Invalid

space

Odd

Invalid

Valid

Write

Even

+:5

Valid

Hi-Z

Odd

/:5

Hi-Z

Valid

Word

Read

Valid

Write

+:5

/:5

Valid

Note: Hi-Z: High-impedance state

Invalid: Input state; input value is ignored.

6.5.3

Basic Operation Timing

8-Bit, 2-State Access Space: Figure 6.10 shows the bus timing for an 8-bit, 2-state access space.
When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. The
/:5 pin is always fixed high. Wait states can be inserted.

Rev. 2.0, 04/02, page 167 of 906

Program Wait Insertion: From 0 to 7 wait states can be inserted automatically between the T

state and T

state on an individual area basis in 3-state access space, according to the settings in

WTCRA and WTCRB.

Pin Wait Insertion: Setting the WAITE bit to 1 in BCR enables wait input by means of the
:$,7 pin. When external space is accessed in this state, a program wait is first inserted in
accordance with the settings in WTCRA and WTCRB. If the

:$,7 pin is low at the falling edge

of ø in the last T

or T

state, another T

state is inserted. If the

:$,7 pin is held low, T

states are

inserted until it goes high. This is useful when inserting seven or more T

states, or when changing

the number of T

states to be inserted for different external devices. The WAITE bit setting applies

to all areas. Figure 6.18 shows an example of wait state insertion timing.

The settings after a reset are: 3-state access, insertion of 7 program wait states, and

:$,7 input

disabled.

Rev. 2.0, 04/02, page 170 of 906

Address bus

Bus cycle

Data bus

Write

Data bus

Read
(when
RDNn = 0)

Read data

Write data

Figure 6.20 Example of Timing when Chip Select Assertion Period is Extended

Both extension state T

inserted before the basic bus cycle and extension state T

inserted after the

basic bus cycle, or only one of these, can be specified for individual areas. Insertion or non-
insertion can be specified for the T

state with the upper 8 bits (CSXH7 to CSXH0) in the CSACR

state with the lower 8 bits (CSXT7 to CSXT0).

6.6

DRAM Interface

In this LSI, external space areas 2 to 5 can be designated as DRAM space, and DRAM interfacing
performed. The DRAM interface allows DRAM to be directly connected to this LSI. A DRAM
space of 2, 4, or 8 Mbytes can be set by means of bits RMTS2 to RMTS0 in DRAMCR. Burst
operation is also possible, using fast page mode.

6.6.1

Setting DRAM Space

Areas 2 to 5 are designated as DRAM space by setting bits RMTS2 to RMTS0 in DRAMCR. The
relation between the settings of bits RMTS2 to RMTS0 and DRAM space is shown in table 6.4.

Rev. 2.0, 04/02, page 171 of 906

Possible DRAM space settings are: one area (area 2), two areas (areas 2 and 3), four areas (areas 2
to 5), and continuous area (areas 2 to 5).

Table 6.4

Relation between Settings of Bits RMTS2 to RMTS0 and DRAM Space

RMTS2

RMTS1

RMTS0

Area 5

Area 4

Area 3

Area 2

Normal space

DRAM space

Normal space

DRAM space

Continuous synchronous DRAM space

Mode register settings of synchronous DRAM

Reserved (setting prohibited)

Continuous
DRAM space

Note: Reserved (setting prohibited) in the H8S/2678 Series.

With continuous DRAM space,

5$6 is valid. The bus specifications (bus width, number of wait

states, etc.) for continuous DRAM space conform to the settings for area 2.

6.6.2

Address Multiplexing

With DRAM space, the row address and column address are multiplexed. In address multiplexing,
the size of the shift of the row address is selected with bits MXC2 to MXC0 in DRAMCR. Table
6.5 shows the relation between the settings of MXC2 to MXC0 and the shift size.

The MXC2 bit should be cleared to 0 when the DRAM interface is used.

Rev. 2.0, 04/02, page 172 of 906

Table 6.5

Relation between Settings of Bits MXC2 to MXC0 and Address Multiplexing

DRAMCR

Address Pins

MXC2 MXC1 MXC0 Shift Size

A23

A16 A15 A14 A13 A12 A11 A10 A9

Row

address

8 bits

A23

A16

A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9

9 bits

A23

A16

A15 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9

10 bits

A23

A16

A15 A14 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10

11 bits

A23

A16

A15 A14 A13 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11

Reserved (setting prohibited)

Column

address

A23

A16

A15 A14 A13 A12 A11 A10 A9

Reserved (setting prohibited)

Note: In the H8S/2678 Series, address pins are A23 to A0.

x: Don't care.

6.6.3

Data Bus

If a bit in ABWCR corresponding to an area designated as DRAM space is set to 1, that area is
designated as 8-bit DRAM space; if the bit is cleared to 0, the area is designated as 16-bit DRAM
space. In 16-bit DRAM space,

16-bit configuration DRAM can be connected directly.

In 8-bit DRAM space the upper half of the data bus, D15 to D8, is enabled, while in 16-bit DRAM
space both the upper and lower halves of the data bus, D15 to D0, are enabled.

Access sizes and data alignment are the same as for the basic bus interface: see section 6.5.1, Data
Size and Data Alignment.

Rev. 2.0, 04/02, page 173 of 906

6.6.4

Pins Used for DRAM Interface

Table 6.6 shows the pins used for DRAM interfacing and their functions. Since the

&6 to &6

pins are in the input state after a reset, set the corresponding DDR to 1 when

5$6 to 5$6

signals are output.

Table 6.6

DRAM Interface Pins

Pin

With DRAM
Setting

Name

I/O

Function

+:5

Write enable

Output

Write enable for DRAM space
access

5$6

Row address strobe 2/
row address strobe

Output

Row address strobe when area 2
is designated as DRAM space or
row address strobe when areas
2 to 5 are designated as
continuous DRAM space

5$6

Row address strobe 3

Output

Row address strobe when area 3
is designated as DRAM space

5$6

Row address strobe 4

Output

Row address strobe when area 4
is designated as DRAM space

5$6

Row address strobe 5

Output

Row address strobe when area 5
is designated as DRAM space

8&$6

Upper column address
strobe

Output

Upper column address strobe for
16-bit DRAM space access or
column address strobe for 8-bit
DRAM space access

/&$6

Lower column address
strobe

Output

Lower column address strobe
signal for 16-bit DRAM space
access

Output enable

Output

Output enable signal for DRAM
space access

:$,7

Wait

Input

Wait request signal

A15 to A0

Address pins

Output

Row address/column address
multiplexed output

D15 to D0

Data pins

I/O

Data input/output pins

Rev. 2.0, 04/02, page 179 of 906

6.6.9

Wait Control

There are two ways of inserting wait states in a DRAM access cycle: program wait insertion and
pin wait insertion using the

:$,7 pin.

Wait states are inserted to extend the

&$6 assertion period in a read access to DRAM space, and

to extend the write data setup time relative to the falling edge of

&$6 in a write access.

Program Wait Insertion: When the bit in ASTCR corresponding to an area designated as DRAM
space is set to 1, from 0 to 7 wait states can be inserted automatically between the T

state and T

state, according to the settings in registers WTCRA and WTCRB.

Pin Wait Insertion: When the WAITE bit in BCR is set to 1 and the ASTCR bit is set to 1, wait
input by means of the

:$,7 pin is enabled. When DRAM space is accessed in this state, a

program wait (T

) is first inserted. If the

:$,7 pin is low at the falling edge of ø in the last T

state, another T

state is inserted. If the

:$,7 pin is held low, T

states are inserted until it

goes high.

Figures 6.26 and 6.27 show examples of wait cycle insertion timing in the case of 2-state and 3-
state column address output cycles.

Rev. 2.0, 04/02, page 183 of 906

This LSI

(Address shift size

set to 10 bits)

n (

2-CAS type 16-Mbit DRAM

1-Mbyte

16-bit configuration

10-bit column address

(

)

(

)

A10

D15 to D0

Row address input:
A9 to A0

Column address input:
A9 to A0

Figure 6.29 Example of 2-CAS DRAM Connection

6.6.11

Burst Operation

With DRAM, in addition to full access (normal access) in which data is accessed by outputting a
row address for each access, a fast page mode is also provided which can be used when making
consecutive accesses to the same row address. This mode enables fast (burst) access of data by
simply changing the column address after the row address has been output. Burst access can be
selected by setting the BE bit to 1 in DRAMCR.

Burst Access (Fast Page Mode): Figures 6.30 and 6.31 show the operation timing for burst
access. When there are consecutive access cycles for DRAM space, the

&$6 signal and column

address output cycles (two states) continue as long as the row address is the same for consecutive
access cycles. The row address used for the comparison is set with bits MXC2 to MXC0 in
DRAMCR.

Rev. 2.0, 04/02, page 185 of 906

(

)

Read

Write

(

)

(

)

Data bus

(

)

(

)

Data bus

Address bus

Note: n = 2 to 5

Row address

Column address 1

Column address 2

High

Figure 6.31 Operation Timing in Fast Page Mode

(RAST = 0, CAST = 1)

The bus cycle can also be extended in burst access by inserting wait states. The wait state insertion
method and timing are the same as for full access. For details see section 6.6.9, Wait Control.

RAS Down Mode and RAS Up Mode: Even when burst operation is selected, it may happen that
access to DRAM space is not continuous, but is interrupted by access to another space. In this
case, if the

5$6 signal is held low during the access to the other space, burst operation can be

resumed when the same row address in DRAM space is accessed again.

RAS Down Mode

To select RAS down mode, set both the RCDM bit and the BE bit to 1 in DRAMCR. If access
to DRAM space is interrupted and another space is accessed, the

5$6 signal is held low

during the access to the other space, and burst access is performed when the row address of the
next DRAM space access is the same as the row address of the previous DRAM space access.
Figure 6.32 shows an example of the timing in RAS down mode.

Note, however, that the

5$6 signal will go high if:

a refresh operation is initiated in the RAS down state

self-refreshing is performed

the chip enters software standby mode

the external bus is released

Rev. 2.0, 04/02, page 188 of 906

CAS-before-RAS (CBR) Refreshing: To select CBR refreshing, set the RFSHE bit to 1 in
REFCR.

With CBR refreshing, RTCNT counts up using the input clock selected by bits RTCK2 to RTCK0
in REFCR, and when the count matches the value set in RTCOR (compare match), refresh control
is performed. At the same time, RTCNT is reset and starts counting up again from H'00.
Refreshing is thus repeated at fixed intervals determined by RTCOR and bits RTCK2 to RTCK0.
Set a value in RTCOR and bits RTCK2 to RTCK0 that will meet the refreshing interval
specification for the DRAM used.

When bits RTCK2 to RTCK0 in REFCR are set, RTCNT starts counting up. RTCNT and RTCOR
settings should therefore be completed before setting bits RTCK2 to RTCK0. RTCNT operation is
shown in figure 6.34, compare match timing in figure 6.35, and CBR refresh timing in figure 6.36.

When the CBRM bit in REFCR is cleared to 0, access to external space other than DRAM space is
performed in parallel during the CBR refresh period.

RTCOR

H'00

Refresh request

RTCNT

Figure 6.34 RTCNT Operation

RTCNT

RTCOR

H'00

Refresh request
signal and CMF bit
setting signal

Figure 6.35 Compare Match Timing

Rev. 2.0, 04/02, page 192 of 906

DRAM space write

rc3

rp1

rp2

Software
standby

Note: n = 2 to 5

(

)

(

)

(

)

Data bus

Address bus

Figure 6.40 Example of Timing when Precharge Time after Self-Refreshing Is Extended

by 2 States

Refreshing and All-Module-Clocks-Stopped Mode: In this LSI, if the ACSE bit is set to 1 in
MSTPCRH, and then a SLEEP instruction is executed with the setting for all peripheral module
clocks to be stopped (MSTPCR = H'FFFF) or for operation of the 8-bit timer module alone
(MSTPCR = H'FFFE), and a transition is made to the sleep state, the all-module-clocks-stopped
mode is entered, in which the bus controller and I/O port clocks are also stopped. As the bus
controller clock is also stopped in this mode, CBR refreshing is not executed. If DRAM is
connected externally and DRAM data is to be retained in sleep mode, the ACSE bit must be
cleared to 0 in MSTPCRH.

6.6.13

DMAC and EXDMAC Single Address Transfer Mode and DRAM Interface

When burst mode is selected on the DRAM interface, the

'$&. and ('$&. output timing can

be selected with the DDS and EDDS bits in DRAMCR. When DRAM space is accessed in DMAC
or EXDMAC single address mode at the same time, these bits select whether or not burst access is
to be performed.

Rev. 2.0, 04/02, page 195 of 906

6.7

Synchronous DRAM Interface

In the H8S/2678R Series, external address space areas 2 to 5 can be designated as continuous
synchronous DRAM space, and synchronous DRAM interfacing performed. The synchronous
DRAM interface allows synchronous DRAM to be directly connected to this LSI. A synchronous
DRAM space of up to 8 Mbytes can be set by means of bits RMTS2 to RMTS0 in DRAMCR.
Synchronous DRAM of CAS latency 1 to 4 can be connected.

Note:

The synchronous DRAM interface is not supported in the H8S/2678 Series.

6.7.1

Setting Continuous Synchronous DRAM Space

Areas 2 to 5 are designated as continuous synchronous DRAM space by setting bits RMTS2 to
RMTS0 in DRAMCR. The relation between the settings of bits RMTS2 to RMTS0 and
synchronous DRAM space is shown in table 6.7. Possible synchronous DRAM interface settings
are and continuous area (areas 2 to 5).

Table 6.7

Relation between Settings of Bits RMTS2 to RMTS0 and Synchronous DRAM
Space

RMTS2

RMTS1

RMTS0

Area 5

Area 4

Area 3

Area 2

Normal space

DRAM space

Normal space

DRAM space

Continuous synchronous DRAM space

Mode settings of synchronous DRAM

Reserved (setting prohibited)

Continuous DRAM space

With continuous synchronous DRAM space,

&6, &6, &6 pins are used as 5$6, &$6, :(

signal. The (

2() pin of the synchronous DRAM is used as the CKE signal, and the &6 pin is

used as synchronous DRAM clock (SDRAM

). The bus specifications for continuous

synchronous DRAM space conform to the settings for area 2. The pin wait and program wait for
the continuous synchronous DRAM are invalid.

Commands for the synchronous DRAM can be specified by combining

5$6, &$6, :(, and

address-precharge-setting command (Prechrge-sel) output on the upper column addresses.

Commands that are supported by this LSI are NOP, auto-refresh (REF), self-refresh (SELF), all
bank precharge (PALL), row address strobe bank-active (ACTV), read (READ), write (WRIT),
and mode-register write (MRS). Commands for bank control cannot be used.

Rev. 2.0, 04/02, page 196 of 906

6.7.2

Address Multiplexing

With continuous synchronous DRAM space, the row address and column address are multiplexed.
In address multiplexing, the size of the shift of the row address is selected with bits MXC2 to
MXC0 in DRAMCR. The address-precharge-setting command (Prechrge-sel) can be output on the
upper column address. Table 6.8 shows the relation between the settings of MXC2 to MXC0 and
the shift size. The MXC2 bit should be set to 1 when the synchronous DRAM interface is used.

Table 6.8

Relation between Settings of Bits MXC2 to MXC0 and Address Multiplexing

DRAMCR

Address Pins

MXC2 MXC1 MXC0

Shift

Size

A23 to

A16

A15 A14 A13 A12 A11 A10 A9

Row

address

Reserved (setting prohibited)

8 bits

A23 to

A16

A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9

9 bits

A23 to

A16

A15 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9

10 bits A23 to

A16

A15 A14 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10

11 bits A23 to

A16

A15 A14 A13 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11

Column

address

Reserved (setting prohibited)

A23 to

A16

A23 to

A16

A23 to

A16

A10 A9

A23 to

A16

A11 A10 A9

X: Don't care.

P: Precharge-sel

Rev. 2.0, 04/02, page 197 of 906

6.7.3

Data Bus

If the ABW2 bit in ABWCR corresponding to an area designated as continuous synchronous
DRAM space is set to 1, area 2 to 5 are designated as 8-bit continuous synchronous DRAM space;
if the bit is cleared to 0, the areas are designated as 16-bit continuous synchronous DRAM space.
In 16-bit continuous synchronous DRAM space,

16-bit configuration synchronous DRAM can be

connected directly.

In 8-bit continuous synchronous DRAM space the upper half of the data bus, D15 to D8, is
enabled, while in 16-bit continuous synchronous DRAM space both the upper and lower halves of
the data bus, D15 to D0, are enabled.

Access sizes and data alignment are the same as for the basic bus interface: see section 6.5.1, Data
Size and Data Alignment.

6.7.4

Pins Used for Synchronous DRAM Interface

Table 6.9 shows pins used for the synchronous DRAM interface and their functions. To enable the
synchronous DRAM interface, fix the DCTL pin to 1. Do not vary the DCTL pin during operation.

Since the

&6 to &6 pins are in the input state after a reset, set DDR to 1 when 5$6, &$6, and

:( signals are output. For details, see section 10, I/O Ports. Set the OEE bit of the DRAMCR
register to 1 when the CKE signal is output.

Rev. 2.0, 04/02, page 198 of 906

Table 6.9

Synchronous DRAM Interface Pins

Pin

With
Synchronous
DRAM Setting

Name

I/O

Function

5$6

Row address strobe

Output

Row address strobe when
areas 2 to 5 are designated
as continuous synchronous
DRAM space

&$6

Column address strobe

Output

Column address strobe when
areas 2 to 5 are designated
as continuous synchronous
DRAM space

Write enable

Output

Write enable strobe when
areas 2 to 5 are designated
as continuous synchronous
DRAM space

SDRAM

Clock

Output

Clock only for synchronous
DRAM

(

)

(CKE)

Clock enable

Output

Clock enable signal when
areas 2 to 5 are designated
as continuous synchronous
DRAM space

8&$6

DQMU

Upper data mask enable Output

Upper data mask enable for
16-bit continuous
synchronous DRAM space
access/data mask enable for
8-bit continuous synchronous
DRAM space access

/&$6

DQML

Lower data mask enable Output

Lower data mask enable
signal for 16-bit continuous
synchronous DRAM space
access

A15 to A0

Address pins

Output

Row address/column address
multiplexed output pins

D15 to D0

Data pins

I/O

Data input/output pins

DCTL

Device control pin

Input

Output enable pin for
SDRAM

Rev. 2.0, 04/02, page 199 of 906

6.7.5

Synchronous DRAM Clock

When the DCTL pin is fixed to 1, synchronous clock (SDRAM

) is output from the

&6 pin.

When the frequency multiplication factor of the PLL circuit of this LSI is set to

1 or

SDRAM

is 90° phase shift from

. Therefore, a stable margin is ensured for the synchronous

DRAM that operates at the rising edge of clocks. Figure 6.43 shows the relationship between

and SDRAM

. When the frequency multiplication factor of the PLL circuit is

4, the phase of

SDRAM

and that of

are the same.

When the CLK pin of the synchronous DRAM is directly connected to SDRAM

of this LSI, it is

recommended to set the frequency multiplication factor of the PLL circuit to

1 or

Note:

SDRAM

output timing is shown when the frequency multiplication factor of the PLL

circuit is

1 or

SDRAMø

Tcyc

1/4 Tcyc (90°)

Figure 6.43 Relationship between

and SDRAM

(when PLL frequency multiplication

factor is

1 or

6.7.6

Basic Operation Timing

The four states of the basic timing consist of one T

(precharge cycle) state, one T

(row address

output cycle) state, and the T

and two T

(column address output cycle) states.

When areas 2 to 5 are set for the continuous synchronous DRAM space, settings of the WAITE bit
of BCR, RAST, CAST, RCDM bits of DRAMCR, and the CBRM bit of REFCR are ignored.

Figure 6.44 shows the basic timing for synchronous DRAM.

Rev. 2.0, 04/02, page 201 of 906

6.7.7

CAS Latency Control

CAS latency is controlled by settings of the W22 to W20 bits of WTCRB. Set the CAS latency
count, as shown in table 6.10, by the setting of synchronous DRAM. Depending on the setting, the
CAS latency control cycle (T

) is inserted. WTCRB can be set regardless of the setting of the

AST2 bit of ASTCR. Figure 6.45 shows the CAS latency control timing when synchronous
DRAM of CAS latency 3 is connected.

The initial value of W22 to W20 is H'7. Set the register according to the CAS latency of
synchronous DRAM to be connected.

Table 6.10

Setting CAS Latency

W22

W21

W20

Description

CAS Latency Control Cycle
Inserted

Connect synchronous DRAM of
CAS latency 1

0 state

Connect synchronous DRAM of
CAS latency 2

1 state

Connect synchronous DRAM of
CAS latency 3

2 states

Connect synchronous DRAM of
CAS latency 4

3 states

Reserved (must not used)

Rev. 2.0, 04/02, page 210 of 906

This LSI

(Address shift size set to 8 bits)

(

)

(

)

(

)

16-Mbit synchronous DRAM

1 Mword × 16 bits × 4-bank configuration
8-bit column address

(DQMU)

(DQML)

A10

A12

A11

Notes: 1. Bank control is not available.

2. The CKE and

pins must be fixed to 1 when the power supply is input.

3. The

pin must be fixed to 0 before accessing synchronous DRAM.

A21

A12 (BS0)

A23

A13 (BS1)

(SDRAMø)

CLK

DQML

DQMU

A11

A10

DCTL

I/O PORT

D15 to D0

DQ15 to DQ0

(CKE)

CKE

Row address

input: A11 to A0

Column address

input: A7 to A0

Bank select

address: A13/A12

Figure 6.51 Example of DQMU and DQML Byte Control

6.7.12

Burst Operation

With synchronous DRAM, in addition to full access (normal access) in which data is accessed by
outputting a row address for each access, burst access is also provided which can be used when
making consecutive accesses to the same row address. This access enables fast access of data by
simply changing the column address after the row address has been output. Burst access can be
selected by setting the BE bit to 1 in DRAMCR.

Rev. 2.0, 04/02, page 212 of 906

SDRAM

Read

CKE

PALL

ACTV

READ

NOP

DQMU, DQML

Data bus

Address bus

Row address

Column

address 1

Column address

Column address 2

Precharge-sel

Row address

High

Write

CKE

PALL

ACTV

NOP

WRIT

DQMU, DQML

Data bus

High

Figure 6.52 Operation Timing of Burst Access

(BE = 1, SDWCD = 0, CAS Latency 2)

RAS Down Mode: Even when burst operation is selected, it may happen that access to continuous
synchronous DRAM space is not continuous, but is interrupted by access to another space. In this
case, if the row address active state is held during the access to the other space, the read or write
command can be issued without ACTV command generation similarly to DRAM RAS down
mode.

To select RAS down mode, set the BE bit to 1 in DRAMCR regardless of the RCDM bit settings.
The operation corresponding to DRAM RAS up mode is not supported by this LSI.

Figure 6.53 shows an example of the timing in RAS down mode.

Rev. 2.0, 04/02, page 213 of 906

Note, however, the next continuous synchronous DRAM space access is a full access if:

a refresh operation is initiated in the RAS down state

self-refreshing is performed

the chip enters software standby mode

the external bus is released

the BE bit is cleared to 0

the mode register of the synchronous DRAM is set

There is synchronous DRAM in which time of the active state of each bank is restricted. If it is not
guaranteed that other row address are accessed in a period in which program execution ensures the
value (software standby, sleep, etc.), auto refresh or self refresh must be set, and the restrictions of
the maximum active state time of each bank must be satisfied. When refresh is not used, programs
must be developed so that the bank is not in the active state for more than the specified time.

Address bus

External address

Column address

Column address 2

External address

Row

address

Column

address

Data bus

Continuous synchronous
DRAM space read

External
space read

CKE

High

PALL

ACTV READ

NOP

READ

DQMU, DQML

Precharge-sel

Row

address

Figure 6.53 Example of Operation Timing in RAS Down Mode

(BE = 1, CAS Latency 2)

Rev. 2.0, 04/02, page 214 of 906

6.7.13

Refresh Control

This LSI is provided with a synchronous DRAM refresh control function. Auto refreshing is used.
In addition, self-refreshing can be executed when the chip enters the software standby state.

Refresh control is enabled when any area is designated as continuous synchronous DRAM space
in accordance with the setting of bits RMTS2 to RMTS0 in DRAMCR.

Auto Refreshing: To select auto refreshing, set the RFSHE bit to 1 in REFCR.

With auto refreshing, RTCNT counts up using the input clock selected by bits RTCK2 to RTCK0
in REFCR, and when the count matches the value set in RTCOR (compare match), refresh control
is performed. At the same time, RTCNT is reset and starts counting up again from H'00.
Refreshing is thus repeated at fixed intervals determined by RTCOR and bits RTCK2 to RTCK0.
Set a value in RTCOR and bits RTCK2 to RTCK0 that will meet the refreshing interval
specification for the synchronous DRAM used.

When bits RTCK2 to RTCK0 are set, RTCNT starts counting up. RTCNT and RTCOR settings
should therefore be completed before setting bits RTCK2 to RTCK0. Auto refresh timing is shown
in figure 6.54.

Since the refresh counter operation is the same as the operation in the DRAM interface, see
section 6.6.12, Refresh Control.

When the continuous synchronous DRAM space is set, access to external space other than
continuous synchronous DRAM space cannot be performed in parallel during the auto refresh
period, since the setting of the CBRM bit of REFCR is ignored.

Rev. 2.0, 04/02, page 219 of 906

Rc2

SDRAM

CKE

NOP

PALL

NOP

ACTV

NOP

DQMU, DQML

Data bus

Address bus

Rp1

Rp2

Row address

Column address

Precharge-sel

Row address

Continuous synchronous DRAM space write

Software
standby

Figure 6.58 Example of Timing when Precharge Time after Self-Refreshing Is Extended

by 2 States (TPCS2 to TPCS0 = H'2, TPC1 = 0, TPC0 = 0, CAS Latency 2)

As the bus controller clock is also stopped in this mode, auto refreshing is not executed. If
synchronous DRAM is connected externally and DRAM data is to be retained in sleep mode, the
ACSE bit must be cleared to 0 in MSTPCR.

Software Standby: When a transition is made to normal software standby, the PLL command is
not output. If synchronous DRAM is connected and DRAM data is to be retained in software
standby, self-refreshing must be set.

6.7.14

Mode Register Setting of Synchronous DRAM

To use synchronous DRAM, mode must be set after power-on. to set mode, set the RMTS2 to
RMTS0 bits in DRAMCR to H'5 and enable the synchronous DRAM mode register setting. After
that, access the continuous synchronous DRAM space in bytes. When the value to be set in the
synchronous DRAM mode register is X, value X is set in the synchronous DRAM mode register
by writing to the continuous synchronous DRAM space of address H'400000 + X for 8-bit bus

Rev. 2.0, 04/02, page 226 of 906

6.8

Burst ROM Interface

In this LSI, external space areas 0 and 1 can be designated as burst ROM space, and burst ROM
interfacing performed. The burst ROM space interface enables ROM with burst access capability
to be accessed at high speed.

Areas 1 and 0 can be designated as burst ROM space by means of bits BSRM1 and BSRM0 in
BROMCR. Continuous burst accesses of 4, 8, 16, or 32 words can be performed, according to the
setting of the BSWD11 and BSWD10 bits in BROMCR. From 1 to 8 states can be selected for
burst access.

Settings can be made independently for area 0 and area 1.

In burst ROM interface space, burst access covers only CPU read accesses.

6.8.1

Basic Timing

The number of access states in the initial cycle (full access) on the burst ROM interface is
determined by the basic bus interface settings in ASTCR, ABWCR, WTCRA, WTCRB, and
CSACRH. When area 0 or area 1 is designated as burst ROM interface space, the settings in
RDNCR and CSACRL are ignored.

From 1 to 8 states can be selected for the burst cycle, according to the settings of bits BSTS02 to
BSTS00 and BSTS12 to BSTS10 in BROMCR. Wait states cannot be inserted. Burst access of up
to 32 words is performed, according to the settings of bits BSTS01, BSTS00, BSTS11, and
BSTS10 in BROMCR.

The basic access timing for burst ROM space is shown in figures 6.63 and 6.64.

Rev. 2.0, 04/02, page 229 of 906

6.9

Idle Cycle

6.9.1

Operation

When this LSI accesses external space, it can insert an idle cycle (T

) between bus cycles in the

following three cases: (1) when read accesses in different areas occur consecutively, (2) when a
write cycle occurs immediately after a read cycle, and (3) when a read cycle occurs immediately
after a write cycle (in the H8S/2678R Series, it cannot insert an idle cycle in the condition (3)).
Insertion of a 1-state or 2-state idle cycle can be selected with the IDLC bit in BCR. By inserting
an idle cycle it is possible, for example, to avoid data collisions between ROM, etc., with a long
output floating time, and high-speed memory, I/O interfaces, and so on.

Consecutive Reads in Different Areas: If consecutive reads in different areas occur while the
ICIS1 bit is set to 1 in BCR, an idle cycle is inserted at the start of the second read cycle.

Figure 6.65 shows an example of the operation in this case. In this example, bus cycle A is a read
cycle for ROM with a long output floating time, and bus cycle B is a read cycle for SRAM, each
being located in a different area. In (a), an idle cycle is not inserted, and a collision occurs in bus
cycle B between the read data from ROM and that from SRAM. In (b), an idle cycle is inserted,
and a data collision is prevented.

Address bus

Bus cycle A

Data bus

Bus cycle B

Long output floating time

Data collision

(a) No idle cycle insertion
(ICIS1 = 0)

Address bus

Bus cycle A

Data bus

Bus cycle B

(b) Idle cycle insertion
(ICIS1 = 1, initial value)

(area A)

(area B)

(area A)

(area B)

Idle cycle

Figure 6.65 Example of Idle Cycle Operation

(Consecutive Reads in Different Areas)

Rev. 2.0, 04/02, page 230 of 906

Write after Read: If an external write occurs after an external read while the ICIS0 bit is set to 1
in BCR, an idle cycle is inserted at the start of the write cycle.

Figure 6.66 shows an example of the operation in this case. In this example, bus cycle A is a read
cycle for ROM with a long output floating time, and bus cycle B is a CPU write cycle. In (a), an
idle cycle is not inserted, and a collision occurs in bus cycle B between the read data from ROM
and the CPU write data. In (b), an idle cycle is inserted, and a data collision is prevented.

Address bus

Bus cycle A

Data bus

Bus cycle B

Long output floating time

Data collision

(a) No idle cycle insertion

(ICIS0 = 0)

Address bus

Bus cycle A

Data bus

Bus cycle B

(b) Idle cycle insertion
(ICIS0 = 1, initial value)

(area A)

(area B)

(area A)

(area B)

Idle cycle

Figure 6.66 Example of Idle Cycle Operation (Write after Read)

Read after Write: If an external read occurs after an external write while the ICIS2 bit is set to 1
in BCR, an idle cycle is inserted at the start of the read cycle.

Figure 6.67 shows an example of the operation in this case. In this example, bus cycle A is a CPU
write cycle and bus cycle B is a read cycle from an external device. In (a), an idle cycle is not
inserted, and a collision occurs in bus cycle B between the CPU write data and read data from an
external device. In (b), an idle cycle is inserted, and a data collision is prevented.

Note:

In the H8S/2678 Series, an idle cycle cannot be inserted in the condition (3).

Rev. 2.0, 04/02, page 232 of 906

Address bus

Bus cycle A

Bus cycle B

Overlap period between

(area B)

and

may occur

(a) No idle cycle insertion
(ICIS1 = 0)

Address bus

Idle cycle

Bus cycle A

Bus cycle B

(b) Idle cycle insertion
(ICIS1 = 1, initial value)

(area A)

(area B)

(area A)

(area B)

Figure 6.68 Relationship between Chip Select (

$) and Read (#

Idle Cycle in Case of DRAM Space Access after Normal Space Access: In a DRAM space
access following a normal space access, the settings of bits ICIS2 (not available in the H8S/2678
Series), ICIS1, ICIS0, and IDLC in BCR are valid. However, in the case of consecutive reads in
different areas, for example, if the second read is a full access to DRAM space, only a T

cycle is

inserted, and a T

cycle is not. The timing in this case is shown in figure 6.69.

Address bus

External read

Data bus

DRAM space read

Figure 6.69 Example of DRAM Full Access after External Read

(CAST = 0)

Rev. 2.0, 04/02, page 234 of 906

Idle Cycle in Case of Continuous Synchronous DRAM Space Access after Normal Space
Access: In a continuous synchronous DRAM space access following a normal space access, the
settings of bits ICIS2, ICIS1, ICIS0, and IDLC in BCR are valid. However, in the case of
consecutive reads in different areas, for example, if the second read is a full access to continuous
synchronous DRAM space, only Tp cycle is inserted, and Ti cycle is not. The timing in this case
is shown in figure 6.72.

Note:

In the H8S/2678 Series, the synchronous DRAM interface is not supported.

Address bus

Column address

Row

address

Row

address

Column

address

Data bus

External space read

Synchronous DRAM space read

CKE

PALL ACTV

NOP

READ

DQMU, DQML

Precharge-sel

Figure 6.72 Example of Synchronous DRAM Full Access after External Read

(CAS Latency 2)

In burst access in RAS down mode, the settings of bits ICIS2, ICIS1, ICIS0, and IDLC are valid
and an idle cycle is inserted. However, in read access, note that the timings of DQMU and DQML
differ according to the settings of the IDLC bit. The timing in this case is illustrated in figures
6.73 and 6.74. In write access, DQMU and DQML are not in accordance with the settings of the
IDLC bit. The timing in this case is illustrated in figure 6.75.

Rev. 2.0, 04/02, page 237 of 906

Address bus

Idle cycle

Data bus

Continuous synchronous
DRAM space read

External space read

Continuous synchronous
DRAM space write

CKE

High

PALL

ACTV READ

NOP

WRIT

DQMU, DQML

Precharge-sel

Row

address

Row

address

Column

address

External address

Column address 1

Column address 2

Figure 6.75 Example of Idle Cycle Operation in RAS Down Mode

(Write after Read) (IDLC = 0, CAS Latency 2)

Idle Cycle in Case of Normal Space Access after DRAM Space Access:

Normal space access after DRAM space read access

While the DRMI bit is cleared to 0 in DRACCR, idle cycle insertion after DRAM space access is
disabled. Idle cycle insertion after DRAM space access can be enabled by setting the DRMI bit to
1. The conditions and number of states of the idle cycle to be inserted are in accordance with the
settings of bits ICIS1, ICIS0, and IDLC in BCR are valid. Figures 6.76 and 6.77 show examples of
idle cycle operation when the DRMI bit is set to 1.

When the DRMI bit is cleared to 0, an idle cycle is not inserted after DRAM space access even if
bits ICIS1 and ICIS0 are set to 1.

Rev. 2.0, 04/02, page 239 of 906

Normal space access after DRAM space write access

While the ICIS2 bit is set to 1 in BCR (there is no ICRS2 bit in the H8S/2678 Series, therefore this
setting cannot be made) and a normal space read access occurs after DRAM space write access,
idle cycle is inserted in the first read cycle. The number of states of the idle cycle to be inserted is
in accordance with the setting of the IDLC bit. It does not depend on the DRMI bit in DRACCR.
Figure 6.78 shows an example of idle cycle operation when the ICIS2 bit is set to 1.

Address bus

External space read

Idle cycle

Data bus

DRAM space read

Figure 6.78 Example of Idle Cycle Operation after DRAM Write Access

(IDLC = 0, ICIS1 = 0, RAST = 0, CAST = 0)

Idle Cycle in Case of Normal Space Access After Continuous Synchronous DRAM Space
Access:

Note: In the H8S/2678 Series, the synchronous DRAM interface is not supported.

Normal space access after a continuous synchronous DRAM space read access

While the DRMI bit is cleared to 0 in DRACCR, idle cycle insertion after continuous synchronous
DRAM space read access is disabled. Idle cycle insertion after continuous synchronous DRAM
space read access can be enabled by setting the DRMI bit to 1. The conditions and number of
states of the idle cycle to be inserted are in accordance with the settings of bits ICIS1, ICIS0, and
IDLC in RCR. Figure 6.79 shows an example of idle cycle operation when the DRMI bit is set to
1. When the DRMI bit is cleared to 0, an idle cycle is not inserted after continuous synchronous
DRAM space read access even if bits ICIS1 and ICIS0 are set to 1.

Rev. 2.0, 04/02, page 240 of 906

Address bus

Idle cycle

Data bus

Continuous synchronous
DRAM space read

External space read

Continuous synchronous
DRAM space read

CKE

High

PALL

ACTV READ

NOP

READ

DQMU, DQML

Precharge-sel

External address

Column address 1

Column address 2

Row

address

Row

address

Column

address

Figure 6.79 Example of Idle Cycle Operation after Continuous Synchronous DRAM Space

Read Access (Read between Different Area) (IDLC = 0, CAS Latency 2)

Normal space access after a continuous synchronous DRAM space write access

If a normal space read cycle occurs after a continuous synchronous DRAM space write access
while the ICIS2 bit is set to 1 in BCR, idle cycle is inserted at the start of the read cycle. The
number of states of the idle cycle to be inserted is in accordance with the setting of bit IDLC. It is
not in accordance with the DRMI bit in DRACCR.

Figure 6.80 shows an example of idle cycle operation when the ICIS2 bit is set to 1.

Rev. 2.0, 04/02, page 242 of 906

Table 6.11

Idle Cycles in Mixed Accesses to Normal Space and DRAM Continuous
Synchronous DRAM Space

Previous Access

Next Access

ICIS2

ICIS1

ICIS0

DRMI

IDLC

Idle cycle

Disabled

1 state inserted

Normal space read
(different area)

2 states inserted

Disabled

1 state inserted

DRAM/continuous
synchronous DRAM

space read

2 states inserted

Disabled

1 state inserted

Normal space write

2 states inserted

Disabled

1 state inserted

Normal space read

DRAM/continuous
synchronous DRAM

space write

2 states inserted

Disabled

1 state inserted

Normal space read

2 states inserted

Disabled

1 state inserted

DRAM/continuous
synchronous DRAM

space read

2 states inserted

Disabled

1 state inserted

Normal space write

2 states inserted

Disabled

1 state inserted

DRAM/continuous

synchronous DRAM
space read

DRAM/continuous
synchronous DRAM

space write

2 states inserted

Disabled

1 state inserted

Normal space read

2 states inserted

Disabled

1 state inserted

Normal space write

DRAM/continuous
synchronous DRAM

space read

2 states inserted

Rev. 2.0, 04/02, page 243 of 906

Previous Access

Next Access

ICIS2

ICIS1

ICIS0

DRMI

IDLC

Idle cycle

Disabled

1 state inserted

Normal space read

2 states inserted

Disabled

1 state inserted

DRAM/continuous
synchronous DRAM
space write

DRAM/continuous
synchronous DRAM
space read

2 states inserted

Note:

In the H8S/2678 Series, the synchronous DRAM interface is not supported.

Setting the DRMI bit in DRACCR to 1 enables an idle cycle to be inserted in the case of
consecutive read and write operations in DRAM/continuous synchronous DRAM space burst
access. Figures 6.81 and 6.82 show an example of the timing for idle cycle insertion in the case of
consecutive read and write accesses to DRAM/continuous synchronous DRAM space.

Address bus

Idle cycle

Data bus

DRAM space write

DRAM space read

(

)

(

)

(

)

Note: n = 2 to 5

Figure 6.81 Example of Timing for Idle Cycle Insertion in Case of Consecutive Read and

Write Accesses to DRAM Space in RAS Down Mode

Rev. 2.0, 04/02, page 245 of 906

6.9.2

Pin States in Idle Cycle

Table 6.12 shows the pin states in an idle cycle.

Table 6.12

Pin States in Idle Cycle

Pins

Pin State

A23 to A0

Contents of following bus cycle

D15 to D0

High impedance

&6Q

(n = 7 to 0)

High

8&$6

/&$6

High

(

)

High

+:5

/:5

High

'$&.Q

(n = 1, 0)

High

('$&.Q

(n = 3 to 0)

High

Notes: 1. Remains low in DRAM space RAS down mode.

2. Remains low in a DRAM space refresh cycle.

6.10

Write Data Buffer Function

This LSI has a write data buffer function for the external data bus. Using the write data buffer
function enables external writes and DMA single address mode transfers to be executed in parallel
with internal accesses. The write data buffer function is made available by setting the WDBE bit
to 1 in BCR.

Figure 6.83 shows an example of the timing when the write data buffer function is used. When this
function is used, if an external write or DMA single address mode transfer continues for two states
or longer, and there is an internal access next, an external write only is executed in the first state,
but from the next state onward an internal access (on-chip memory or internal I/O register
read/write) is executed in parallel with the external write rather than waiting until it ends.

Rev. 2.0, 04/02, page 246 of 906

Internal address bus

A23 to A0

External write cycle

On-chip memory read

Internal I/O register read

Internal read signal

D15 to D0

External address

Internal memory

External space
write

Internal I/O register address

Figure 6.83 Example of Timing when Write Data Buffer Function is Used

6.11

Bus Release

This LSI can release the external bus in response to a bus request from an external device. In the
external bus released state, internal bus masters except the EXDMAC continue to operate as long
as there is no external access. If any of the following requests are issued in the external bus
released state, the

%5(42 signal can be driven low to output a bus request externally.

When an internal bus master wants to perform an external access

When a refresh request is generated

When a SLEEP instruction is executed to place the chip in software standby mode or all-
module-clocks-stopped mode

6.11.1

Operation

In externally expanded mode, the bus can be released to an external device by setting the BRLE
bit to 1 in BCR. Driving the

%5(4 pin low issues an external bus request to this LSI. When the

%5(4 pin is sampled, at the prescribed timing the %$&. pin is driven low, and the address bus,
data bus, and bus control signals are placed in the high-impedance state, establishing the external
bus released state.

Rev. 2.0, 04/02, page 247 of 906

In the external bus released state, internal bus masters except the EXDMAC can perform accesses
using the internal bus. When an internal bus master wants to make an external access, it
temporarily defers initiation of the bus cycle, and waits for the bus request from the external bus
master to be canceled. If a refresh request is generated in the external bus released state, or if a
SLEEP instruction is executed to place the chip in software standby mode or all-module-clocks-
stopped mode, refresh control and software standby or all-module-clocks-stopped control is
deferred until the bus request from the external bus master is canceled.

If the BREQOE bit is set to 1 in BCR, the

%5(42 pin can be driven low when any of the

following requests are issued, to request cancellation of the bus request externally.

When an internal bus master wants to perform an external access

When a refresh request is generated

When a SLEEP instruction is executed to place the chip in software standby mode or all-
module-clocks-stopped mode

When the

%5(4 pin is driven high, the %$&. pin is driven high at the prescribed timing and the

external bus released state is terminated.

If an external bus release request and external access occur simultaneously, the order of priority is
as follows:

(High) External bus release > External access by internal bus master (Low)

If a refresh request and external bus release request occur simultaneously, the order of priority is
as follows:

(High) Refresh > External bus release (Low)

Rev. 2.0, 04/02, page 250 of 906

Figure 6.85 shows the timing for transition to the bus released state with the synchronous DRAM
interface.

CPU
cycle

External bus released state

External space read

Address bus

DQMU, DQML

High-Z

NOP

PALL

NOP

[1]

[2]

[3]

[5]

[4]

[6]

[8]

[7]

[9]

[1] Low level of BREQ signal is sampled at rise of f.
[2] PLL command is issued.
[3] Bus control signal returns to be high at end of external space access cycle.
At least one state from sampling of BREQ signal.
[4] BACK signal is driven low, releasing bus to external bus master..
[5] BREQ signal state is also sampled in external bus released state.
[6] High level of BREQ signal is sampled.
[7] BACK signal is driven high, ending external bus release cycle.
[8] When there is external access or refresh request of internal bus master during
external bus release while the BREQOE bit is set to 1, BREQO signal goes low.
[9] BREQO signal goes high 1.5 states after rising edge of BACK signal. If BREQO
signal is asserted because of auto-refreshing request, it retains low until auto-refresh cycle starts up.

Data bus

High-Z

Precharge-sel

High-Z

CKE

High-Z

SDRAMø

Row

address

Figure 6.85 Bus Release State Transition Timing when Synchronous DRAM Interface

Rev. 2.0, 04/02, page 251 of 906

6.12

Bus Arbitration

This LSI has a bus arbiter that arbitrates bus mastership operations (bus arbitration).

There are four bus masters--the CPU, DTC, DMAC, and EXDMAC--that perform read/write
operations when they have possession of the bus. Each bus master requests the bus by means of a
bus request signal. The bus arbiter determines priorities at the prescribed timing, and permits use
of the bus by means of a bus request acknowledge signal. The selected bus master then takes
possession of the bus and begins its operation.

6.12.1

Operation

The bus arbiter detects the bus masters' bus request signals, and if the bus is requested, sends a bus
request acknowledge signal to the bus master. If there are bus requests from more than one bus
master, the bus request acknowledge signal is sent to the one with the highest priority. When a bus
master receives the bus request acknowledge signal, it takes possession of the bus until that signal
is canceled.

The order of priority of the bus mastership is as follows:

(High) EXDMAC > DMAC > DTC > CPU (Low)

An internal bus access by internal bus masters except the EXDMAC and external bus release, a
refresh when the CBRM bit is 0, and an external bus access by the EXDMAC can be executed in
parallel.

If an external bus release request, a refresh request, and an external access by an internal bus
master occur simultaneously, the order of priority is as follows:

(High) Refresh > EXDMAC > External bus release (Low)

(High) External bus release > External access by internal bus master except EXDMAC (Low)

As a refresh when the CBRM bit in REFCR is cleared to 0 and an external access other than to
DRAM space by an internal bus master can be executed simultaneously, there is no relative order
of priority for these two operations.

6.12.2

Bus Transfer Timing

Even if a bus request is received from a bus master with a higher priority than that of the bus
master that has acquired the bus and is currently operating, the bus is not necessarily transferred
immediately. There are specific timings at which each bus master can relinquish the bus.

Rev. 2.0, 04/02, page 252 of 906

CPU: The CPU is the lowest-priority bus master, and if a bus request is received from the DTC,
DMAC, or EXDMAC, the bus arbiter transfers the bus to the bus master that issued the request.
The timing for transfer of the bus is as follows:

The bus is transferred at a break between bus cycles. However, if a bus cycle is executed in
discrete operations, as in the case of a longword-size access, the bus is not transferred between
the component operations.

With bit manipulation instructions such as BSET and BCLR, the sequence of operations is:
data read (read), relevant bit manipulation operation (modify), write-back (write). The bus is
not transferred during this read-modify-write cycle, which is executed as a series of bus cycles.

If the CPU is in sleep mode, the bus is transferred immediately.

DTC: The DTC sends the bus arbiter a request for the bus when an activation request is generated.

The DTC can release the bus after a vector read, a register information read (3 states), a single data
transfer, or a register information write (3 states). It does not release the bus during a register
information read (3 states), a single data transfer, or a register information write (3 states).

DMAC: The DMAC sends the bus arbiter a request for the bus when an activation request is
generated.

In the case of an external request in short address mode or normal mode, and in cycle steal mode,
the DMAC releases the bus after a single transfer.

In block transfer mode, it releases the bus after transfer of one block, and in burst mode, after
completion of the transfer. However, in the event of an EXDMAC or external bus release request,
which have a higher priority than the DMAC, the bus may be transferred to the bus master even if
block or burst transfer is in progress.

EXDMAC: The EXDMAC sends the bus arbiter a request for the bus when an activation request
is generated.

As the EXDMAC is used exclusively for transfers to and from the external bus, if the bus is
transferred to the EXDMAC, internal accesses by other internal bus masters are still executed in
parallel.

In normal transfer mode or cycle steal transfer mode, the EXDMAC releases the bus after a single
transfer.

In block transfer mode, it releases the bus after transfer of one block, and in burst transfer mode,
after completion of the transfer. By setting the BGUP bit to 1 in EDMDR, it is possible to specify
temporary release of the bus in the event of an external access request from an internal bus master.
For details see section 8, EXDMA Controller.

Rev. 2.0, 04/02, page 253 of 906

External Bus Release: When the

%5(4 pin goes low and an external bus release request is issued

while the BRLE bit is set to 1 in BCR, a bus request is sent to the bus arbiter.

External bus release can be performed on completion of an external bus cycle.

6.13

Bus Controller Operation in Reset

In a reset, this LSI, including the bus controller, enters the reset state immediately, and any
executing bus cycle is aborted.

6.14

Usage Notes

6.14.1

External Bus Release Function and All-Module-Clocks-Stopped Mode

In this LSI, if the ACSE bit is set to 1 in MSTPCR, and then a SLEEP instruction is executed with
the setting for all peripheral module clocks to be stopped (MSTPCR = H'FFFF) or for operation of
the 8-bit timer module alone (MSTPCR = H'FFFE), and a transition is made to the sleep state, the
all-module-clocks-stopped mode is entered in which the clock is also stopped for the bus
controller and I/O ports. In this state, the external bus release function is halted. To use the
external bus release function in sleep mode, the ACSE bit in MSTPCR must be cleared to 0.
Conversely, if a SLEEP instruction to place the chip in all-module-clocks-stopped mode is
executed in the external bus released state, the transition to all-module-clocks-stopped mode is
deferred and performed until after the bus is recovered.

6.14.2

External Bus Release Function and Software Standby

In this LSI, internal bus master operation does not stop even while the bus is released, as long as
the program is running in on-chip ROM, etc., and no external access occurs. If a SLEEP
instruction to place the chip in software standby mode is executed while the external bus is
released, the transition to software standby mode is deferred and performed after the bus is
recovered.

Also, since clock oscillation halts in software standby mode, if

%5(4 goes low in this mode,

indicating an external bus release request, the request cannot be answered until the chip has
recovered from the software standby state.

6.14.3

External Bus Release Function and CBR Refreshing/Auto Refreshing

CBR refreshing/auto refreshing cannot be executed while the external bus is released. Setting the
BREQOE bit to 1 in BCR beforehand enables the

%5(42 signal to be output when a CBR

refresh/auto refresh request is issued.

Note: In the H8S/2678 Series, the auto refresh control is not supported.

Rev. 2.0, 04/02, page 254 of 906

6.14.4

%5(42

%5(42 Output Timing

When the BREQOE bit is set to 1 and the

%5(42 signal is output, %5(42 may go low before

the

%$&. signal.

This will occur if the next external access request or CBR refresh request occurs while internal bus
arbitration is in progress after the chip samples a low level of

%5(4.

6.14.5

Notes on Usage of the Synchronous DRAM

Setting of Synchronous DRAM Interface: The DCTL pin must be fixed to 1 to enable the
synchronous DRAM interface. Do not change the DCTL pin during operation.

Connection Clock: Be sure to set the clock to be connected to the synchronous DRAM to
SDRAM

:$,

:$,77 Pin: In the continuous synchronous DRAM space, insertion of the wait state by the :$,7
pin is disabled regardless of the setting of the WAITE bit in BCR.

Bank Control: This LSI cannot carry out the bank control of the synchronous DRAM. All banks
are selected.

Burst Access: The burst read/burst write mode of the synchronous DRAM is not supported.
When setting the mode register of the synchronous DRAM, set to the burst read/single write and
set the burst length to 1.

CAS Latency: When connecting a synchronous DRAM having CAS latency of 1, set the BE bit
to 0 in the DRAMCR.

Rev. 2.0, 04/02, page 255 of 906

Section 7 DMA Controller (DMAC)

This LSI has a built-in DMA controller (DMAC) which can carry out data transfer on up to 4
channels.

7.1

Features

Selectable as short address mode or full address mode

Short address mode

Maximum of 4 channels can be used

Dual address mode or single address mode can be selected

In dual address mode, one of the two addresses, transfer source and transfer destination, is
specified as 24 bits and the other as 16 bits

In single address mode, transfer source or transfer destination address only is specified as 24
bits

In single address mode, transfer can be performed in one bus cycle

Choice of sequential mode, idle mode, or repeat mode for dual address mode and single
address mode

Full address mode

Maximum of 2 channels can be used

Transfer source and transfer destination addresses as specified as 24 bits

Choice of normal mode or block transfer mode

16-Mbyte address space can be specified directly

Byte or word can be set as the transfer unit

Activation sources: internal interrupt, external request, auto-request (depending on transfer
mode)

Six 16-bit timer-pulse unit (TPU) compare match/input capture interrupts

Serial communication interface (SCI_0, SCI_1) transmission complete interrupt, reception
complete interrupt

A/D converter conversion end interrupt

External request

Auto-request

Module stop mode can be set

DMAS260A_010020020400

Rev. 2.0, 04/02, page 257 of 906

7.2

Input/Output Pins

Table 7.1 shows the DMAC pin configuration.

Table 7.1

Pin Configuration

Channel

Pin Name

Symbol

I/O

Function

DMA request 0

'5(4

Input

Channel 0 external request

DMA transfer acknowledge 0

'$&.

Output

Channel 0 single address
transfer acknowledge

DMA transfer end 0

7(1'

Output

Channel 0 transfer end

DMA request 1

'5(4

Input

Channel 1 external request

DMA transfer acknowledge 1

'$&.

Output

Channel 1 single address
transfer acknowledge

DMA transfer end 1

7(1'

Output

Channel 1 transfer end

7.3

Register Descriptions

Memory address register_0AH (MAR_0AH)

Memory address register_0AL (MAR_0AL)

I/O address register_0A (IOAR_0A)

Transfer count register_0A (ECTR_0A)

Memory address register_0BH (MAR_0BH)

Memory address register_0BL (MAR_0BL)

I/O address register_0B (IOAR_0B)

Transfer count register_0B (ECTR_0B)

Memory address register_1AH (MAR_1AH)

Memory address register_1AL (MAR_1AL)

I/O address register_1A (IOAR_1A)

Transfer count register_1A (ETCR_1B)

Memory address register_1BH (MAR_1BH)

Memory address register_1BL (MAR_1BL)

I/O address register_1B (IOAR_1B)

Transfer count register_1B (ETCR_1B)

DMA control register_0A (DMACR_0A)

DMA control register_0B (DMACR_0B)

DMA control register_1A (DMACR_1A)

DMA control register_1B (DMACR_1B)

Rev. 2.0, 04/02, page 258 of 906

DMA band control register H (DMABCRH)

DMA band control register L (DMABCRL)

DMA write enable register (DMAWER)

DMA terminal control register (DMATCR)

The functions of MAR, IOAR, ETCR, DMACR, and DMABCR differ according to the transfer
mode (short address mode or full address mode). The transfer mode can be selected by means of
the FAE1 and FAE0 bits in DMABCRH. The register configurations for short address mode and
full address mode of channel 0 are shown in table 7.2.

Table 7.2

Short Address Mode and Full Address Mode (Channel 0)

FAE0

Description

Short address mode specified (channels 0A and 0B operate independently)

Channel 0A

MAR_0AH

Specifies transfer source/transfer destination address

Specifies transfer destination/transfer source address

Specifies number of transfers

Specifies transfer size, mode, activation source.

Specifies transfer source/transfer destination address

Specifies transfer destination/transfer source address

Specifies number of transfers

Specifies transfer size, mode, activation source.

IOAR_0A

ETCR_0A

DMACR_0A

Channel 0B

MAR_0BH

MAR_0AL

MAR_0BL

IOAR_0B

ETCR_0B

DMACR_0B

Full address mode specified (channels 0A and 0B operate in combination as channel 0)

Channel 0

MAR_0AH

Specifies transfer source address

Specifies transfer destination address

Not used

Specifies number of transfers

Specifies number of transfers (used in block transfer

mode only)

Specifies transfer size, mode, activation source, etc.

IOAR_0A

ETCR_0A

DMACR_0A

MAR_0BH

MAR_0AL

MAR_0BL

IOAR_0B

ETCR_0B

DMACR_0B

7.3.1

Memory Address Registers (MARA and MARB)

MAR is a 32-bit readable/writable register that specifies the source address (transfer source
address) or destination address (transfer destination address). MAR consists of two 16-bit registers
MARH and MARL. The upper 8 bits of MARH are reserved: they are always read as 0, and
cannot be modified.

The DMA has four MAR registers: MAR_0A in channel 0 (channel 0A), MAR_0B in channel 0
(channel 0B), MAR_1A in channel 1 (channel 1A), and MAR_1B in channel 1 (channel 1B).

Rev. 2.0, 04/02, page 259 of 906

MAR is not initialized by a reset or in standby mode.

Short Address Mode: In short address mode, MARA and MARB operate independently.
Whether MAR functions as the source address register or as the destination address register can be
selected by means of the DTDIR bit in DMACR.

MAR is incremented or decremented each time a byte or word transfer is executed, so that the
address specified by MAR is constantly updated.

Full Address Mode: In full address mode, MARA functions as the source address register, and
MARB as the destination address register.

MAR is incremented or decremented each time a byte or word transfer is executed, so that the
source or destination address is constantly updated.

7.3.2

I/O Address Registers (IOARA and IOARB)

IOAR is a 16-bit readable/writable register that specifies the lower 16 bits of the source address
(transfer source address) or destination address (transfer destination address). The upper 8 bits of
the transfer address are automatically set to H'FF.

The DMA has four IOAR registers: IOAR_0A in channel 0 (channel 0A), IOAR_0B in channel 0
(channel 0B), IOAR_1A in channel 1 (channel 1A), and IOAR_1B in channel 1 (channel 1B).

Whether IOAR functions as the source address register or as the destination address register can
be selected by means of the DTDIR bit in DMACR.

IOAR is not incremented or decremented each time a data transfer is executed, so the address
specified by IOAR is fixed.

IOAR is not initialized by a reset or in standby mode.

IOAR can be used in short address mode but not in full address mode.

7.3.3

Execute Transfer Count Registers (ETCRA and ETCRB)

ETCR is a 16-bit readable/writable register that specifies the number of transfers.

The DMA has four ETCR registers: ETCR_0A in channel 0 (channel 0A), ETCR_0B in channel 0
(channel 0B), ETCR_1A in channel 1 (channel 1A), and ETCR_1B in channel 1 (channel 1B).

ETCR is not initialized by a reset or in standby mode.

Rev. 2.0, 04/02, page 260 of 906

Short Address Mode: The function of ETCR in sequential mode and idle mode differs from that
in repeat mode.

In sequential mode and idle mode, ETCR functions as a 16-bit transfer counter. ETCR is
decremented by 1 each time a transfer is performed, and when the count reaches H'00, the DTE bit
in DMABCRL is cleared, and transfer ends.

In repeat mode, ETCRL functions as an 8-bit transfer counter and ETCRH functions as a transfer
count holding register. ETCRL is decremented by 1 each time a transfer is performed, and when
the count reaches H'00, ETCRL is loaded with the value in ETCRH. At this point, MAR is
automatically restored to the value it had when the count was started. The DTE bit in DMABCRL
is not cleared, and so transfers can be performed repeatedly until the DTE bit is cleared by the
user.

Full Address Mode: The function of ETCR in normal mode differs from that in block transfer
mode.

In normal mode, ETCRA functions as a 16-bit transfer counter. ETCRA is decremented by 1 each
time a data transfer is performed, and transfer ends when the count reaches H'0000. ETCRB is not
used in normal mode.

In block transfer mode, ETCRAL functions as an 8-bit block size counter and ETCRAH functions
as a block size holding register. ETCRAL is decremented by 1 each time a 1-byte or 1-word
transfer is performed, and when the count reaches H'00, ETCRAL is loaded with the value in
ETCRAH. So by setting the block size in ETCRAH and ETCRAL, it is possible to repeatedly
transfer blocks consisting of any desired number of bytes or words.

In block transfer mode, ETCRB functions as a 16-bit block transfer counter. ETCRB is
decremented by 1 each time a block is transferred, and transfer ends when the count reaches
H'0000.

Rev. 2.0, 04/02, page 261 of 906

7.3.4

DMA Control Registers (DMACRA and DMACRB)

DMACR controls the operation of each DMAC channel.

The DMA has four DMACR registers: DMACR_0A in channel 0 (channel 0A), DMACR_0B in
channel 0 (channel 0B), DMACR_1A in channel 1 (channel 1A), and DMACR_1B in channel 1
(channel 1B).

In short address mode, channels A and B operate independently, and in full address mode,
channels A and B operate together. The bit functions in the DMACR registers differ according to
the transfer mode.

Short Address Mode:

DMACR_0A, DMACR_0B, DMACR_1A, and DMARC_1B

Bit

Bit Name

Initial Value

R/W

Description

DTSZ

R/W

Data Transfer Size

Selects the size of data to be transferred at one
time.

0: Byte-size transfer

1: Word-size transfer

DTID

R/W

Data Transfer Increment/Decrement

Selects incrementing or decrementing of MAR
after every data transfer in sequential mode or
repeat mode. In idle mode, MAR is neither
incremented nor decremented.

0: MAR is incremented after a data transfer

(Initial value)

When DTSZ = 0, MAR is incremented by 1

When DTSZ = 1, MAR is incremented by 2

1: MAR is decremented after a data transfer

When DTSZ = 0, MAR is decremented by 1

When DTSZ = 1, MAR is decremented by 2

Rev. 2.0, 04/02, page 262 of 906

Bit

Bit Name

Initial Value

R/W

Description

RPE

R/W

Repeat Enable

Used in combination with the DTIE bit in
DMABCR to select the mode (sequential, idle,
or repeat) in which transfer is to be performed.

When DTIE = 0 (no transfer end interrupt)

0: Transfer in sequential mode

1: Transfer in repeat mode

When DTIE = 1 (with transfer end interrupt)

0: Transfer in sequential mode

1: Transfer in idle mode

DTDIR

R/W

Data Transfer Direction

Used in combination with the SAE bit in
DMABCR to specify the data transfer direction
(source or destination). The function of this bit is
therefore different in dual address mode and
single address mode.

When SAE = 0

0: Transfer with MAR as source address and

'$&.

pin as write strobe

1: Transfer with

'$&.

pin as read strobe and

MAR as destination address

When SAE = 1

0: Transfer with MAR as source address and
IOAR as destination address

1: Transfer with IOAR as source address and
MAR as destination address

DTF3

DTF2

DTF1

DTF0

R/W

Data Transfer Factor 3 to 0

These bits select the data transfer factor
(activation source). There are some differences
in activation sources for channel A and channel
B.

Rev. 2.0, 04/02, page 264 of 906

Bit

Bit Name

Initial Value

R/W

Description

Channel B

0000: Setting prohibited

0001: Activated by A/D converter conversion
end interrupt

0010: Activated by

'5(4

pin rising edge input

(

detected as a low level in the first transfer after

transfer is enabled)

0011: Activated by

'5(4

pin low-level input

0100: Activated by SCI channel 0 transmission
complete interrupt

0101: Activated by SCI channel 0 reception
complete interrupt

0110: Activated by SCI channel 1 transmission
complete interrupt

0111: Activated by SCI channel 1 reception
complete interrupt

1000: Activated by TPU channel 0 compare
match/input capture A interrupt

1001: Activated by TPU channel 1 compare
match/input capture A interrupt

1010: Activated by TPU channel 2 compare
match/input capture A interrupt

1011: Activated by TPU channel 3 compare
match/input capture A interrupt

1100: Activated by TPU channel 4 compare
match/input capture A interrupt

1101: Activated by TPU channel 5 compare
match/input capture A interrupt

1110: Setting prohibited

1111: Setting prohibited

The same factor can be selected for more than
one channel. In this case, activation starts with
the highest-priority channel according to the
relative channel priorities. For relative channel
priorities, see section 7.5.12, Multi-Channel
Operation.

Rev. 2.0, 04/02, page 265 of 906

Full Address Mode:

DMACR_0A and DMACR_1A

Bit

Bit Name

Initial Value

R/W

Description

DTSZ

R/W

Data Transfer Size

Selects the size of data to be transferred at one
time.

0: Byte-size transfer

1: Word-size transfer

SAID

SAIDE

R/W

Source Address Increment/Decrement

Source Address Increment/Decrement Enable

These bits specify whether source address
register MARA is to be incremented,
decremented, or left unchanged, when data
transfer is performed.

00: MARA is fixed

01: MARA is incremented after a data transfer

When DTSZ = 0, MARA is incremented by 1

When DTSZ = 1, MARA is incremented by 2

10: MARA is fixed

11: MARA is decremented after a data transfer

When DTSZ = 0, MARA is decremented by

When DTSZ = 1, MARA is decremented by

BLKDIR

BLKE

R/W

Block Direction

Block Enable

These bits specify whether normal mode or
block transfer mode is to be used for data
transfer. If block transfer mode is specified, the
BLKDIR bit specifies whether the source side or
the destination side is to be the block area.

x0: Transfer in normal mode

01: Transfer in block transfer mode (destination
side is block area)

11: Transfer in block transfer mode (source side
is block area)

Rev. 2.0, 04/02, page 266 of 906

Bit

Bit Name

Initial Value

R/W

Description

10
to
8

All 0

R/W

Reserved

These bits can be read from or written to.
However, the write value should always be 0.

Legend

x: Don't care

DMACR_0B and DMACR_1B

Bit

Bit Name

Initial Value

R/W

Description

R/W

Reserved

This bit can be read from or written to. However,
the write value should always be 0.

6
5

DAID
DAIDE

0
0

R/W
R/W

Destination Address Increment/Decrement

Destination Address Increment/Decrement
Enable

These bits specify whether destination address
register MARB is to be incremented,
decremented, or left unchanged, when data
transfer is performed.

00: MARB is fixed

01: MARB is incremented after a data transfer

When DTSZ = 0, MARB is incremented by 1

When DTSZ = 1, MARB is incremented by 2

10: MARB is fixed

11: MARB is decremented after a data transfer

When DTSZ = 0, MARB is decremented by

When DTSZ = 1, MARB is decremented by

R/W

Reserved

This bit can be read from or written to. However,
the write value should always be 0.

DTF3

DTF2

DTF1

DTF0

R/W

Data Transfer Factor 3 to 0

These bits select the data transfer factor
(activation source). The factors that can be
specified differ between normal mode and block
transfer mode.

Rev. 2.0, 04/02, page 267 of 906

Bit

Bit Name

Initial Value

R/W

Description

Normal Mode

0000: Setting prohibited

0001: Setting prohibited

0010: Activated by

'5(4

pin falling edge input

(detected as a low level in the first transfer after
transfer is enabled)

0011: Activated by

'5(4

pin low-level input

010x: Setting prohibited

0110: Auto-request (cycle steal)

0111: Auto-request (burst)

1xxx: Setting prohibited

Block Transfer Mode