Document Outline

Cover
Cautions
Preface
List of Items Revised or Added for This Version
Comparison of H8/3048 Series Product Specifications
Contents
Section 1 Overview
- 1.1 Overview
- 1.2 Block Diagram
- 1.3 Pin Description
  - 1.3.1 Pin Arrangement
  - 1.3.2 Pin Assignments in Each Mode
  - 1.3.3 Pin Functions
- 1.4 Differences between H8/3048F and H8/3048F-ONE
Section 2 CPU
- 2.1 Overview
  - 2.1.1 Features
  - 2.1.2 Differences from H8/300 CPU
- 2.2 CPU Operating Modes
- 2.3 Address Space
- 2.4 Register Configuration
  - 2.4.1 Overview
  - 2.4.2 General Registers
  - 2.4.3 Control Registers
  - 2.4.4 Initial CPU Register Values
- 2.5 Data Formats
  - 2.5.1 General Register Data Formats
  - 2.5.2 Memory Data Formats
- 2.6 Instruction Set
  - 2.6.1 Instruction Set Overview
  - 2.6.2 Instructions and Addressing Modes
  - 2.6.3 Tables of Instructions Classified by Function
  - 2.6.4 Basic Instruction Formats
  - 2.6.5 Notes on Use of Bit Manipulation Instructions
- 2.7 Addressing Modes and Effective Address Calculation
  - 2.7.1 Addressing Modes
  - 2.7.2 Effective Address Calculation
- 2.8 Processing States
  - 2.8.1 Overview
  - 2.8.2 Program Execution State
  - 2.8.3 Exception-Handling State
  - 2.8.4 Exception-Handling Sequences
  - 2.8.5 Bus-Released State
  - 2.8.6 Reset State
  - 2.8.7 Power-Down State
- 2.9 Basic Operational Timing
  - 2.9.1 Overview
  - 2.9.2 On-Chip Memory Access Timing
  - 2.9.3 On-Chip Supporting Module Access Timing
  - 2.9.4 Access to External Address Space
Section 3 MCU Operating Modes
- 3.1 Overview
  - 3.1.1 Operating Mode Selection
  - 3.1.2 Register Configuration
- 3.2 Mode Control Register (MDCR)
- 3.3 System Control Register (SYSCR)
- 3.4 Operating Mode Descriptions
  - 3.4.1 Mode 1
  - 3.4.2 Mode 2
  - 3.4.3 Mode 3
  - 3.4.4 Mode 4
  - 3.4.5 Mode 5
  - 3.4.6 Mode 6
  - 3.4.7 Mode 7
- 3.5 Pin Functions in Each Operating Mode
- 3.6 Memory Map in Each Operating Mode
Section 4 Exception Handling
- 4.1 Overview
  - 4.1.1 Exception Handling Types and Priority
  - 4.1.2 Exception Handling Operation
  - 4.1.3 Exception Vector Table
- 4.2 Reset
  - 4.2.1 Overview
  - 4.2.2 Reset Sequence
  - 4.2.3 Interrupts after Reset
- 4.3 Interrupts
- 4.4 Trap Instruction
- 4.5 Stack Status after Exception Handling
- 4.6 Notes on Stack Usage
Section 5 Interrupt Controller
- 5.1 Overview
  - 5.1.1 Features
  - 5.1.2 Block Diagram
  - 5.1.3 Pin Configuration
  - 5.1.4 Register Configuration
- 5.2 Register Descriptions
  - 5.2.1 System Control Register (SYSCR)
  - 5.2.2 Interrupt Priority Registers A and B (IPRA, IPRB)
  - 5.2.3 IRQ Status Register (ISR)
  - 5.2.4 IRQ Enable Register (IER)
  - 5.2.5 IRQ Sense Control Register (ISCR)
- 5.3 Interrupt Sources
  - 5.3.1 External Interrupts
  - 5.3.2 Internal Interrupts
  - 5.3.3 Interrupt Vector Table
- 5.4 Interrupt Operation
  - 5.4.1 Interrupt Handling Process
  - 5.4.2 Interrupt Sequence
  - 5.4.3 Interrupt Response Time
- 5.5 Usage Notes
  - 5.5.1 Contention between Interrupt and Interrupt-Disabling Instruction
  - 5.5.2 Instructions that Inhibit Interrupts
  - 5.5.3 Interrupts during EEPMOV Instruction Execution
  - 5.5.4 Usage Notes on External Interrupts
  - 5.5.5 Notes on Non-Maskable Interrupts (NMI)
Section 6 Bus Controller
- 6.1 Overview
  - 6.1.1 Features
  - 6.1.2 Block Diagram
  - 6.1.3 Input/Output Pins
  - 6.1.4 Register Configuration
- 6.2 Register Descriptions
  - 6.2.1 Bus Width Control Register (ABWCR)
  - 6.2.2 Access State Control Register (ASTCR)
  - 6.2.3 Wait Control Register (WCR)
  - 6.2.4 Wait State Controller Enable Register (WCER)
  - 6.2.5 Bus Release Control Register (BRCR)
  - 6.2.6 Chip Select Control Register (CSCR)
- 6.3 Operation
  - 6.3.1 Area Division
  - 6.3.2 Chip Select Signals
  - 6.3.3 Data Bus
  - 6.3.4 Bus Control Signal Timing
  - 6.3.5 Wait Modes
  - 6.3.6 Interconnections with Memory (Example)
  - 6.3.7 Bus Arbiter Operation
- 6.4 Usage Notes
  - 6.4.1 Connection to Dynamic RAM and Pseudo-Static RAM
  - 6.4.2 Register Write Timing
  - 6.4.3 BREQ Input Timing
  - 6.4.4 Transition To Software Standby Mode
Section 7 Refresh Controller
- 7.1 Overview
  - 7.1.1 Features
  - 7.1.2 Block Diagram
  - 7.1.3 Input/Output Pins
  - 7.1.4 Register Configuration
- 7.2 Register Descriptions
  - 7.2.1 Refresh Control Register (RFSHCR)
  - 7.2.2 Refresh Timer Control/Status Register (RTMCSR)
  - 7.2.3 Refresh Timer Counter (RTCNT)
  - 7.2.4 Refresh Time Constant Register (RTCOR)
- 7.3 Operation
  - 7.3.1 Overview
  - 7.3.2 DRAM Refresh Control
  - 7.3.3 Pseudo-Static RAM Refresh Control
  - 7.3.4 Interval Timer
- 7.4 Interrupt Source
- 7.5 Usage Notes
Section 8 DMA Controller
- 8.1 Overview
  - 8.1.1 Features
  - 8.1.2 Block Diagram
  - 8.1.3 Functional Overview
  - 8.1.4 Input/Output Pins
  - 8.1.5 Register Configuration
- 8.2 Register Descriptions (Short Address Mode)
  - 8.2.1 Memory Address Registers (MAR)
  - 8.2.2 I/O Address Registers (IOAR)
  - 8.2.3 Execute Transfer Count Registers (ETCR)
  - 8.2.4 Data Transfer Control Registers (DTCR)
- 8.3 Register Descriptions (Full Address Mode)
  - 8.3.1 Memory Address Registers (MAR)
  - 8.3.2 I/O Address Registers (IOAR)
  - 8.3.3 Execute Transfer Count Registers (ETCR)
  - 8.3.4 Data Transfer Control Registers (DTCR)
- 8.4 Operation
  - 8.4.1 Overview
  - 8.4.2 I/O Mode
  - 8.4.3 Idle Mode
  - 8.4.4 Repeat Mode
  - 8.4.5 Normal Mode
  - 8.4.6 Block Transfer Mode
  - 8.4.7 DMAC Activation
  - 8.4.8 DMAC Bus Cycle
  - 8.4.9 DMAC Multiple-Channel Operation
  - 8.4.10 External Bus Requests, Refresh Controller, and DMAC
  - 8.4.11 NMI Interrupts and DMAC
  - 8.4.12 Aborting a DMA Transfer
  - 8.4.13 Exiting Full Address Mode
  - 8.4.14 DMAC States in Reset State, Standby Modes, and Sleep Mode
- 8.5 Interrupts
- 8.6 Usage Notes
  - 8.6.1 Note on Word Data Transfer
  - 8.6.2 DMAC Self-Access
  - 8.6.3 Longword Access to Memory Address Registers
  - 8.6.4 Note on Full Address Mode Setup
  - 8.6.5 Note on Activating DMAC by Internal Interrupts
  - 8.6.6 NMI Interrupts and Block Transfer Mode
  - 8.6.7 Memory and I/O Address Register Values
  - 8.6.8 Bus Cycle when Transfer is Aborted
Section 9 I/O Ports
- 9.1 Overview
- 9.2 Port 1
  - 9.2.1 Overview
  - 9.2.2 Register Descriptions
- 9.3 Port 2
  - 9.3.1 Overview
  - 9.3.2 Register Descriptions
- 9.4 Port 3
  - 9.4.1 Overview
  - 9.4.2 Register Descriptions
- 9.5 Port 4
  - 9.5.1 Overview
  - 9.5.2 Register Descriptions
- 9.6 Port 5
  - 9.6.1 Overview
  - 9.6.2 Register Descriptions
- 9.7 Port 6
  - 9.7.1 Overview
  - 9.7.2 Register Descriptions
- 9.8 Port 7
  - 9.8.1 Overview
  - 9.8.2 Register Description
- 9.9 Port 8
  - 9.9.1 Overview
  - 9.9.2 Register Descriptions
- 9.10 Port 9
  - 9.10.1 Overview
  - 9.10.2 Register Descriptions
- 9.11 Port A
  - 9.11.1 Overview
  - 9.11.2 Register Descriptions
  - 9.11.3 Pin Functions
- 9.12 Port B
  - 9.12.1 Overview
  - 9.12.2 Register Descriptions
  - 9.12.3 Pin Functions
Section 10 16-Bit Integrated Timer Unit (ITU)
- 10.1 Overview
  - 10.1.1 Features
  - 10.1.2 Block Diagrams
  - 10.1.3 Input/Output Pins
  - 10.1.4 Register Configuration
- 10.2 Register Descriptions
  - 10.2.1 Timer Start Register (TSTR)
  - 10.2.2 Timer Synchro Register (TSNC)
  - 10.2.3 Timer Mode Register (TMDR)
  - 10.2.4 Timer Function Control Register (TFCR)
  - 10.2.5 Timer Output Master Enable Register (TOER)
  - 10.2.6 Timer Output Control Register (TOCR)
  - 10.2.7 Timer Counters (TCNT)
  - 10.2.8 General Registers (GRA, GRB)
  - 10.2.9 Buffer Registers (BRA, BRB)
  - 10.2.10 Timer Control Registers (TCR)
  - 10.2.11 Timer I/O Control Register (TIOR)
  - 10.2.12 Timer Status Register (TSR)
  - 10.2.13 Timer Interrupt Enable Register (TIER)
- 10.3 CPU Interface
  - 10.3.1 16-Bit Accessible Registers
  - 10.3.2 8-Bit Accessible Registers
- 10.4 Operation
  - 10.4.1 Overview
  - 10.4.2 Basic Functions
  - 10.4.3 Synchronization
  - 10.4.4 PWM Mode
  - 10.4.5 Reset-Synchronized PWM Mode
  - 10.4.6 Complementary PWM Mode
  - 10.4.7 Phase Counting Mode
  - 10.4.8 Buffering
  - 10.4.9 ITU Output Timing
- 10.5 Interrupts
  - 10.5.1 Setting of Status Flags
  - 10.5.2 Clearing of Status Flags
  - 10.5.3 Interrupt Sources and DMA Controller Activation
- 10.6 Usage Notes
Section 11 Programmable Timing Pattern Controller
- 11.1 Overview
  - 11.1.1 Features
  - 11.1.2 Block Diagram
  - 11.1.3 TPC Pins
  - 11.1.4 Registers
- 11.2 Register Descriptions
  - 11.2.1 Port A Data Direction Register (PADDR)
  - 11.2.2 Port A Data Register (PADR)
  - 11.2.3 Port B Data Direction Register (PBDDR)
  - 11.2.4 Port B Data Register (PBDR)
  - 11.2.5 Next Data Register A (NDRA)
  - 11.2.6 Next Data Register B (NDRB)
  - 11.2.7 Next Data Enable Register A (NDERA)
  - 11.2.8 Next Data Enable Register B (NDERB)
  - 11.2.9 TPC Output Control Register (TPCR)
  - 11.2.10 TPC Output Mode Register (TPMR)
- 11.3 Operation
  - 11.3.1 Overview
  - 11.3.2 Output Timing
  - 11.3.3 Normal TPC Output
  - 11.3.4 Non-Overlapping TPC Output
  - 11.3.5 TPC Output Triggering by Input Capture
- 11.4 Usage Notes
  - 11.4.1 Operation of TPC Output Pins
  - 11.4.2 Note on Non-Overlapping Output
Section 12 Watchdog Timer
- 12.1 Overview
  - 12.1.1 Features
  - 12.1.2 Block Diagram
  - 12.1.3 Pin Configuration
  - 12.1.4 Register Configuration
- 12.2 Register Descriptions
  - 12.2.1 Timer Counter (TCNT)
  - 12.2.2 Timer Control/Status Register (TCSR)
  - 12.2.3 Reset Control/Status Register (RSTCSR)
  - 12.2.4 Notes on Register Access
- 12.3 Operation
  - 12.3.1 Watchdog Timer Operation
  - 12.3.2 Interval Timer Operation
  - 12.3.3 Timing of Setting of Overflow Flag (OVF)
  - 12.3.4 Timing of Setting of Watchdog Timer Reset Bit (WRST)
- 12.4 Interrupts
- 12.5 Usage Notes
- 12.6 Notes
Section 13 Serial Communication Interface
- 13.1 Overview
  - 13.1.1 Features
  - 13.1.2 Block Diagram
  - 13.1.3 Input/Output Pins
  - 13.1.4 Register Configuration
- 13.2 Register Descriptions
  - 13.2.1 Receive Shift Register (RSR)
  - 13.2.2 Receive Data Register (RDR)
  - 13.2.3 Transmit Shift Register (TSR)
  - 13.2.4 Transmit Data Register (TDR)
  - 13.2.5 Serial Mode Register (SMR)
  - 13.2.6 Serial Control Register (SCR)
  - 13.2.7 Serial Status Register (SSR)
  - 13.2.8 Bit Rate Register (BRR)
- 13.3 Operation
  - 13.3.1 Overview
  - 13.3.2 Operation in Asynchronous Mode
  - 13.3.3 Multiprocessor Communication
  - 13.3.4 Synchronous Operation
- 13.4 SCI Interrupts
- 13.5 Usage Notes
Section 14 Smart Card Interface
- 14.1 Overview
  - 14.1.1 Features
  - 14.1.2 Block Diagram
  - 14.1.3 Input/Output Pins
  - 14.1.4 Register Configuration
- 14.2 Register Descriptions
  - 14.2.1 Smart Card Mode Register (SCMR)
  - 14.2.2 Serial Status Register (SSR)
  - 14.2.3 Serial Mode Register (SMR)
  - 14.2.4 Serial Control Register (SCR)
- 14.3 Operation
  - 14.3.1 Overview
  - 14.3.2 Pin Connections
  - 14.3.3 Data Format
  - 14.3.4 Register Settings
  - 14.3.5 Clock
  - 14.3.6 Transmitting and Receiving Data
- 14.4 Usage Notes
Section 15 A/D Converter
- 15.1 Overview
  - 15.1.1 Features
  - 15.1.2 Block Diagram
  - 15.1.3 Input Pins
  - 15.1.4 Register Configuration
- 15.3 CPU Interface
- 15.4 Operation
  - 15.4.1 Single Mode (SCAN = 0)
  - 15.4.2 Scan Mode (SCAN = 1)
  - 15.4.3 Input Sampling and A/D Conversion Time
  - 15.4.4 External Trigger Input Timing
- 15.5 Interrupts
- 15.6 Usage Notes
Section 16 D/A Converter
- 16.1 Overview
  - 16.1.1 Features
  - 16.1.2 Block Diagram
  - 16.1.3 Input/Output Pins
  - 16.1.4 Register Configuration
- 16.2 Register Descriptions
  - 16.2.1 D/A Data Registers 0 and 1 (DADR0/1)
  - 16.2.2 D/A Control Register (DACR)
  - 16.2.3 D/A Standby Control Register (DASTCR)
- 16.3 Operation
- 16.4 D/A Output Control
- 16.5 Usage Notes
Section 17 RAM
- 17.1 Overview
  - 17.1.1 Block Diagram
  - 17.1.2 Register Configuration
- 17.2 System Control Register (SYSCR)
- 17.3 Operation
Section 18 ROM (H8/3048ZTAT and Mask-ROM Versions)
- 18.1 Overview
  - 18.1.1 Block Diagram
- 18.2 PROM Mode
  - 18.2.1 PROM Mode Setting
  - 18.2.2 Socket Adapter and Memory Map
- 18.3 PROM Programming
  - 18.3.1 Programming and Verification
  - 18.3.2 Programming Precautions
  - 18.3.3 Reliability of Programmed Data
- 18.4 Notes on Ordering Mask ROM Version Chip
Section 19 Flash Memory (H8/3048F: Dual Power Supply (V PP = 12 V))
- 19.1 Overview
- 19.2 Flash Memory Overview
  - 19.2.1 Flash Memory Operation
  - 19.2.2 Mode Programming and Flash Memory Address Space
  - 19.2.3 Features
  - 19.2.4 Block Diagram
  - 19.2.5 Input/Output Pins
  - 19.2.6 Register Configuration
- 19.3 Flash Memory Register Descriptions
  - 19.3.1 Flash Memory Control Register
  - 19.3.2 Erase Block Register 1
  - 19.3.3 Erase Block Register 2
  - 19.3.4 RAM Control Register (RAMCR)
- 19.4 On-Board Programming Modes
  - 19.4.1 Boot Mode
  - 19.4.2 User Program Mode
- 19.5 Programming and Erasing Flash Memory
  - 19.5.1 Program Mode
  - 19.5.2 Program-Verify Mode
  - 19.5.3 Programming Flowchart and Sample Program
  - 19.5.4 Erase Mode
  - 19.5.5 Erase-Verify Mode
  - 19.5.6 Erasing Flowchart and Sample Program
  - 19.5.7 Prewrite-Verify Mode
  - 19.5.8 Protect Modes
  - 19.5.9 NMI Input Masking
- 19.6 Flash Memory Emulation by RAM
- 19.7 Flash Memory PROM Mode
  - 19.7.1 PROM Mode Setting
  - 19.7.2 Socket Adapter and Memory Map
  - 19.7.3 Operation in PROM Mode
- 19.8 Flash Memory Programming and Erasing Precautions (Dual-Power Supply)
- 19.9 Notes when Converting the F-ZTAT (Dual-Power Supply) Application Software to the Mask-ROM Versions
Section 20 Clock Pulse Generator
- 20.1 Overview
  - 20.1.1 Block Diagram
- 20.2 Oscillator Circuit
  - 20.2.1 Connecting a Crystal Resonator
  - 20.2.2 External Clock Input
- 20.3 Duty Adjustment Circuit
- 20.4 Prescalers
- 20.5 Frequency Divider
  - 20.5.1 Register Configuration
  - 20.5.2 Division Control Register (DIVCR)
  - 20.5.3 Usage Notes
Section 21 Power-Down State
- 21.1 Overview
- 21.2 Register Configuration
  - 21.2.1 System Control Register (SYSCR)
  - 21.2.2 Module Standby Control Register (MSTCR)
- 21.3 Sleep Mode
  - 21.3.1 Transition to Sleep Mode
  - 21.3.2 Exit from Sleep Mode
- 21.4 Software Standby Mode
  - 21.4.1 Transition to Software Standby Mode
  - 21.4.2 Exit from Software Standby Mode
  - 21.4.3 Selection of Waiting Time for Exit from Software Standby Mode
  - 21.4.4 Sample Application of Software Standby Mode
  - 21.4.5 Note
- 21.5 Hardware Standby Mode
  - 21.5.1 Transition to Hardware Standby Mode
  - 21.5.2 Exit from Hardware Standby Mode
  - 21.5.3 Timing for Hardware Standby Mode
- 21.6 Module Standby Function
  - 21.6.1 Module Standby Timing
  - 21.6.2 Read/Write in Module Standby
  - 21.6.3 Usage Notes
- 21.7 System Clock Output Disabling Function
Section 22 Electrical Characteristics
- 22.1 Electrical Characteristics for H8/3048 ZTAT (PROM) and On-Chip Mask ROM Versions
  - 22.1.1 Absolute Maximum Ratings
  - 22.1.2 DC Characteristics
  - 22.1.3 AC Characteristics
  - 22.1.4 A/D Conversion Characteristics
  - 22.1.5 D/A Conversion Characteristics
- 22.2 Electrical Characteristics of H8/3048F (Dual-Power Supply)
  - 22.2.1 Absolute Maximum Ratings
  - 22.2.2 DC Characteristics
  - 22.2.3 AC Characteristics
  - 22.2.4 A/D Conversion Characteristics
  - 22.2.5 D/A Conversion Characteristics
  - 22.2.6 Flash Memory Characteristics
- 22.3 Operational Timing
  - 22.3.1 Bus Timing
  - 22.3.2 Refresh Controller Bus Timing
  - 22.3.3 Control Signal Timing
  - 22.3.4 Clock Timing
  - 22.3.5 TPC and I/O Port Timing
  - 22.3.6 ITU Timing
  - 22.3.7 SCI Input/Output Timing
  - 22.3.8 DMAC Timing
Appendix A Instruction Set
- A.1 Instruction List
- A.2 Operation Code Map
- A.3 Number of States Required for Execution
Appendix B Internal I/O Register
- B.1 Addresses
- B.2 Function
Appendix C I/O Port Block Diagrams
- C.1 Port 1 Block Diagram
- C.2 Port 2 Block Diagram
- C.3 Port 3 Block Diagram
- C.4 Port 4 Block Diagram
- C.5 Port 5 Block Diagram
- C.6 Port 6 Block Diagrams
- C.7 Port 7 Block Diagrams
- C.8 Port 8 Block Diagrams
- C.9 Port 9 Block Diagrams
- C.10 Port A Block Diagrams
- C.11 Port B Block Diagrams
Appendix D Pin States
- D.1 Port States in Each Mode
- D.2 Pin States at Reset
Appendix E Timing of Transition to and Recovery from Hardware Standby Mode
Appendix F Product Code Lineup
Appendix G Package Dimensions
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Электронный компонент: HD6433048V

Document Outline