Document Outline

• Cover
• Cautions
• Preface
• Comparison of H8/3062 Series Product Specifications
• List of Items Revised or Added for This Version
• Contents
• Section 1 Overview
  • 1.1 Overview
  • 1.2 Block Diagram
  • 1.3 Pin Description
    • 1.3.1 Pin Arrangement
    • 1.3.2 Pin Functions
    • 1.3.3 Pin Assignments in Each Mode
  • 1.4 Notes on H8/3062F-ZTAT R-Mask Version
    • 1.4.1 Pin Arrangement
    • 1.4.2 Product Type Names and Markings
    • 1.4.3 Differences between H8/3062F-ZTAT and H8/3062F-ZTAT R-Mask Version
  • 1.5 Notes on H8/3064F-ZTAT B-Mask Version,H8/3062F-ZTAT B-Mask Version,H8/3064 Mask ROM B-Mask Version,H8/3062 Mask ROM B-Mas
    • 1.5.1 Pin Arrangement
    • 1.5.2 Product Type Names and Markings
    • 1.5.3 VCL Pin
    • 1.5.4 Notes on Changeover to On-Chip Mask ROM Versions and On-Chip Mask ROM B-Mask Versions
  • 1.6 Setting Oscillation Settling Wait Time
  • 1.7 Caution on Crystal Resonator Connection
• Section 2 CPU
  • 2.1 Overview
    • 2.1.1 Features
    • 2.1.2 Differences from H8/300 CPU
  • 2.2 CPU Operating Modes
  • 2.3 Address Space
  • 2.4 Register Configuration
    • 2.4.1 Overview
    • 2.4.2 General Registers
    • 2.4.3 Control Registers
    • 2.4.4 Initial CPU Register Values
  • 2.5 Data Formats
    • 2.5.1 General Register Data Formats
    • 2.5.2 Memory Data Formats
  • 2.6 Instruction Set
    • 2.6.1 Instruction Set Overview
    • 2.6.2 Instructions and Addressing Modes
    • 2.6.3 Tables of Instructions Classified by Function
    • 2.6.4 Basic Instruction Formats
    • 2.6.5 Notes on Use of Bit Manipulation Instructions
  • 2.7 Addressing Modes and Effective Address Calculation
    • 2.7.1 Addressing Modes
    • 2.7.2 Effective Address Calculation
  • 2.8 Processing States
    • 2.8.1 Overview
    • 2.8.2 Program Execution State
    • 2.8.3 Exception-Handling State
    • 2.8.4 Exception Handling Operation
    • 2.8.5 Bus-Released State
    • 2.8.6 Reset State
    • 2.8.7 Power-Down State
  • 2.9 Basic Operational Timing
    • 2.9.1 Overview
    • 2.9.2 On-Chip Memory Access Timing
    • 2.9.3 On-Chip Supporting Module Access Timing
    • 2.9.4 Access to External Address Space
• Section 3 MCU Operating Modes
  • 3.1 Overview
    • 3.1.1 Operating Mode Selection
    • 3.1.2 Register Configuration
  • 3.2 Mode Control Register (MDCR)
  • 3.3 System Control Register (SYSCR)
  • 3.4 Operating Mode Descriptions
    • 3.4.1 Mode 1
    • 3.4.2 Mode 2
    • 3.4.3 Mode 3
    • 3.4.4 Mode 4
    • 3.4.5 Mode 5
    • 3.4.6 Mode 6
    • 3.4.7 Mode 7
  • 3.5 Pin Functions in Each Operating Mode
  • 3.6 Memory Map in Each Operating Mode
    • 3.6.1 Comparison of H8/3062 Series Memory Maps
    • 3.6.2 Reserved Areas
• Section 4 Exception Handling
  • 4.1 Overview
    • 4.1.1 Exception Handling Types and Priority
    • 4.1.2 Exception Handling Operation
    • 4.1.3 Exception Vector Table
  • 4.2 Reset
    • 4.2.1 Overview
    • 4.2.2 Reset Sequence
    • 4.2.3 Interrupts after Reset
  • 4.3 Interrupts
  • 4.4 Trap Instruction
  • 4.5 Stack Status after Exception Handling
  • 4.6 Notes on Stack Usage
• Section 5 Interrupt Controller
  • 5.1 Overview
    • 5.1.1 Features
    • 5.1.2 Block Diagram
    • 5.1.3 Pin Configuration
    • 5.1.4 Register Configuration
  • 5.2 Register Descriptions
    • 5.2.1 System Control Register (SYSCR)
    • 5.2.2 Interrupt Priority Registers A and B (IPRA,IPRB)
    • 5.2.3 IRQ Status Register (ISR)
    • 5.2.4 IRQ Enable Register (IER)
    • 5.2.5 IRQ Sense Control Register (ISCR)
  • 5.3 Interrupt Sources
    • 5.3.1 External Interrupts
    • 5.3.2 Internal Interrupts
    • 5.3.3 Interrupt Exception Handling Vector Table
  • 5.4 Interrupt Operation
    • 5.4.1 Interrupt Handling Process
    • 5.4.2 Interrupt Exception Handling Sequence
    • 5.4.3 Interrupt Response Time
  • 5.5 Usage Notes
    • 5.5.1 Contention between Interrupt and Interrupt-Disabling Instruction
    • 5.5.2 Instructions that Inhibit Interrupts
    • 5.5.3 Interrupts during EEPMOV Instruction Execution
• Section 6 Bus Controller
  • 6.1 Overview
    • 6.1.1 Features
    • 6.1.2 Block Diagram
    • 6.1.3 Pin Configuration
    • 6.1.4 Register Configuration
  • 6.2 Register Descriptions
    • 6.2.1 Bus Width Control Register (ABWCR)
    • 6.2.2 Access State Control Register (ASTCR)
    • 6.2.3 Wait Control Registers H and L (WCRH,WCRL)
    • 6.2.4 Bus Release Control Register (BRCR)
    • 6.2.5 Bus Control Register (BCR)
    • 6.2.6 Chip Select Control Register (CSCR)
    • 6.2.7 Address Control Register (ADRCR)
  • 6.3 Operation
    • 6.3.1 Area Division
    • 6.3.2 Bus Specifications
    • 6.3.3 Memory Interfaces
    • 6.3.4 Chip Select Signals
    • 6.3.5 Address Output Method
  • 6.4Basic Bus Interface
    • 6.4.1 Overview
    • 6.4.2 Data Size and Data Alignment
    • 6.4.3 Valid Strobes
    • 6.4.4 Memory Areas
    • 6.4.5 Basic Bus Control Signal Timing
    • 6.4.6 Wait Control
  • 6.5 Idle Cycle
    • 6.5.1 Operation
    • 6.5.2 Pin States in Idle Cycle
  • 6.6 Bus Arbiter
    • 6.6.1 Operation
  • 6.7 Register and Pin Input Timing
    • 6.7.1 Register Write Timing
    • 6.7.2 BREQ Pin Input Timing
• Section 7 I/O Ports
  • 7.1 Overview
  • 7.2 Port 1
    • 7.2.1 Overview
    • 7.2.2 Register Descriptions
  • 7.3 Port 2
    • 7.3.1 Overview
    • 7.3.2 Register Descriptions
  • 7.4 Port 3
    • 7.4.1 Overview
    • 7.4.2 Register Descriptions
  • 7.5 Port 4
    • 7.5.1 Overview
    • 7.5.2 Register Descriptions
  • 7.6 Port 5
    • 7.6.1 Overview
    • 7.6.2 Register Descriptions
  • 7.7 Port 6
    • 7.7.1 Overview
    • 7.7.2 Register Descriptions
  • 7.8 Port 7
    • 7.8.1 Overview
    • 7.8.2 Register Description
  • 7.9 Port 8
    • 7.9.1 Overview
    • 7.9.2 Register Descriptions
  • 7.10 Port 9
    • 7.10.1 Overview
    • 7.10.2 Register Descriptions
  • 7.11 Port A
    • 7.11.1 Overview
    • 7.11.2 Register Descriptions
  • 7.12 Port B
    • 7.12.1 Overview
    • 7.12.2 Register Descriptions
• Section 8 16-Bit Timer
  • 8.1 Overview
    • 8.1.1 Features
    • 8.1.2 Block Diagrams
    • 8.1.3 Pin Configuration
    • 8.1.4 Register Configuration
  • 8.2 Register Descriptions
    • 8.2.1 Timer Start Register (TSTR)
    • 8.2.2 Timer Synchro Register (TSNC)
    • 8.2.3 Timer Mode Register (TMDR)
    • 8.2.4 Timer Interrupt Status Register A (TISRA)
    • 8.2.5 Timer Interrupt Status Register B (TISRB)
    • 8.2.6 Timer Interrupt Status Register C (TISRC)
    • 8.2.7 Timer Counters (16TCNT)
    • 8.2.8 General Registers (GRA,GRB)
    • 8.2.9 Timer Control Registers (16TCR)
    • 8.2.10 Timer I/O Control Register (TIOR)
    • 8.2.11 Timer Output Level Setting Register C (TOLR)
  • 8.3 CPU Interface
    • 8.3.1 16-Bit Accessible Registers
    • 8.3.2 8-Bit Accessible Registers
  • 8.4 Operation
    • 8.4.1 Overview
    • 8.4.2 Basic Functions
    • 8.4.3 Synchronization
    • 8.4.4 PWM Mode
    • 8.4.5 Phase Counting Mode
    • 8.4.6 16-Bit Timer Output Timing
  • 8.5 Interrupts
    • 8.5.1 Setting of Status Flags
    • 8.5.2 Timing of Clearing of Status Flags
    • 8.5.3 Interrupt Sources
  • 8.6 Usage Notes
• Section 9 8-Bit Timers
  • 9.1 Overview
    • 9.1.1 Features
    • 9.1.2 Block Diagram
    • 9.1.3 Pin Configuration
    • 9.1.4 Register Configuration
  • 9.2 Register Descriptions
    • 9.2.1 Timer Counters (8TCNT)
    • 9.2.2 Time Constant Registers A (TCORA)
    • 9.2.3 Time Constant Registers B (TCORB)
    • 9.2.4 Timer Control Register (8TCR)
    • 9.2.5 Timer Control/Status Registers (8TCSR)
  • 9.3 CPU Interface
    • 9.3.1 8-Bit Registers
  • 9.4 Operation
    • 9.4.1 8TCNT Count Timing
    • 9.4.2 Compare Match Timing
    • 9.4.3 Input Capture Signal Timing
    • 9.4.4 Timing of Status Flag Setting
    • 9.4.5 Operation with Cascaded Connection
    • 9.4.6 Input Capture Setting
  • 9.5 Interrupt
    • 9.5.1 Interrupt Sources
    • 9.5.2 A/D Converter Activation
  • 9.6 8-Bit Timer Application Example
  • 9.7 Usage Notes
    • 9.7.1 Contention between 8TCNT Write and Clear
    • 9.7.2 Contention between 8TCNT Write and Increment
    • 9.7.3 Contention between TCOR Write and Compare Match
    • 9.7.4 Contention between TCOR Read and Input Capture
    • 9.7.5 Contention between Counter Clearing by Input Capture and Counter Increment
    • 9.7.6 Contention between TCOR Write and Input Capture
    • 9.7.7 Contention between 8TCNT Byte Write and Increment in 16-Bit Count Mode (Cascaded Connection)
    • 9.7.8 Contention between Compare Matches A and B
    • 9.7.9 8TCNT Operation and Internal Clock Source Switchover
• Section 10 Programmable Timing Pattern Controller (TPC)
  • 10.1 Overview
    • 10.1.1 Features
    • 10.1.2 Block Diagram
    • 10.1.3 Pin Configuration
    • 10.1.4 Register Configuration
  • 10.2 Register Descriptions
    • 10.2.1 Port A Data Direction Register (PADDR)
    • 10.2.2 Port A Data Register (PADR)
    • 10.2.3 Port B Data Direction Register (PBDDR)
    • 10.2.4 Port B Data Register (PBDR)
    • 10.2.5 Next Data Register A (NDRA)
    • 10.2.6 Next Data Register B (NDRB)
    • 10.2.7 Next Data Enable Register A (NDERA)
    • 10.2.8 Next Data Enable Register B (NDERB)
    • 10.2.9 TPC Output Control Register (TPCR)
    • 10.2.10 TPC Output Mode Register (TPMR)
  • 10.3 Operation
    • 10.3.1 Overview
    • 10.3.2 Output Timing
    • 10.3.3 Normal TPC Output
    • 10.3.4 Non-Overlapping TPC Output
    • 10.3.5 TPC Output Triggering by Input Capture
  • 10.4Usage Notes
    • 10.4.1 Operation of TPC Output Pins
    • 10.4.2 Note on Non-Overlapping Output
• Section 11 Watchdog Timer
  • 11.1 Overview
    • 11.1.1 Features
    • 11.1.2 Block Diagram
    • 11.1.3 Pin Configuration
    • 11.1.4 Register Configuration
  • 11.2 Register Descriptions
    • 11.2.1 Timer Counter (TCNT)
    • 11.2.2 Timer Control/Status Register (TCSR)
    • 11.2.3 Reset Control/Status Register (RSTCSR)
    • 11.2.4 Notes on Register Rewriting
  • 11.3 Operation
    • 11.3.1 Watchdog Timer Operation
    • 11.3.2 Interval Timer Operation
    • 11.3.3 Timing of Setting of Overflow Flag (OVF)
    • 11.3.4 Timing of Setting of Watchdog Timer Reset Bit (WRST)
  • 11.4Interrupts
  • 11.5 Usage Notes
• Section 12 Serial Communication Interface
  • 12.1 Overview
    • 12.1.1 Features
    • 12.1.2 Block Diagram
    • 12.1.3 Pin Configuration
    • 12.1.4 Register Configuration
  • 12.2 Register Descriptions
    • 12.2.1 Receive Shift Register (RSR)
    • 12.2.2 Receive Data Register (RDR)
    • 12.2.3 Transmit Shift Register (TSR)
    • 12.2.4 Transmit Data Register (TDR)
    • 12.2.5 Serial Mode Register (SMR)
    • 12.2.6 Serial Control Register (SCR)
    • 12.2.7 Serial Status Register (SSR)
    • 12.2.8 Bit Rate Register (BRR)
  • 12.3Operation
    • 12.3.1 Overview
    • 12.3.2 Operation in Asynchronous Mode
    • 12.3.3 Multiprocessor Communication
    • 12.3.4 Synchronous Operation
  • 12.4 SCI Interrupts
  • 12.5 Usage Notes
    • 12.5.1 Notes on Use of SCI
• Section 13 Smart Card Interface
  • 13.1 Overview
    • 13.1.1 Features
    • 13.1.2 Block Diagram
    • 13.1.3 Pin Configuration
    • 13.1.4 Register Configuration
  • 13.2 Register Descriptions
    • 13.2.1 Smart Card Mode Register (SCMR)
    • 13.2.2 Serial Status Register (SSR)
    • 13.2.3 Serial Mode Register (SMR)
    • 13.2.4 Serial Control Register (SCR)
  • 13.3 Operation
    • 13.3.1 Overview
    • 13.3.2 Pin Connections
    • 13.3.3 Data Format
    • 13.3.4 Register Settings
    • 13.3.5 Clock
    • 13.3.6 Transmitting and Receiving Data
  • 13.4 Usage Notes
• Section 14 A/D Converter
  • 14.1 Overview
    • 14.1.1 Features
    • 14.1.2 Block Diagram
    • 14.1.3 Pin Configuration
    • 14.1.4 Register Configuration
  • 14.2 Register Descriptions
    • 14.2.1 A/D Data Registers A to D (ADDRA to ADDRD)
    • 14.2.2 A/D Control/Status Register (ADCSR)
    • 14.2.3 A/D Control Register (ADCR)
  • 14.3 CPU Interface
  • 14.4 Operation
    • 14.4.1 Single Mode (SCAN =0)
    • 14.4.2 Scan Mode (SCAN =1)
    • 14.4.3 Input Sampling and A/D Conversion Time
    • 14.4.4 External Trigger Input Timing
  • 14.5 Interrupts
  • 14.6 Usage Notes
• Section 15 D/A Converter
  • 15.1 Overview
    • 15.1.1 Features
    • 15.1.2 Block Diagram
    • 15.1.3 Pin Configuration
    • 15.1.4 Register Configuration
  • 15.2 Register Descriptions
    • 15.2.1 D/A Data Registers 0 and 1 (DADR0,DADR1)
    • 15.2.2 D/A Control Register (DACR)
    • 15.2.3 D/A Standby Control Register (DASTCR)
  • 15.3 Operation
  • 15.4 D/A Output Control
• Section 16 RAM
  • 16.1 Overview
    • 16.1.1 Block Diagram
    • 16.1.2 Register Configuration
  • 16.2 System Control Register (SYSCR)
  • 16.3 Operation
• Section 17 ROM [H8/3062F-ZTAT,H8/3062F-ZTAT ROM Version, On-Chip Mask ROM Models ]
  • 17.1 Overview
  • 17.2 Overview of Flash Memory (H8/3062F-ZTAT,H8/3062F-ZTAT R-Mask Version)
    • 17.2.1 Features
    • 17.2.2 Block Diagram
    • 17.2.3 Pin Configuration
    • 17.2.4 Register Configuration
  • 17.3 Flash Memory Register Descriptions
    • 17.3.1 Flash Memory Control Register (FLMCR)
    • 17.3.2 Erase Block Register (EBR)
    • 17.3.3 RAM Control Register (RAMCR)
    • 17.3.4 Flash Memory Status Register (FLMSR)
  • 17.4 On-Board Programming Mode
    • 17.4.1 Boot Mode
    • 17.4.2 User Program Mode
  • 17.5 Flash Memory Programming/Erasing
    • 17.5.1 Program Mode
    • 17.5.2 Program-Verify Mode
    • 17.5.3 Erase Mode
    • 17.5.4 Erase-Verify Mode
  • 17.6 Flash Memory Protection
    • 17.6.1 Hardware Protection
    • 17.6.2 Software Protection
    • 17.6.3 Error Protection
    • 17.6.4 NMI Input Disabling Conditions
  • 17.7 Flash Memory Emulation in RAM
  • 17.8Flash Memory PROM Mode
    • 17.8.1 Socket Adapters and Memory Map
    • 17.8.2 Notes on Use of PROM Mode
  • 17.9 Flash Memory Programming and Erasing Precautions
  • 17.10 Mask ROM (H8/3062 Mask ROM Version,H8/3061 Mask ROM Version,H8/3060 Mask ROM Version)Overview
    • 17.10.1 Block Diagram
  • 17.11 Notes on Ordering Mask ROM Version Chips
  • 17.12 Notes when Converting the F-ZTAT Application Software to the Mask-ROM Versions
• Section 18 H8/3064 Internal Voltage Step-Down Version ROM [H8/3064F-ZTAT B-Mask Version,H8/3064 Mask ROM B-Mask Version ]
  • 18.1 Overview
    • 18.1.1 Differences from H8/3062F-ZTAT and H8/3062F-ZTAT R-Mask Version
  • 18.2 Features
    • 18.2.1 Block Diagram
    • 18.2.2 Pin Configuration
    • 18.2.3 Register Configuration
  • 18.3 Register Descriptions
    • 18.3.1 Flash Memory Control Register 1 (FLMCR1)
    • 18.3.2 Flash Memory Control Register 2 (FLMCR2)
    • 18.3.3 Erase Block Register 1 (EBR1)
    • 18.3.4 Erase Block Register 2 (EBR2)
    • 18.3.5 RAM Control Register (RAMCR)
  • 18.4 Overview of Operation
    • 18.4.1 Mode Transitions
    • 18.4.2 On-Board Programming Modes
    • 18.4.3 Flash Memory Emulation in RAM
    • 18.4.4 Block Configuration
  • 18.5 On-Board Programming Mode
    • 18.5.1 Boot Mode
    • 18.5.2 User Program Mode
  • 18.6Flash Memory Programming/Erasing
    • 18.6.1 Program Mode
    • 18.6.2 Program-Verify Mode
    • 18.6.3 Erase Mode
    • 18.6.4 Erase-Verify Mode
  • 18.7 Flash Memory Protection
    • 18.7.1 Hardware Protection
    • 18.7.2 Software Protection
    • 18.7.3 Error Protection
  • 18.8 Flash Memory Emulation in RAM
  • 18.9 NMI Input Disabling Conditions
  • 18.10 Flash Memory PROM Mode
    • 18.10.1 Socket Adapters and Memory Map
    • 18.10.2 Notes on Use of PROM Mode
  • 18.11 Flash Memory Programming and Erasing Precautions
  • 18.12 Mask ROM (H8/3064 Mask ROM B-Mask Version)Overview
    • 18.12.1 Block Diagram
  • 18.13 Notes on Ordering Mask ROM Version Chips
  • 18.14 Notes when Converting the F-ZTAT Application Software to the Mask-ROM Version
• Section 19 H8/3062 Internal Voltage Step-Down Version ROM [H8/3062F-ZTAT B-Mask Version,Mask ROM B-Mask Versions of H8/3062,H
  • 19.1 Overview
    • 19.1.1 Differences from H8/3062F-ZTAT and H8/3062F-ZTAT R-Mask Version
  • 19.2 Features
    • 19.2.1 Block Diagram
    • 19.2.2 Pin Configuration
    • 19.2.3 Register Configuration
  • 19.3 Register Descriptions
    • 19.3.1 Flash Memory Control Register 1 (FLMCR1)
    • 19.3.2 Flash Memory Control Register 2 (FLMCR2)
    • 19.3.3 Erase Block Register (EBR)
    • 19.3.4 RAM Control Register (RAMCR)
  • 19.4 Overview of Operation
    • 19.4.1 Mode Transitions
    • 19.4.2 On-Board Programming Modes
    • 19.4.3 Flash Memory Emulation in RAM
    • 19.4.4 Block Configuration
  • 19.5 On-Board Programming Mode
    • 19.5.1 Boot Mode
    • 19.5.2 User Program Mode
  • 19.6 Flash Memory Programming/Erasing
    • 19.6.1 Program Mode
    • 19.6.2 Program-Verify Mode
    • 19.6.3 Erase Mode
    • 19.6.4 Erase-Verify Mode
  • 19.7 Flash Memory Protection
    • 19.7.1 Hardware Protection
    • 19.7.2 Software Protection
    • 19.7.3 Error Protection
  • 19.8 Flash Memory Emulation in RAM
  • 19.9 NMI Input Disabling Conditions
  • 19.10Flash Memory PROM Mode
    • 19.10.1 Socket Adapters and Memory Map
    • 19.10.2 Notes on Use of PROM Mode
  • 19.11 Flash Memory Programming and Erasing Precautions
  • 19.12 Mask ROM (H8/3062 Mask ROM B-Mask Version,H8/3061 Mask ROM B-Mask Version,H8/3060 Mask ROM B-Mask Version) Overview
    • 19.12.1 Block Diagram
  • 19.13 Notes on Ordering Mask ROM Version Chips
  • 19.14 Notes when Converting the F-ZTAT Application Software to the Mask-ROM Versions
• Section 20 Clock Pulse Generator
  • 20.1 Overview
    • 20.1.1 Block Diagram
  • 20.2 Oscillator Circuit
    • 20.2.1 Connecting a Crystal Resonator
    • 20.2.2 External Clock Input
  • 20.3 Duty Adjustment Circuit
  • 20.4 Prescalers
  • 20.5 Frequency Divider
    • 20.5.1 Register Configuration
    • 20.5.2 Division Control Register (DIVCR)
    • 20.5.3 Usage Notes
• Section 21 Power-Down State
  • 21.1 Overview
  • 21.2 Register Configuration
    • 21.2.1 System Control Register (SYSCR)
    • 21.2.2 Module Standby Control Register H (MSTCRH)
    • 21.2.3 Module Standby Control Register L (MSTCRL)
  • 21.3 Sleep Mode
    • 21.3.1 Transition to Sleep Mode
    • 21.3.2 Exit from Sleep Mode
  • 21.4 Software Standby Mode
    • 21.4.1 Transition to Software Standby Mode
    • 21.4.2 Exit from Software Standby Mode
    • 21.4.3 Selection of Waiting Time for Exit from Software Standby Mode
    • 21.4.4 Sample Application of Software Standby Mode
    • 21.4.5 Usage Note
    • 21.4.6 Cautions on Clearing the software Standby Mode of F-ZTAT Version
  • 21.5 Hardware Standby Mode
    • 21.5.1 Transition to Hardware Standby Mode
    • 21.5.2 Exit from Hardware Standby Mode
    • 21.5.3 Timing for Hardware Standby Mode
  • 21.6 Module Standby Function
    • 21.6.1 Module Standby Timing
    • 21.6.2 Read/Write in Module Standby
    • 21.6.3 Usage Notes
  • 21.7 System Clock Output Disabling Function
• Section 22 Electrical Characteristics
  • 22.1 Electrical Characteristics of H8/3062 Mask ROM Version, H8/3061 Mask ROM Version,and H8/3060 Mask ROM Version
    • 22.1.1 Absolute Maximum Ratings
    • 22.1.2 DC Characteristics
    • 22.1.3 AC Characteristics
    • 22.1.4 A/D Conversion Characteristics
    • 22.1.5 D/A Conversion Characteristics
  • 22.2 Electrical Characteristics of H8/3062F-ZTAT and H8/3062F-ZTAT R-Mask Version
    • 22.2.1 Absolute Maximum Ratings
    • 22.2.2 DC Characteristics
    • 22.2.3 AC Characteristics
    • 22.2.4 A/D Conversion Characteristics
    • 22.2.5 D/A Conversion Characteristics
    • 22.2.6 Flash Memory Characteristics
  • 22.3 Electrical Characteristics of H8/3064F-ZTAT B-Mask Version
    • 22.3.1 Absolute Maximum Ratings
    • 22.3.2 DC Characteristics
    • 22.3.3 AC Characteristics
    • 22.3.4 A/D Conversion Characteristics
    • 22.3.5 D/A Conversion Characteristics
    • 22.3.6 Flash Memory Characteristics
  • 22.4 Electrical Characteristics of H8/3064 Mask ROM B-Mask Version
    • 22.4.1 Absolute Maximum Ratings
    • 22.4.2 DC Characteristics
    • 22.4.3 AC Characteristics
    • 22.4.4 A/D Conversion Characteristics
    • 22.4.5 D/A Conversion Characteristics
  • 22.5 Electrical Characteristics of H8/3062F-ZTAT B-Mask Version
    • 22.5.1 Absolute Maximum Ratings
    • 22.5.2 DC Characteristics
    • 22.5.3 AC Characteristics
    • 22.5.4 A/D Conversion Characteristics
    • 22.5.5 D/A Conversion Characteristics
    • 22.5.6 Flash Memory Characteristics
  • 22.6 Electrical Characteristics of H8/3062 Mask ROM B-Mask Version, H8/3061 Mask ROM B-Mask Version,and H8/3060 Mask ROM B-Ma
    • 22.6.1 Absolute Maximum Ratings
    • 22.6.2 DC Characteristics
    • 22.6.3 AC Characteristics
    • 22.6.4 A/D Conversion Characteristics
    • 22.6.5 D/A Conversion Characteristics
  • 22.7 Operational Timing
    • 22.7.1 Clock Timing
    • 22.7.2 Control Signal Timing
    • 22.7.3 Bus Timing
    • 22.7.4 TPC and I/O Port Timing
    • 22.7.5 Timer Input/Output Timing
    • 22.7.6 SCI Input/Output Timing
• Appendix A Instruction Set
  • A.1 Instruction List
  • A.2 Operation Code Maps
  • A.3 Number of States Required for Execution
• Appendix B Internal I/O Registers
  • B.1 Address List (H8/3062F-ZTAT,H8/3062F-ZTAT R-Mask Version, H8/3062 Mask ROM Version,H8/3061 Mask ROM Version, H8/3060 Mask
  • B.2 Address List (H8/3064F-ZTAT B-Mask Version,H8/3064 Mask ROM B-Mask Version)
  • B.3 Address List (H8/3062F-ZTAT B-Mask Version,H8/3062 Mask ROM B-Mask Version,H8/3061 Mask ROM B-Mask Version, and H8/3060 M
  • B.4 Functions
• Appendix C I/O Port Block Diagrams
  • C.1 Port 1 Block Diagram
  • C.2 Port 2 Block Diagram
  • C.3 Port 3 Block Diagram
  • C.4 Port 4 Block Diagram
  • C.5 Port 5 Block Diagram
  • C.6 Port 6 Block Diagrams
  • C.7 Port 7 Block Diagrams
  • C.8 Port 8 Block Diagrams
  • C.9 Port 9 Block Diagrams
  • C.10 Port A Block Diagrams
  • C.11 Port B Block Diagrams
• Appendix D Pin States
  • D.1 Port States in Each Mode
  • D.2 Pin States at Reset
• Appendix E Timing of Transition to and Recovery from Hardware Standby Mode
• Appendix F Product Code Lineup
• Appendix G Package Dimensions
• Appendix H Comparison of H8/300H Series Product Specifications
  • H.1 Differences between H8/3067 and H8/3062 Series,H8/3048 Series, H8/3007 and H8/3006,and H8/3002
  • H.2 Comparison of Pin Functions of 100-Pin Package Products (FP-100B,TFP-100B)
• Colophon