Document Outline

• Cover
• Cautions
• Preface
• List of Items Revised or Added for This Version
• Contents
• Section 1 SH7040 Series Overview
  • 1.1 SH7040 Series Overview
    • 1.1.1 SH7040 Series Features
  • 1.2 Block Diagram
  • 1.3 Pin Arrangement and Pin Functions
    • 1.3.1 Pin Arrangment
    • 1.3.2 Pin Arrangement by Mode
    • 1.3.3 Pin Functions
  • 1.4 The F-ZTAT Version Onboard Programming
• Section 2 CPU
  • 2.1 Register Configuration
    • 2.1.1 General Registers (Rn)
    • 2.1.2 Control Registers
    • 2.1.3 System Registers
    • 2.1.4 Initial Values of Registers
  • 2.2 Data Formats
    • 2.2.1 Data Format in Registers
    • 2.2.2 Data Format in Memory
    • 2.2.3 Immediate Data Format
  • 2.3 Instruction Features
    • 2.3.1 RISC-Type Instruction Set
    • 2.3.2 Addressing Modes
    • 2.3.3 Instruction Format
  • 2.4 Instruction Set by Classification
  • 2.5 Processing States
    • 2.5.1 State Transitions
    • 2.5.2 Power-Down State
• Section 3 Operating Modes
  • 3.1 Operating Modes,Types,and Selection
  • 3.2 Explanation of Operating Modes
  • 3.3 Pin Configuration
• Section 4 Clock Pulse Generator (CPG)
  • 4.1 Overview
    • 4.1.1 Block Diagram
  • 4.2 Oscillator
    • 4.2.1 Connecting a Crystal Oscillator
    • 4.2.2 External Clock Input Method
  • 4.3 Prescaler
  • 4.4 Oscillator Halt Function
  • 4.5 Usage Notes
    • 4.5.1 Oscillator Usage Notes
    • 4.5.2 Notes on Board Design
    • 4.5.3 Spread Spectrum Clock Generator Usage Notes
• Section 5 Exception Processing
  • 5.1 Overview
    • 5.1.1 Types of Exception Processing and Priority
    • 5.1.2 Exception Processing Operations
    • 5.1.3 Exception Processing Vector Table
  • 5.2 Resets
    • 5.2.1 Power-On Reset
    • 5.2.2 Manual Reset
  • 5.3 Address Errors
    • 5.3.1 Address Error Exception Processing
  • 5.4 Interrupts
    • 5.4.1 Interrupt Priority Level
    • 5.4.2 Interrupt Exception Processing
  • 5.5 Exceptions Triggered by Instructions
    • 5.5.1 Trap Instructions
    • 5.5.2 Illegal Slot Instructions
    • 5.5.3 General Illegal Instructions
  • 5.6 When Exception Sources Are Not Accepted
    • 5.6.1 Immediately after a Delayed Branch Instruction
    • 5.6.2 Immediately after an Interrupt-Disabled Instruction
  • 5.7 Stack Status after Exception Processing Ends
  • 5.8 Notes on Use
    • 5.8.1 Value of Stack Pointer (SP)
    • 5.8.2 Value of Vector Base Register (VBR)
    • 5.8.3 Address Errors Caused by Stacking of Address Error Exception Processing
• Section 6 Interrupt Controller (INTC)
  • 6.1 Overview
    • 6.1.1 Features
    • 6.1.2 Block Diagram
    • 6.1.3 Pin Configuration
    • 6.1.4 Register Configuration
  • 6.2 Interrupt Sources
    • 6.2.1 NMI Interrupts
    • 6.2.2 User Break Interrupt
    • 6.2.3 IRQ Interrupts
    • 6.2.4 On-Chip Peripheral Module Interrupts
    • 6.2.5 Interrupt Exception Vectors and Priority Rankings
  • 6.3 Description of Registers
    • 6.3.1 Interrupt Priority Registers A �H (IPRA �IPRH)
    • 6.3.2 Interrupt Control Register (ICR)
    • 6.3.3 IRQ Status Register (ISR)
  • 6.4 Interrupt Operation
    • 6.4.1 Interrupt Sequence
    • 6.4.2 Stack after Interrupt Exception Processing
  • 6.5 Interrupt Response Time
  • 6.6 Data Transfer with Interrupt Request Signals
    • 6.6.1 Handling DTC Activating and CPU Interrupt Sources,but Not DMAC Activating Sources
    • 6.6.2 Handling DMAC Activating Sources but Not CPU Interrupt or DTC Activating Sources
    • 6.6.3 Handling DTC Activating Sources but Not CPU Interrupt or DMAC Activating Sources
    • 6.6.4 Treating CPU Interrupt Sources but Not DTC or DMAC Activating Sources
• Section 7 User Break Controller (UBC)
  • 7.1 Overview
    • 7.1.1 Features
    • 7.1.2 Block Diagram
    • 7.1.3 Register Configuration
  • 7.2 Register Descriptions
    • 7.2.1 User Break Address Register (UBAR)
    • 7.2.2 User Break Address Mask Register (UBAMR)
    • 7.2.3 User Break Bus Cycle Register (UBBR)
  • 7.3 Operation
    • 7.3.1 Flow of the User Break Operation
    • 7.3.2 Break on On-Chip Memory Instruction Fetch Cycle
    • 7.3.3 Program Counter (PC)Values Saved
  • 7.4 Use Examples
    • 7.4.1 Break on CPU Instruction Fetch Cycle
    • 7.4.2 Break on CPU Data Access Cycle
    • 7.4.3 Break on DMA/DTC Cycle
  • 7.5 Cautions on Use
    • 7.5.1 On-Chip Memory Instruction Fetch
    • 7.5.2 Instruction Fetch at Branches
    • 7.5.3 Contention between User Break and Exception Handling
    • 7.5.4 Break at Non-Delay Branch Instruction Jump Destination
• Section 8 Data Transfer Controller (DTC)
  • 8.1 Overview
    • 8.1.1 Features
    • 8.1.2 Block Diagram
    • 8.1.3 Register Configuration
  • 8.2 Register Description
    • 8.2.1 DTC Mode Register (DTMR)
    • 8.2.2 DTC Source Address Register (DTSAR)
    • 8.2.3 DTC Destination Address Register (DTDAR)
    • 8.2.4 DTC Initial Address Register (DTIAR)
    • 8.2.5 DTC Transfer Count Register A (DTCRA)
    • 8.2.6 DTC Transfer Count Register B (DTCRB)
    • 8.2.7 DTC Enable Registers (DTER)
    • 8.2.8 DTC Control/Status Register (DTCSR)
    • 8.2.9 DTC Information Base Register (DTBR)
  • 8.3 Operation
    • 8.3.1 Overview of Operation
    • 8.3.2 Activating Sources
    • 8.3.3 DTC Vector Table
    • 8.3.4 Register Information Placement
    • 8.3.5 Normal Mode
    • 8.3.6 Repeat Mode
    • 8.3.7 Block Transfer Mode
    • 8.3.8 Operation Timing
    • 8.3.9 DTC Execution State Counts
    • 8.3.10 DTC Usage Procedure
    • 8.3.11 DTC Use Example
  • 8.4 Cautions on Use
• Section 9 Cache Memory (CAC)
  • 9.1 Overview
    • 9.1.1 Features
    • 9.1.2 Block Diagram
    • 9.1.3 Register Configuration
  • 9.2 Register Explanation
    • 9.2.1 Cache Control Register (CCR)
  • 9.3 Address Array and Data Array
    • 9.3.1 Cache Address Array Read/Write Space
    • 9.3.2 Cache Data Array Read/Write Space
  • 9.4 Cautions on Use
    • 9.4.1 Cache Initialization
    • 9.4.2 Forced Access to Address Array and Data Array
    • 9.4.3 Cache Miss Penalty and Cache Fill Timing
    • 9.4.4 Cache Hit after Cache Miss
• Section 10 Bus State Controller (BSC)
  • 10.1 Overview
    • 10.1.1 Features
    • 10.1.2 Block Diagram
    • 10.1.3 Pin Configuration
    • 10.1.4 Register Configuration
    • 10.1.5 Address Map
  • 10.2 Description of Registers
    • 10.2.1 Bus Control Register 1 (BCR1)
    • 10.2.2 Bus Control Register 2 (BCR2)
    • 10.2.3 Wait Control Register 1 (WCR1)
    • 10.2.4 Wait Control Register 2 (WCR2)
    • 10.2.5 DRAM Area Control Register (DCR)
    • 10.2.6 Refresh Timer Control/Status Register (RTCSR)
    • 10.2.7 Refresh Timer Counter (RTCNT)
    • 10.2.8 Refresh Time Constant Register (RTCOR)
  • 10.3 Accessing Ordinary Space
    • 10.3.1 Basic Timing
    • 10.3.2 Wait State Control
    • 10.3.3 CS Assert Period Extension
  • 10.4 DRAM Access
    • 10.4.1 DRAM Direct Connection
    • 10.4.2 Basic Timing
    • 10.4.3 Wait State Control
    • 10.4.4 Burst Operation
    • 10.4.5 Refresh Timing
  • 10.5 Address/Data Multiplex I/O Space Access
    • 10.5.1 Basic Timing
    • 10.5.2 Wait State Control
    • 10.5.3 CS Assertion Extension
  • 10.6 Waits between Access Cycles
    • 10.6.1 Prevention of Data Bus Conflicts
    • 10.6.2 Simplification of Bus Cycle Start Detection
  • 10.7 Bus Arbitration
  • 10.8 Memory Connection Examples
  • 10.9 On-Chip Peripheral I/O Register Access
  • 10.10 CPU Operation when Program is in External Memory
• Section 11 Direct Memory Access Controller (DMAC)
  • 11.1 Overview
    • 11.1.1 Features
    • 11.1.2 Block Diagram
    • 11.1.3 Pin Configuration
    • 11.1.4 Register Configuration
  • 11.2 Register Descriptions
    • 11.2.1 DMA Source Address Registers 0 �3 (SAR0 �SAR3)
    • 11.2.2 DMA Destination Address Registers 0 �3 (DAR0 �DAR3)
    • 11.2.3 DMA Transfer Count Registers 0 �3 (DMATCR0 �DMATCR3)
    • 11.2.4 DMA Channel Control Registers 0 �3 (CHCR0 �CHCR3)
    • 11.2.5 DMAC Operation Register (DMAOR)
  • 11.3 Operation
    • 11.3.1 DMA Transfer Flow
    • 11.3.2 DMA Transfer Requests
    • 11.3.3 Channel Priority
    • 11.3.4 DMA Transfer Types
    • 11.3.5 Address Modes
    • 11.3.6 Dual Address Mode
    • 11.3.7 Bus Modes
    • 11.3.8 Relationship between Request Modes and Bus Modes by DMA Transfer Category
    • 11.3.9 Bus Mode and Channel Priority Order
    • 11.3.10 Number of Bus Cycle States and DREQ Pin Sample Timing
    • 11.3.11 Source Address Reload Function
    • 11.3.12 DMA Transfer Ending Conditions
    • 11.3.13 DMAC Access from CPU
  • 11.4 Examples of Use
    • 11.4.1 Example of DMA Transfer between On-Chip SCI and External Memory
    • 11.4.2 Example of DMA Transfer between External RAM and External Device with DACK
    • 11.4.3 Example of DMA Transfer between A/D Converter and On-Chip Memory (Address Reload On)(Excluding A Mask)
    • 11.4.4 Example of DMA Transfer between A/D Converter and Internal Memory (Address Reload On)(A Mask)
    • 11.4.5 Example of DMA Transfer between External Memory and SCI1 Send Side (Indirect Address On)
  • 11.5 Cautions on Use
• Section 12 Multifunction Timer Pulse Unit (MTU)
  • 12.1 Overview
    • 12.1.1 Features
    • 12.1.2 Block Diagram
    • 12.1.3 Pin Configuration
    • 12.1.4 Register Configuration
  • 12.2 MTU Register Descriptions
    • 12.2.1 Timer Control Register (TCR)
    • 12.2.2 Timer Mode Register (TMDR)
    • 12.2.3 Timer I/O Control Register (TIOR)
    • 12.2.4 Timer Interrupt Enable Register (TIER)
    • 12.2.5 Timer Status Register (TSR)
    • 12.2.6 Timer Counters (TCNT)
    • 12.2.7 Timer General Register (TGR)
    • 12.2.8 Timer Start Register (TSTR)
    • 12.2.9 Timer Synchro Register (TSYR)
    • 12.2.10 Timer Output Master Enable Register (TOER)
    • 12.2.11 Timer Output Control Register (TOCR)
    • 12.2.12 Timer Gate Control Register (TGCR)
    • 12.2.13 Timer Subcounter (TCNTS)
    • 12.2.14 Timer Dead Time Data Register (TDDR)
    • 12.2.15 Timer Period Data Register (TCDR)
    • 12.2.16 Timer Period Buffer Register (TCBR)
  • 12.3 Bus Master Interface
    • 12.3.1 16-Bit Registers
    • 12.3.2 8-Bit Registers
  • 12.4 Operation
    • 12.4.1 Overview
    • 12.4.2 Basic Functions
    • 12.4.3 Synchronous Operation
    • 12.4.4 Buffer Operation
    • 12.4.5 Cascade Connection Mode
    • 12.4.6 PWM Mode
    • 12.4.7 Phase Counting Mode
    • 12.4.8 Reset-Synchronized PWM Mode
    • 12.4.9 Complementary PWM Mode
  • 12.5 Interrupts
    • 12.5.1 Interrupt Sources and Priority Ranking
    • 12.5.2 DTC/DMAC Activation
    • 12.5.3 A/D Converter Activation
  • 12.6 Operation Timing
    • 12.6.1 Input/Output Timing
    • 12.6.2 Interrupt Signal Timing
  • 12.7 Notes and Precautions
    • 12.7.1 Input Clock Limitations
    • 12.7.2 Note on Cycle Setting
    • 12.7.3 Contention between TCNT Write and Clear
    • 12.7.4 Contention between TCNT Write and Increment
    • 12.7.5 Contention between Buffer Register Write and Compare Match
    • 12.7.6 Contention between TGR Read and Input Capture
    • 12.7.7 Contention between TGR Write and Input Capture
    • 12.7.8 Contention between Buffer Register Write and Input Capture
    • 12.7.9 Contention between TGR Write and Compare Match
    • 12.7.10 TCNT2 Write and Overflow/Underflow Contention in Cascade Connection
    • 12.7.11 Counter Value during Complementary PWM Mode Stop
    • 12.7.12 Buffer Operation Setting in Complementary PWM Mode
    • 12.7.13 Reset Sync PWM Mode Buffer Operation and Compare Match Flag
    • 12.7.14 Overflow Flags in Reset Sync PWM Mode
    • 12.7.15 Notes on Compare Match Flags in Complementary PWM Mode
    • 12.7.16 Contention between Overflow/Underflow and Counter Clearing
    • 12.7.17 Contention between TCNT Write and Overflow/Underflow
    • 12.7.18 Cautions on Transition from Normal Operation or PWM Mode 1 to Reset-Synchronous PWM Mode
    • 12.7.19 Output Level in Complementary PWM Mode and Reset-Synchronous PWM Mode
    • 12.7.20 Cautions on Using the Chopping Function in Complementary PWM Mode or Reset Synchronous PWM Mode (A Mask Excluded)
    • 12.7.21 Cautions on Carrying Out Buffer Operation of Channel 0 in PWM Mode (A Mask Excluded)
    • 12.7.22 Cautions on Restarting with Sync Clear of Another Channel in Complementary PWM Mode (A Mask Excluded)
  • 12.8 MTU Output Pin Initialization
    • 12.8.1 Operating Modes
    • 12.8.2 Reset Start Operation
    • 12.8.3 Operation in Case of Re-Setting Due to Error During Operation,Etc.
    • 12.8.4 Overview of Initialization Procedures and Mode Transitions in Case of Error during Operation,Etc.
  • 12.9 Port Output Enable (POE)
    • 12.9.1 Features
    • 12.9.2 Block Diagram
    • 12.9.3 Pin Configuration
    • 12.9.4 Register Configuration
  • 12.10 POE Register Descriptions
    • 12.10.1 Input Level Control/Status Register (ICSR)
    • 12.10.2 Output Level Control/Status Register (OCSR)
  • 12.11 Operation
    • 12.11.1 Input Level Detection Operation
    • 12.11.2 Output-Level Compare Operation
    • 12.11.3 Release from High-Impedance State
    • 12.11.4 POE timing
    • 12.11.5 Usage Notes
• Section 13 Watchdog Timer (WDT)
  • 13.1 Overview
    • 13.1.1 Features
    • 13.1.2 Block Diagram
    • 13.1.3 Pin Configuration
    • 13.1.4 Register Configuration
  • 13.2 Register Descriptions
    • 13.2.1 Timer Counter (TCNT)
    • 13.2.2 Timer Control/Status Register (TCSR)
    • 13.2.3 Reset Control/Status Register (RSTCSR)
    • 13.2.4 Register Access
  • 13.3 Operation
    • 13.3.1 Watchdog Timer Mode
    • 13.3.2 Interval Timer Mode
    • 13.3.3 Clearing the Standby Mode
    • 13.3.4 Timing of Setting the Overflow Flag (OVF)
    • 13.3.5 Timing of Setting the Watchdog Timer Overflow Flag (WOVF)
  • 13.4Notes on Use
    • 13.4.1 TCNT Write and Increment Contention
    • 13.4.2 Changing CKS2 �CKS0 Bit Values
    • 13.4.3 Changing between Watchdog Timer/Interval Timer Modes
    • 13.4.4 System Reset With WDTOVF
    • 13.4.5 Internal Reset with the Watchdog Timer
• Section 14 Serial Communication Interface (SCI)
  • 14.1 Overview
    • 14.1.1 Features
    • 14.1.2 Block Diagram
    • 14.1.3 Pin Configuration
    • 14.1.4 Register Configuration
  • 14.2 Register Descriptions
    • 14.2.1 Receive Shift Register (RSR)
    • 14.2.2 Receive Data Register (RDR)
    • 14.2.3 Transmit Shift Register (TSR)
    • 14.2.4 Transmit Data Register (TDR)
    • 14.2.5 Serial Mode Register (SMR)
    • 14.2.6 Serial Control Register (SCR)
    • 14.2.7 Serial Status Register (SSR)
    • 14.2.8 Bit Rate Register (BRR)
  • 14.3 Operation
    • 14.3.1 Overview
    • 14.3.2 Operation in Asynchronous Mode
    • 14.3.3 Multiprocessor Communication
    • 14.3.4 Clock Synchronous Operation
  • 14.4 SCI Interrupt Sources and the DMAC/DTC
  • 14.5 Notes on Use
    • 14.5.1 TDR Write and TDRE Flags
    • 14.5.2 Simultaneous Multiple Receive Errors
    • 14.5.3 Break Detection and Processing
    • 14.5.4 Sending a Break Signal
    • 14.5.5 Receive Error Flags and Transmitter Operation (Clock Synchronous Mode Only)
    • 14.5.6 Receive Data Sampling Timing and Receive Margin in the Asynchronous Mode
    • 14.5.7 Constraints on DMAC/DTC Use
    • 14.5.8 Cautions for Clock Synchronous External Clock Mode
    • 14.5.9 Caution for Clock Synchronous Internal Clock Mode
• Section 15 High Speed A/D Converter (Excluding A Mask)
  • 15.1 Overview
    • 15.1.1 Features
    • 15.1.2 Block Diagram
    • 15.1.3 Pin Configuration
    • 15.1.4 Register Configuration
  • 15.2 Register Descriptions
    • 15.2.1 A/D Data Registers A �H (ADDRA �ADDRH)
    • 15.2.2 A/D Control/Status Register (ADCSR)
    • 15.2.3 A/D Control Register (ADCR)
  • 15.3 Bus Master Interface
  • 15.4 Operation
    • 15.4.1 Select-Single Mode
    • 15.4.2 Select-Scan Mode
    • 15.4.3 Group-Single Mode
    • 15.4.4 Group-Scan Mode
    • 15.4.5 Buffer Operation
    • 15.4.6 Simultaneous Sampling Operation
    • 15.4.7 Conversion Start Modes
    • 15.4.8 Conversion Start by External Input
    • 15.4.9 A/D Conversion Time
  • 15.5 Interrupts
  • 15.6 Notes on Use
• Section 16 Mid-Speed A/D Converter (A Mask)
  • 16.1 Overview
    • 16.1.1 Features
    • 16.1.2 Block Diagram
    • 16.1.3 Pin Configuration
    • 16.1.4 Register Configuration
  • 16.2 Register Descriptions
    • 16.2.1 A/D Data Register A �D (ADDRA0 �ADDRD0,ADDRA1 �ADDRD1)
    • 16.2.2 A/D Control/Status Register (ADCSR0,ADCSR1)
    • 16.2.3 A/D Control Register (ADCR0,ADCR1)
  • 16.3 Interface with CPU
  • 16.4 Operation
    • 16.4.1 Single Mode (SCAN=0)
    • 16.4.2 Scan Mode (SCAN=1)
    • 16.4.3 Input Sampling and A/D Conversion Time
    • 16.4.4 External Trigger Input Timing
  • 16.5 Interrupt and DMA,DTC Transfer Requests
  • 16.6 A/D Conversion Precision Definitions
  • 16.7 Usage Notes
    • 16.7.1 Analog Voltage Settings
    • 16.7.2 Handling of Analog Input Pins
• Section 17 Compare Match Timer (CMT)
  • 17.1 Overview
    • 17.1.1 Features
    • 17.1.2 Block Diagram
    • 17.1.3 Register Configuration
  • 17.2 Register Descriptions
    • 17.2.1 Compare Match Timer Start Register (CMSTR)
    • 17.2.2 Compare Match Timer Control/Status Register (CMCSR)
    • 17.2.3 Compare Match Timer Counter (CMCNT)
    • 17.2.4 Compare Match Timer Constant Register (CMCOR)
  • 17.3 Operation
    • 17.3.1 Period Count Operation
    • 17.3.2 CMCNT Count Timing
  • 17.4 Interrupts
    • 17.4.1 Interrupt Sources and DTC Activation
    • 17.4.2 Compare Match Flag Set Timing
    • 17.4.3 Compare Match Flag Clear Timing
  • 17.5 Notes on Use
    • 17.5.1 Contention between CMCNT Write and Compare Match
    • 17.5.2 Contention between CMCNT Word Write and Incrementation
    • 17.5.3 Contention between CMCNT Byte Write and Incrementation
• Section 18 Pin Function Controller
  • 18.1 Overview
  • 18.2 Register Configuration
  • 18.3 Register Descriptions
    • 18.3.1 Port A I/O Register H (PAIORH)
    • 18.3.2 Port A I/O Register L (PAIORL)
    • 18.3.3 Port A Control Register H (PACRH)
    • 18.3.4 Port A Control Registers L1,L2 (PACRL1 and PACRL2)
    • 18.3.5 Port B I/O Register (PBIOR)
    • 18.3.6 Port B Control Registers (PBCR1 and PBCR2)
    • 18.3.7 Port C I/O Register (PCIOR)
    • 18.3.8 Port C Control Register (PCCR)
    • 18.3.9 Port D I/O Register H (PDIORH)
    • 18.3.10 Port D I/O Register L (PDIORL)
    • 18.3.11 Port D Control Registers H1,H2 (PDCRH1 and PDCRH2)
    • 18.3.12 Port D Control Register L (PDCRL)
    • 18.3.13 Port E I/O Register (PEIOR)
    • 18.3.14 Port E Control Registers 1,2 (PECR1 and PECR2)
    • 18.3.15 IRQOUT Function Control Register (IFCR)
  • 18.4 Cautions on Use
• Section 19 I/O Ports (I/O)
  • 19.1 Overview
  • 19.2 Port A
    • 19.2.1 Register Configuration
    • 19.2.2 Port A Data Register H (PADRH)
    • 19.2.3 Port A Data Register L (PADRL)
  • 19.3 Port B
    • 19.3.1 Register Configuration
    • 19.3.2 Port B Data Register (PBDR)
  • 19.4 Port C
    • 19.4.1 Register Configuration
    • 19.4.2 Port C Data Register (PCDR)
  • 19.5 Port D
    • 19.5.1 Register Configuration
    • 19.5.2 Port D Data Register H (PDDRH)
    • 19.5.3 Port D Data Register L (PDDRL)
  • 19.6 Port E
    • 19.6.1 Register Configuration
    • 19.6.2 Port E Data Register (PEDR)
  • 19.7 Port F
    • 19.7.1 Register Configuration
    • 19.7.2 Port F Data Register (PFDR)
• Section 20 64/128/256kB Mask ROM
  • 20.1 Overview
• Section 21 128kB PROM
  • 21.1 Overview
  • 21.2 PROM Mode
    • 21.2.1 PROM Mode Settings
    • 21.2.2 Socket Adapter Pin Correspondence and Memory Map
  • 21.3 PROM Programming
    • 21.3.1 Programming Mode Selection
    • 21.3.2 Write/Verify and Electrical Characteristics
    • 21.3.3 Cautions on Writing
    • 21.3.4 Post-Write Reliability
• Section 22 256kB Flash Memory (F-ZTAT)
  • 22.1 Features
  • 22.2 Overview
    • 22.2.1 Block Diagram
    • 22.2.2 Mode Transition Diagram
    • 22.2.3 Onboard Program Mode
    • 22.2.4 Flash Memory Emulation in RAM
    • 22.2.5 Differences between Boot Mode and User Program Mode
    • 22.2.6 Block Configuration
  • 22.3 Pin Configuration
  • 22.4 Register Configuration
  • 22.5 Description of Registers
    • 22.5.1 Flash Memory Control Register 1 (FLMCR1)
    • 22.5.2 Flash Memory Control Register 2 (FLMCR2)
    • 22.5.3 Erase Block Register 1 (EBR1)
    • 22.5.4 Erase Block Register 2 (EBR2)
    • 22.5.5 RAM Emulation Register (RAMER)
  • 22.6 On-Board Programming Mode
    • 22.6.1 Boot Mode
    • 22.6.2 User Program Mode
  • 22.7 Programming/Erasing Flash Memory
    • 22.7.1 Program Mode (n =1 for Addresses H'0000 �H'1FFFF,n =2 for Addresses H'20000 �H'3FFFF)
    • 22.7.2 Program-Verify Mode (n =1 for Addresses H'0000 �H'1FFFF,n =2 for Addresses H'20000 �H'3FFFF)
    • 22.7.3 Erase Mode (n =1 for Addresses H'0000 �H'1FFFF,n =2 for Addresses H'20000�H'3FFFF)
    • 22.7.4 Erase-Verify Mode (n =1 for Addresses H'00000 �H'1FFFF,n =2 for Addresses H'20000 �H'3FFFF)
  • 22.8 Protection
    • 22.8.1 Hardware Protection
    • 22.8.2 Software Protection
    • 22.8.3 Error Protection
  • 22.9 Flash Memory Emulation in RAM
  • 22.10 Note on Flash Memory Programming/Erasing
  • 22.11 Flash Memory Programmer Mode
    • 22.11.1 Socket Adapter Pin Correspondence Diagrams
    • 22.11.2 Programmer Mode Operation
    • 22.11.3 Memory Read Mode
    • 22.11.4 Auto-Program Mode
    • 22.11.5 Auto-Erase Mode
    • 22.11.6 Status Read Mode
    • 22.11.7 Status Polling
    • 22.11.8 Programmer Mode Transition Time
    • 22.11.9 Cautions Concerning Memory Programming
• Section 23 RAM
  • 23.1 Overview
  • 23.2 Operation
• Section 24 Power-Down State
  • 24.1 Overview
    • 24.1.1 Power-Down States
    • 24.1.2 Related Register
  • 24.2 Standby Control Register (SBYCR)
  • 24.3 Sleep Mode
    • 24.3.1 Transition to Sleep Mode
    • 24.3.2 Canceling Sleep Mode
  • 24.4 Standby Mode
    • 24.4.1 Transition to Standby Mode
    • 24.4.2 Canceling the Standby Mode
    • 24.4.3 Standby Mode Application Example
• Section 25 Electrical Characteristics (5V,28.7 MHz Version)
  • 25.1 Absolute Maximum Ratings
  • 25.2 DC Characteristics
  • 25.3 AC Characteristics
    • 25.3.1 Clock Timing
    • 25.3.2 Control Signal Timing
    • 25.3.3 Bus Timing
    • 25.3.4 Direct Memory Access Controller Timing
    • 25.3.5 Multifunction Timer Pulse Unit Timing
    • 25.3.6 I/O Port Timing
    • 25.3.7 Watchdog Timer Timing
    • 25.3.8 Serial Communication Interface Timing
    • 25.3.9 High-speed A/D Converter Timing (excluding A mask)
    • 25.3.10 Mid-speed Converter Timing (A mask)
    • 25.3.11 Measuring Conditions for AC Characteristics
  • 25.4 A/D Converter Characteristics
• Section 26 Electrical Characteristics (3.3V,16.7 MHz Version)
  • 26.1 Absolute Maximum Ratings
  • 26.2 DC Characteristics
  • 26.3 AC Characteristics
    • 26.3.1 Clock Timing
    • 26.3.2 Control Signal Timing
    • 26.3.3 Bus Timing
    • 26.3.4 Direct Memory Access Controller Timing
    • 26.3.5 Multifunction Timer Pulse Unit Timing
    • 26.3.6 I/O Port Timing
    • 26.3.7 Watchdog Timer Timing
    • 26.3.8 Serial Communication Interface Timing
    • 26.3.9 High-speed A/D Converter Timing (excluding A mask)
    • 26.3.10 Mid-speed Converter Timing (A mask)
    • 26.3.11 Measurement Conditions for AC Characteristic
  • 26.4 A/D Converter Characteristics
• Appendix A On-Chip Supporting Module Registers
  • A.1 Addresses
• Appendix B Block Diagrams
• Appendix C Pin States
• Appendix D Notes when Converting the F �ZTAT Application Software to the Mask-ROM Versions
• Appendix E Product Code Lineup
• Appendix F Package Dimensions
• Colophon