Document Outline

Cover
Cautions
Preface
List of Items Revised or Added for This Version
Contents
Section 1 Overview
- 1.1 SuperH Microcomputer Features
- 1.2 Block Diagram
- 1.3 Pin Descriptions
  - 1.3.1 Pin Arrangement
  - 1.3.2 Pin Functions
  - 1.3.3 Pin Layout by Mode
Section 2 CPU
- 2.1 Register Configuration
  - 2.1.1 General Registers (Rn)
  - 2.1.2 Control Registers
  - 2.1.3 System Registers
  - 2.1.4 Initial Values of Registers
- 2.2 Data Formats
  - 2.2.1 Data Format in Registers
  - 2.2.2 Data Format in Memory
  - 2.2.3 Immediate Data Format
- 2.3 Instruction Features
  - 2.3.1 RISC-Type Instruction Set
  - 2.3.2 Addressing Modes
  - 2.3.3 Instruction Formats
- 2.4 Instruction Set
  - 2.4.1 Instruction Set by Classification
  - 2.4.2 Operation Code Map
- 2.5 CPU State
  - 2.5.1 State Transitions
  - 2.5.2 Power-Down State
Section 3 Operating Modes
- 3.1 Types of Operating Modes and Their Selection
- 3.2 Operating Mode Descriptions
  - 3.2.1 Mode 0 (MCU Mode 0)
  - 3.2.2 Mode 1 (MCU Mode 1)
  - 3.2.3 Mode 2 (MCU Mode 2)
  - 3.2.4 Mode 7 (PROM Mode)
Section 4 Exception Handling
- 4.1 Overview
  - 4.1.1 Exception Handling Types and Priorities
  - 4.1.2 Exception Handling Operation
  - 4.1.3 Exception Vector Table
- 4.2 Resets
  - 4.2.1 Reset Types
  - 4.2.2 Power-On Reset
  - 4.2.3 Manual Reset
- 4.3 Address Errors
  - 4.3.1 Address Error Sources
  - 4.3.2 Address Error Exception Handling
- 4.4 Interrupts
  - 4.4.1 Interrupt Sources
  - 4.4.2 Interrupt Priority Rankings
  - 4.4.3 Interrupt Exception Handling
- 4.5 Instruction Exceptions
  - 4.5.1 Types of Instruction Exceptions
  - 4.5.2 Trap Instruction
  - 4.5.3 Illegal Slot Instruction
  - 4.5.4 General Illegal Instructions
- 4.6 Cases in which Exceptions are Not Accepted
  - 4.6.1 Immediately after Delayed Branch Instruction
  - 4.6.2 Immediately after Interrupt-Disabling Instruction
- 4.7 Stack Status after Exception Handling
- 4.8 Notes
  - 4.8.1 Value of the Stack Pointer (SP)
  - 4.8.2 Value of the Vector Base Register (VBR)
  - 4.8.3 Address Errors Caused by Stacking During Address Error Exception Handling
Section 5 Interrupt Controller (INTC)
- 5.1 Overview
  - 5.1.1 Features
  - 5.1.2 Block Diagram
  - 5.1.3 Pin Configuration
  - 5.1.4 Registers
- 5.2 Interrupt Sources
  - 5.2.1 NMI Interrupts
  - 5.2.2 User Break Interrupt
  - 5.2.3 IRQ Interrupts
  - 5.2.4 On-Chip Interrupts
  - 5.2.5 Interrupt Exception Vectors and Priority Rankings
- 5.3 Register Descriptions
  - 5.3.1 Interrupt Priority Registers A …E (IPRA …IPRE)
  - 5.3.2 Interrupt Control Register (ICR)
- 5.4 Interrupt Operation
  - 5.4.1 Interrupt Sequence
  - 5.4.2 Stack after Interrupt Exception Handling
- 5.5 Interrupt Response Time
- 5.6 Usage Notes
Section 6 User Break Controller (UBC)
- 6.1 Overview
  - 6.1.1 Features
  - 6.1.2 Block Diagram
  - 6.1.3 Register Configuration
- 6.2 Register Descriptions
  - 6.2.1 Break Address Registers (BAR)
  - 6.2.2 Break Address Mask Register (BAMR)
  - 6.2.3 Break Bus Cycle Register (BBR)
- 6.3 Operation
  - 6.3.1 Flow of User Break Operation
  - 6.3.2 Break on Instruction Fetch Cycles to On-Chip Memory
  - 6.3.3 Program Counter (PC)Value Saved in User Break Interrupt Exception Processing
- 6.4 Setting User Break Conditions
- 6.5 Notes
  - 6.5.1 On-Chip Memory Instruction Fetch
  - 6.5.2 Instruction Fetch at Branches
  - 6.5.3 Instruction Fetch Break
Section 7 Clock Pulse Generator (CPG)
- 7.1 Overview
- 7.2 Clock Source
  - 7.2.1 Connecting a Crystal Resonator
  - 7.2.2 External Clock Input
- 7.3 Usage Notes
Section 8 Bus State Controller (BSC)
- 8.1 Overview
  - 8.1.1 Features
  - 8.1.2 Block Diagram
  - 8.1.3 Pin Configuration
  - 8.1.4 Register Configuration
  - 8.1.5 Overview of Areas
- 8.2 Register Descriptions
  - 8.2.1 Bus Control Register (BCR)
  - 8.2.2 Wait State Control Register 1 (WCR1)
  - 8.2.3 Wait State Control Register 2 (WCR2)
  - 8.2.4 Wait State Control Register 3 (WCR3)
  - 8.2.5 DRAM Area Control Register (DCR)
  - 8.2.6 Refresh Control Register (RCR)
  - 8.2.7 Refresh Timer Control/Status Register (RTCSR)
  - 8.2.8 Refresh Timer Counter (RTCNT)
  - 8.2.9 Refresh Time Constant Register (RTCOR)
  - 8.2.10 Parity Control Register (PCR)
  - 8.2.11 Notes on Register Access
- 8.3 Address Space Subdivision
  - 8.3.1 Address Spaces and Areas
  - 8.3.2 Bus Width
  - 8.3.3 Chip Select Signals (CS0 …CS7 )
  - 8.3.4 Shadows
  - 8.3.5 Area Descriptions
- 8.4 Accessing External Memory Space
  - 8.4.1 Basic Timing
  - 8.4.2 Wait State Control
  - 8.4.3 Byte Access Control
- 8.5 DRAM Interface Operation
  - 8.5.1 DRAM Address Multiplexing
  - 8.5.2 Basic Timing
  - 8.5.3 Wait State Control
  - 8.5.4 Byte Access Control
  - 8.5.5 DRAM Burst Mode
  - 8.5.6 Refresh Control
- 8.6 Address/Data Multiplexed I/O Space Access
  - 8.6.1 Basic Timing
  - 8.6.2 Wait State Control
  - 8.6.3 Byte Access Control
- 8.7 Parity Check and Generation
- 8.8 Warp Mode
- 8.9 Wait State Control
- 8.10 Bus Arbitration
  - 8.10.1 Operation of Bus Arbitration
  - 8.10.2 BACK Operation
- 8.11 Usage Notes
  - 8.11.1 Usage Notes on Manual Reset
  - 8.11.2 Usage Notes on Parity Data Pins DPH and DPL
  - 8.11.3 Maximum Number of States from BREQ Input to Bus Release
Section 9 Direct Memory Access Controller (DMAC)
- 9.1 Overview
  - 9.1.1 Features
  - 9.1.2 Block Diagram
  - 9.1.3 Pin Configuration
  - 9.1.4 Register Configuration
- 9.2 Register Descriptions
  - 9.2.1 DMA Source Address Registers 0 …3 (SAR0 …SAR3)
  - 9.2.2 DMA Destination Address Registers 0 …3 (DAR0 …DAR3)
  - 9.2.3 DMA Transfer Count Registers 0 …3 (TCR0 …TCR3)
  - 9.2.4 DMA Channel Control Registers 0 …3 (CHCR0 …CHCR3)
  - 9.2.5 DMA Operation Register (DMAOR)
- 9.3 Operation
  - 9.3.1 DMA Transfer Flow
  - 9.3.2 DMA Transfer Requests
  - 9.3.3 Channel Priority
  - 9.3.4 DMA Transfer Types
  - 9.3.5 Number of Bus Cycle States and DREQ Pin Sample Timing
  - 9.3.6 DMA Transfer Ending Conditions
- 9.4 Examples of Use
  - 9.4.1 DMA Transfer between On-Chip RAM and Memory-Mapped External Device
  - 9.4.2 Example of DMA Transfer between On-Chip SCI and External Memory
  - 9.4.3 Example of DMA Transfer Between On-Chip A/D Converter and External Memory
- 9.5 Usage Notes
Section 10 16-Bit Integrated Timer Pulse Unit (ITU)
- 10.1 Overview
  - 10.1.1 Features
  - 10.1.2 Block Diagram
  - 10.1.3 Input/Output Pins
  - 10.1.4 Register Configuration
- 10.2 ITU Register Descriptions
  - 10.2.1 Timer Start Register (TSTR)
  - 10.2.2 Timer Synchro Register (TSNC)
  - 10.2.3 Timer Mode Register (TMDR)
  - 10.2.4 Timer Function Control Register (TFCR)
  - 10.2.5 Timer Output Control Register (TOCR)
  - 10.2.6 Timer Counters (TCNT)
  - 10.2.7 General Registers A and B (GRA and GRB)
  - 10.2.8 Buffer Registers A and B (BRA,BRB)
  - 10.2.9 Timer Control Register (TCR)
  - 10.2.10 Timer I/O Control Register (TIOR)
  - 10.2.11 Timer Status Register (TSR)
  - 10.2.12 Timer Interrupt Enable Register (TIER)
- 10.3 CPU Interface
  - 10.3.1 16-Bit Accessible Registers
  - 10.3.2 8-Bit Accessible Registers
- 10.4 Operation
  - 10.4.1 Overview
  - 10.4.2 Basic Functions
  - 10.4.3 Synchronizing Mode
  - 10.4.4 PWM Mode
  - 10.4.5 Reset-Synchronized PWM Mode
  - 10.4.6 Complementary PWM Mode
  - 10.4.7 Phase Counting Mode
  - 10.4.8 Buffer Mode
  - 10.4.9 ITU Output Timing
- 10.5 Interrupts
  - 10.5.1 Timing of Setting Status Flags
  - 10.5.2 Status Flag Clear Timing
  - 10.5.3 Interrupt Sources and DMAC Activation
- 10.6 Notes and Precautions
  - 10.6.1 Contention between TCNT Write and Clear
  - 10.6.2 Contention between TCNT Word Write and Increment
  - 10.6.3 Contention between TCNT Byte Write and Increment
  - 10.6.4 Contention between GR Write and Compare Match
  - 10.6.5 Contention between TCNT Write and Overflow/Underflow
  - 10.6.6 Contention between General Register Read and Input Capture
  - 10.6.7 Contention Between Counter Clearing by Input Capture and Counter Increment
  - 10.6.8 Contention between General Register Write and Input Capture
  - 10.6.9 Note on Waveform Cycle Setting
  - 10.6.10 Contention between BR Write and Input Capture
  - 10.6.11 Note on Writing in Synchronizing Mode
  - 10.6.12 Note on Setting Reset-Synchronized PWM Mode/Complementary PWM Mode
  - 10.6.13 Clearing Complementary PWM Mode
  - 10.6.14 Note on Counter Clearing by Input Capture
  - 10.6.15 ITU Operating Modes
Section 11 Programmable Timing Pattern Controller (TPC)
- 11.1 Overview
  - 11.1.1 Features
  - 11.1.2 Block Diagram
  - 11.1.3 Input/Output Pins
  - 11.1.4 Registers
- 11.2 Register Descriptions
  - 11.2.1 Port B Control Registers 1 and 2 (PBCR1,PCBR2)
  - 11.2.2 Port B Data Register (PBDR)
  - 11.2.3 Next Data Register A (NDRA)
  - 11.2.4 Next Data Register B (NDRB)
  - 11.2.5 Next Data Enable Register A (NDERA)
  - 11.2.6 Next Data Enable Register B (NDERB)
  - 11.2.7 TPC Output Control Register (TPCR)
  - 11.2.8 TPC Output Mode Register (TPMR)
- 11.3 Operation
  - 11.3.1 Overview
  - 11.3.2 Output Timing
  - 11.3.3 Examples of Use of Ordinary TPC Output
  - 11.3.4 TPC Output Non-Overlap Operation
  - 11.3.5 TPC Output by Input Capture
- 11.4 Usage Notes
  - 11.4.1 Non-Overlap Operation
Section 12 Watchdog Timer (WDT)
- 12.1 Overview
  - 12.1.1 Features
  - 12.1.2 Block Diagram
  - 12.1.3 Pin Configuration
  - 12.1.4 Register Configuration
- 12.2 Register Descriptions
  - 12.2.1 Timer Counter (TCNT)
  - 12.2.2 Timer Control/Status Register (TCSR)
  - 12.2.3 Reset Control/Status Register (RSTCSR)
  - 12.2.4 Notes on Register Access
- 12.3 Operation
  - 12.3.1 Operation in Watchdog Timer Mode
  - 12.3.2 Operation in Interval Timer Mode
  - 12.3.3 Operation in Standby Mode
  - 12.3.4 Timing of Overflow Flag (OVF)Setting
  - 12.3.5 Timing of Watchdog Timer Overflow Flag (WOVF)Setting
- 12.4Usage Notes
  - 12.4.1 TCNT Write and Increment Contention
  - 12.4.2 Changing CKS2 …CKS0 Bit Values
  - 12.4.3 Changing Watchdog Timer/Interval Timer Modes
  - 12.4.4 System Reset With WDTOVF
  - 12.4.5 Internal Reset With Watchdog Timer
Section 13 Serial Communication Interface (SCI)
- 13.1 Overview
  - 13.1.1 Features
  - 13.1.2 Block Diagram
  - 13.1.3 Input/Output Pins
  - 13.1.4 Register Configuration
- 13.2 Register Descriptions
  - 13.2.1 Receive Shift Register
  - 13.2.2 Receive Data Register
  - 13.2.3 Transmit Shift Register
  - 13.2.4 Transmit Data Register
  - 13.2.5 Serial Mode Register
  - 13.2.6 Serial Control Register
  - 13.2.7 Serial Status Register
  - 13.2.8 Bit Rate Register (BRR)
- 13.3 Operation
  - 13.3.1 Overview
  - 13.3.2 Operation in Asynchronous Mode
  - 13.3.3 Multiprocessor Communication
  - 13.3.4 Synchronous Operation
- 13.4 SCI Interrupt Sources and the DMAC
- 13.5 Usage Notes
Section 14 A/D Converter
- 14.1 Overview
  - 14.1.1 Features
  - 14.1.2 Block Diagram
  - 14.1.3 Configuration of Input Pins
  - 14.1.4 Configuration of A/D Registers
- 14.2 Register Descriptions
  - 14.2.1 A/D Data Registers A …D (ADDRA …ADDRD)
  - 14.2.2 A/D Control/Status Register (ADCSR)
  - 14.2.3 A/D Control Register (ADCR)
- 14.3 CPU Interface
- 14.4 Operation
  - 14.4.1 Single Mode (SCAN =0)
  - 14.4.2 Scan Mode (SCAN =1)
  - 14.4.3 Input Sampling Time and A/D Conversion Time
  - 14.4.4 A/D Conversion Start by External Trigger Input
- 14.5 Interrupts and DMA Transfer Requests
- 14.6 Definitions of A/D Conversion Accuracy
- 14.7 A/D Converter Usage Notes
  - 14.7.1 Setting Analog Input Voltage
  - 14.7.2 Handling of Analog Input Pins
  - 14.7.3 Switchover between Analog Input and General Port Functions
Section 15 Pin Function Controller (PFC)
- 15.1 Overview
- 15.2 Register Configuration
- 15.3 Register Descriptions
  - 15.3.1 Port A I/O Register (PAIOR)
  - 15.3.2 Port A Control Registers (PACR1 and PACR2)
  - 15.3.3 Port B I/O Register (PBIOR)
  - 15.3.4 Port B Control Registers (PBCR1 and PBCR2)
  - 15.3.5 Column Address Strobe Pin Control Register (CASCR)
Section 16 I/O Ports (I/O)
- 16.1 Overview
- 16.2 Port A
  - 16.2.1 Register Configuration
  - 16.2.2 Port A Data Register (PADR)
- 16.3 Port B
  - 16.3.1 Register Configuration
  - 16.3.2 Port B Data Register (PBDR)
- 16.4 Port C
  - 16.4.1 Register Configuration
  - 16.4.2 Port C Data Register (PCDR)
Section 17 ROM
- 17.1 Overview
- 17.2PROM Mode
  - 17.2.1 Setting PROM Mode
  - 17.2.2 Socket Adapter Pin Correspondence and Memory Map
- 17.3 PROM Programming
  - 17.3.1 Selecting the Programming Mode
  - 17.3.2 Write/Verify and Electrical Characteristics
  - 17.3.3 Notes on Writing
  - 17.3.4 Reliability after Writing
Section 18 RAM
- 18.1 Overview
- 18.2 Operation
Section 19 Power-Down State
- 19.1 Overview
  - 19.1.1 Power-Down Modes
  - 19.1.2 Register
- 19.2 Standby Control Register (SBYCR)
- 19.3 Sleep Mode
  - 19.3.1 Transition to Sleep Mode
  - 19.3.2 Exiting Sleep Mode
- 19.4 Standby Mode
  - 19.4.1 Transition to Standby Mode
  - 19.4.2 Exiting Standby Mode
  - 19.4.3 Standby Mode Application
Section 20 Electrical Characteristics
- 20.1 SH7032 and SH7034 Electrical Characteristics
  - 20.1.1 Absolute Maximum Ratings
  - 20.1.2 DC Characteristics
  - 20.1.3 AC Characteristics
    - (1)Clock Timing
    - (2)Control Signal Timing
    - (3)Bus Timing
    - (4)DMAC Timing
    - (5)16-bit Integrated Timer Pulse Unit Timing
    - (6)Programmable Timing Pattern Controller and I/O Port Timing
    - (7)Watchdog Timer Timing
    - (8)Serial Communication Interface Timing
    - (9)A/D Converter Timing
    - (10)AC Characteristics Test Conditions
  - 20.1.4 A/D Converter Characteristics
- 20.2 SH7034B 3.3 V 12.5 MHz Version and 20 MHz Version Electrical Characteristics
  - 20.2.1 Absolute Maximum Ratings
  - 20.2.2 DC Characteristics
  - 20.2.3 AC Characteristics
    - (1)Clock Timing
    - (2)Control Signal Timing
    - (3)Bus Timing
    - (4)DMAC Timing
    - (5)16-bit Integrated Timer Pulse Unit Timing
    - (6)Programmable Timing Pattern Controller and I/O Port Timing
    - (7)Watchdog Timer Timing
    - (8)Serial Communication Interface Timing
    - (9)A/D Converter Timing
    - (10)AC Characteristics Test Conditions
  - 20.2.4 A/D Converter Characteristics
Appendix A On-Chip Supporting Module Registers
- A.1 List of Registers
- A.2 Register Tables
  - A.2.1 Serial Mode Register (SMR)SCI
  - A.2.2 Bit Rate Register (BRR)SCI
  - A.2.3 Serial Control Register (SCR)SCI
  - A.2.4 Transmit Data Register (TDR)SCI
  - A.2.5 Serial Status Register (SSR)SCI
  - A.2.6 Receive Data Register (RDR)SCI
  - A.2.7 A/D Data Register AH …DL (ADDRAH …ADDRL)A/D
  - A.2.8 A/D Control/Status Register (ADCSR)A/D
  - A.2.9 A/D Control Register (ADCR)A/D
  - A.2.10 Timer Start Register (TSTR)ITU
  - A.2.11 Timer Synchronization Register (TSNC)ITU
  - A.2.12 Timer Mode Register (TMDR)ITU
  - A.2.13 Timer Function Control Register (TFCR)ITU
  - A.2.14 Timer Control Registers 0 …4 (TCR0 …TCR4)ITU
  - A.2.15 Timer I/O Control Registers 0 …4 (TIOR0 …TIOR4)ITU
  - A.2.16 Timer Interrupt Enable Registers 0 …4 (TIER0 …TIER4)ITU
  - A.2.17 Timer Status Registers 0 …4 (TSR0 …TSR4)ITU
  - A.2.18 Timer Counter 0 …4 (TCNT0 …TCNT4)ITU
  - A.2.19 General Registers A0 …4 (GRA0 …GRA4)ITU
  - A.2.20 General Registers B0 …4 (GRB0 …GRB4)ITU
  - A.2.21 Buffer Registers A3,4 (BRA3,BRA4)ITU
  - A.2.22 Buffer Registers B3,4 (BRB3,BRB4)ITU
  - A.2.23 Timer Output Control Register (TOCR)ITU
  - A.2.24 DMA Source Address Registers 0 …3 (SAR0 …SAR3)DMAC
  - A.2.25 DMA Destination Address Registers 0 …3 (DAR0 …DAR3)DMAC
  - A.2.26 DMA Transfer Count Registers 0 …3 (TCR0 …TCR3)DMAC
  - A.2.27 DMA Channel Control Registers 0 …3 (CHCR0 …CHCR3)DMAC
  - A.2.28 DMA Operation Registers (DMAOR)DMAC
  - A.2.29 Interrupt Priority Setting Register A (IPRA)INTC
  - A.2.30 Interrupt Priority Setting Register B (IPRB)INTC
  - A.2.31 Interrupt Priority Setting Register C (IPRC)INTC
  - A.2.32 Interrupt Priority Setting Register D (IPRD)INTC
  - A.2.33 Interrupt Priority Setting Register E (IPRE)INTC
  - A.2.34 Interrupt Control Register (ICR)INTC
  - A.2.35 Break Address Register H (BARH)UBC
  - A.2.36 Break Address Register L (BARL)UBC
  - A.2.37 Break Address Mask Register H (BAMRH)UBC
  - A.2.38 Break Address Mask Register L (BAMRL)UBC
  - A.2.39 Break Bus Cycle Register (BBR)UBC
  - A.2.40 Bus Control Register (BCR)BSC
  - A.2.41 Wait State Control Register 1 (WCR1)BSC
  - A.2.42 Wait State Control Register 2 (WCR2)BSC
  - A.2.43 Wait State Control Register 3 (WCR3)BSC
  - A.2.44 DRAM Area Control Register (DCR)BSC
  - A.2.45 Parity Control Register (PCR)BSC
  - A.2.46 Refresh Control Register (RCR)BSC
  - A.2.47 Refresh Timer Control/Status Register (RTCSR)BSC
  - A.2.48 Refresh Timer Counter (RTCNT)BSC
  - A.2.49 Refresh Timer Constant Register (RTCOR)BSC
  - A.2.50 Timer Control/Status Register (TCSR)WDT
  - A.2.51 Timer Counter (TCNT)WDT
  - A.2.52 Reset Control/Status Register (RSTCSR)WDT
  - A.2.53 Standby Control Register (SBYCR)Power-Down State
  - A.2.54 Port A Data Register (PADR)Port A
  - A.2.55 Port B Data Register (PBDR)Port B
  - A.2.56 Port C Data Register (PCDR)Port C
  - A.2.57 Port A I/O Register (PAIOR)PFC
  - A.2.58 Port B I/O Register (PBIOR)PFC
  - A.2.59 Port A Control Register 1 (PACR1)PFC
  - A.2.60 Port A Control Register 2 (PACR2)PFC
  - A.2.61 Port B Control Register 1 (PBCR1)PFC
  - A.2.62 Port B Control Register 2 (PBCR2)PFC
  - A.2.63 Column Address Strobe Pin Control Register (CASCR)PFC
  - A.2.64 TPC Output Mode Register (TPMR)TPC
  - A.2.65 TPC Output Control Register (TPCR)TPC
  - A.2.66 Next Data Enable Register A (NDERA)TPC
  - A.2.67 Next Data Enable Register B (NDERB)TPC
  - A.2.68 Next Data Register A (NDRA)TPC (When the Output Triggers of TPC Output Groups 0 and 1 are the Same)
  - A.2.69 Next Data Register A (NDRA)TPC (When the Output Triggers of TPC Output Groups 0 and 1 are the Same)
  - A.2.70 Next Data Register A (NDRA)TPC (When the Output Triggers of TPC Output Groups 0 and 1 are Different)
  - A.2.71 Next Data Register A (NDRA)TPC (When the Output Triggers of TPC Output Groups 0 and 1 are Different)
  - A.2.72 Next Data Register B (NDRB)TPC (When the Output Triggers of TPC Output Groups 2 and 3 are the Same)
  - A.2.73 Next Data Register B (NDRB)TPC (When the Output Triggers of TPC Output Groups 2 and 3 are the Same)
  - A.2.74 Next Data Register B (NDRB)TPC (When the Output Triggers of TPC Output Groups 2 and 3 are Different)
  - A.2.75 Next Data Register B (NDRB)TPC (When the Output Triggers of TPC Output Groups 2 and 3 are Different)
- A.3 Register Status in Reset and Power-Down States
Appendix B Pin States
Appendix C Package Dimensions
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