Document Outline
- Cover
- Cautions
- General Precautions on the Handling of Products
- Configuration of this Manual
- Preface
- List of Items Revised or Added for This Version
- Contents
- Section 1 Overview
- 1.1 Overview
- 1.2 Internal Block Diagram
- 1.3 Pin Arrangement
- 1.4 Pin Functions in Each Operating Mode
- 1.5 Pin Functions
- Section 2 CPU
- 2.1 Features
- 2.1.1 Differences between H8S/2600 CPU and H8S/2000 CPU
- 2.1.2 Differences from H8/300 CPU
- 2.1.3 Differences from H8/300H CPU
- 2.2 CPU Operating Modes
- 2.2.1 Normal Mode
- 2.2.2 Advanced Mode
- 2.3 Address Space
- 2.4 Register Configuration
- 2.4.1 General Registers
- 2.4.2 Program Counter (PC)
- 2.4.3 Extended Control Register (EXR)
- 2.4.4 Condition-Code Register (CCR)
- 2.4.5 Initial Register Values
- 2.5 Data Formats
- 2.5.1 General Register Data Formats
- 2.5.2 Memory Data Formats
- 2.6 Instruction Set
- 2.6.1 Table of Instructions Classified by Function
- 2.6.2 Basic Instruction Formats
- 2.7 Addressing Modes and Effective Address Calculation
- 2.7.1 Register DirectRn
- 2.7.2 Register Indirect@ERn
- 2.7.3 Register Indirect with Displacement@(d:16, ERn) or @(d:32, ERn)
- 2.7.4 Register Indirect with Post-Increment or Pre-Decrement@ERn+ or @-ERn
- 2.7.5 Absolute Address@aa:8, @aa:16, @aa:24, or @aa:32
- 2.7.6 Immediate#xx:8, #xx:16, or #xx:32
- 2.7.7 Program-Counter Relative@(d:8, PC) or @(d:16, PC)
- 2.7.8 Memory Indirect@@aa:8
- 2.7.9 Effective Address Calculation
- 2.8 Processing States
- 2.9 Usage Notes
- 2.9.1 Note on TAS Instruction Usage
- 2.9.2 STM/LTM Instruction Usage
- 2.9.3 Note on Bit Manipulation Instructions
- Section 3 MCU Operating Modes
- 3.1 Operating Mode Selection
- 3.2 Register Descriptions
- 3.2.1 Mode Control Register (MDCR)
- 3.2.2 System Control Register (SYSCR)
- 3.3 Operating Mode Descriptions
- 3.3.1 Mode 4
- 3.3.2 Mode 5
- 3.3.3 Mode 6
- 3.3.4 Mode 7
- 3.3.5 Pin Functions
- 3.4 Memory Map in Each Operating Mode
- Section 4 Exception Handling
- 4.1 Exception Handling Types and Priority
- 4.2 Exception Sources and Exception Vector Table
- 4.3 Reset
- 4.3.1 Reset Types
- 4.3.2 Reset Exception Handling
- 4.3.3 Interrupts after Reset
- 4.3.4 State of On-Chip Peripheral Modules after Reset Release
- 4.4 Traces
- 4.5 Interrupts
- 4.6 Trap Instruction
- 4.7 Stack Status after Exception Handling
- 4.8 Notes on Use of the Stack
- Section 5 Interrupt Controller
- 5.1 Features
- 5.2 Input/Output Pins
- 5.3 Register Descriptions
- 5.3.1 Interrupt Priority Registers A to G, I to K, M (IPRA to IPRG, IPRI to IPRK, IPRM)
- 5.3.2 IRQ Enable Register (IER)
- 5.3.3 IRQ Sense Control Registers H and L (ISCRH, ISCRL)
- 5.3.4 IRQ Status Register (ISR)
- 5.4 Interrupt Sources
- 5.4.1 External Interrupts
- 5.4.2 Internal Interrupts
- 5.5 Interrupt Exception Handling Vector Table
- 5.6 Interrupt Control Modes and Interrupt Operation
- 5.6.1 Interrupt Control Mode 0
- 5.6.2 Interrupt Control Mode 2
- 5.6.3 Interrupt Exception Handling Sequence
- 5.6.4 Interrupt Response Times
- 5.6.5 DTC Activation by Interrupt
- 5.7 Usage Notes
- 5.7.1 Contention between Interrupt Generation and Disabling
- 5.7.2 Instructions that Disable Interrupts
- 5.7.3 Times when Interrupts are Disabled
- 5.7.4 Interrupts during Execution of EEPMOV Instruction
- Section 6 Bus Controller
- 6.1 Features
- 6.2 Input/Output Pins
- 6.3 Register Descriptions
- 6.3.1 Bus Width Control Register (ABWCR)
- 6.3.2 Access State Control Register (ASTCR)
- 6.3.3 Wait Control Registers H and L (WCRH, WCRL)
- 6.3.4 Bus Control Register H (BCRH)
- 6.3.5 Bus Control Register L (BCRL)
- 6.3.6 Pin Function Control Register (PFCR)
- 6.4 Bus Control
- 6.4.1 Area Divisions
- 6.4.2 Bus Specifications
- 6.4.3 Bus Interface for Each Area
- 6.4.4 Chip Select Signals
- 6.5 Basic Timing
- 6.5.1 On-Chip Memory (ROM, RAM) Access Timing
- 6.5.2 On-Chip Peripheral Module Access Timing
- 6.5.3 External Address Space Access Timing
- 6.6 Basic Bus Interface
- 6.6.1 Data Size and Data Alignment
- 6.6.2 Valid Strobes
- 6.6.3 Basic Timing
- 6.6.4 Wait Control
- 6.7 Burst ROM Interface
- 6.7.1 Basic Timing
- 6.7.2 Wait Control
- 6.8 Idle Cycle
- 6.9 Bus Release
- 6.10 Bus Arbitration
- 6.10.1 Operation
- 6.10.2 Bus Transfer Timing
- 6.10.3 External Bus Release Usage Note
- 6.11 Resets and the Bus Controller
- Section 7 DMA Controller
- 7.1 Features
- 7.2 Register Configuration
- 7.3 Register Descriptions
- 7.3.1 Memory Address Registers (MAR)
- 7.3.2 I/O Address Register (IOAR)
- 7.3.3 Execute Transfer Count Register (ETCR)
- 7.3.4 DMA Control Register (DMACR)
- 7.3.5 DMA Band Control Register (DMABCR)
- 7.3.6 DMA Write Enable Register (DMAWER)
- 7.4 Operation
- 7.4.1 Transfer Modes
- 7.4.2 Sequential Mode
- 7.4.3 Idle Mode
- 7.4.4 Repeat Mode
- 7.4.5 Normal Mode
- 7.4.6 Block Transfer Mode
- 7.4.7 DMAC Activation Sources
- 7.4.8 Basic DMAC Bus Cycles
- 7.4.9 DMAC Bus Cycles (Dual Address Mode)
- 7.4.10 DMAC Multi-Channel Operation
- 7.4.11 Relation between the DMAC, External Bus Requests, Refresh Cycles, and the DTC
- 7.4.12 NMI Interrupts and DMAC
- 7.4.13 Forced Termination of DMAC Operation
- 7.4.14 Clearing Full Address Mode
- 7.5 Interrupts
- 7.6 Usage Notes
- 7.6.1 DMAC Register Access during Operation
- 7.6.2 Module Stop
- 7.6.3 Medium-Speed Mode
- 7.6.4 Activation Source Acceptance
- 7.6.5 Internal Interrupt after End of Transfer:
- 7.6.6 Channel Re-Setting
- Section 8 Data Transfer Controller (DTC)
- 8.1 Features
- 8.2 Register Descriptions
- 8.2.1 DTC Mode Register A (MRA)
- 8.2.2 DTC Mode Register B (MRB)
- 8.2.3 DTC Source Address Register (SAR)
- 8.2.4 DTC Destination Address Register (DAR)
- 8.2.5 DTC Transfer Count Register A (CRA)
- 8.2.6 DTC Transfer Count Register B (CRB)
- 8.2.7 DTC Enable Registers (DTCERA to DTCERF)
- 8.2.8 DTC Vector Register (DTVECR)
- 8.3 Activation Sources
- 8.4 Location of Register Information and DTC Vector Table
- 8.5 Operation
- 8.5.1 Normal Mode
- 8.5.2 Repeat Mode
- 8.5.3 Block Transfer Mode
- 8.5.4 Chain Transfer
- 8.5.5 Interrupts
- 8.5.6 Operation Timing
- 8.5.7 Number of DTC Execution States
- 8.6 Procedures for Using DTC
- 8.6.1 Activation by Interrupt
- 8.6.2 Activation by Software
- 8.7 Examples of Use of the DTC
- 8.7.1 Normal Mode
- 8.7.2 Software Activation
- 8.8 Usage Notes
- 8.8.1 Module Stop
- 8.8.2 On-Chip RAM
- 8.8.3 DTCE Bit Setting
- 8.8.4 DMAC Transfer End Interrupt
- Section 9 I/O Ports
- 9.1 Port 1
- 9.1.1 Port 1 Data Direction Register (P1DDR)
- 9.1.2 Port 1 Data Register (P1DR)
- 9.1.3 Port 1 Register (PORT1)
- 9.1.4 Pin Functions
- 9.2 Port 3
- 9.2.1 Port 3 Data Direction Register (P3DDR)
- 9.2.2 Port 3 Data Register (P3DR)
- 9.2.3 Port 3 Register (PORT3)
- 9.2.4 Port 3 Open-Drain Control Register (P3ODR)
- 9.2.5 Pin Functions
- 9.3 Port 4
- 9.3.1 Port 4 Register (PORT4)
- 9.3.2 Pin Function
- 9.4 Port 7
- 9.4.1 Port 7 Data Direction Register (P7DDR)
- 9.4.2 Port 7 Data Register (P7DR)
- 9.4.3 Port 7 Register (PORT7)
- 9.4.4 Pin Functions
- 9.5 Port 9
- 9.5.1 Port 9 Register (PORT9)
- 9.5.2 Pin Function
- 9.6 Port A
- 9.6.1 Port A Data Direction Register (PADDR)
- 9.6.2 Port A Data Register (PADR)
- 9.6.3 Port A Register (PORTA)
- 9.6.4 Port A MOS Pull-Up Control Register (PAPCR)
- 9.6.5 Port A Open Drain Control Register (PAODR)
- 9.6.6 Pin Functions
- 9.6.7 Port A Input Pull-Up MOS Function
- 9.7 Port B
- 9.7.1 Port B Data Direction Register (PBDDR)
- 9.7.2 Port B Data Register (PBDR)
- 9.7.3 Port B Register (PORTB)
- 9.7.4 Port B MOS Pull-Up Control Register (PBPCR)
- 9.7.5 Pin Functions
- 9.7.6 Port B Input Pull-Up MOS Function
- 9.8 Port C
- 9.8.1 Port C Data Direction Register (PCDDR)
- 9.8.2 Port C Data Register (PCDR)
- 9.8.3 Port C Register (PORTC)
- 9.8.4 Port C Pull-Up MOS Control Register (PCPCR)
- 9.8.5 Pin Functions
- 9.8.6 Port C Input Pull-Up MOS Function
- 9.9 Port D
- 9.9.1 Port D Data Direction Register (PDDDR)
- 9.9.2 Port D Data Register (PDDR)
- 9.9.3 Port D Register (PORTD)
- 9.9.4 Port D Pull-up MOS Control Register (PDPCR)
- 9.9.5 Pin Functions
- 9.9.6 Port D Input Pull-Up MOS Function
- 9.10 Port E
- 9.10.1 Port E Data Direction Register (PEDDR)
- 9.10.2 Port E Data Register (PEDR)
- 9.10.3 Port E Register (PORTE)
- 9.10.4 Port E Pull-up MOS Control Register (PEPCR)
- 9.10.5 Pin Function
- 9.10.6 Port E Input Pull-Up MOS State
- 9.11 Port F
- 9.11.1 Port F Data Direction Register (PFDDR)
- 9.11.2 Port F Data Register (PFDR)
- 9.11.3 Port F Register (PORTF)
- 9.11.4 Pin Functions
- 9.12 Port G
- 9.12.1 Port G Data Direction Register (PGDDR)
- 9.12.2 Port G Data Register (PGDR)
- 9.12.3 Port G Register (PORTG)
- 9.12.4 Pin Functions
- Section 10 16-Bit Timer Pulse Unit (TPU)
- 10.1 Features
- 10.2 Input/Output Pins
- 10.3 Register Descriptions
- 10.3.1 Timer Control Register (TCR)
- 10.3.2 Timer Mode Register (TMDR)
- 10.3.3 Timer I/O Control Register (TIOR)
- 10.3.4 Timer Interrupt Enable Register (TIER)
- 10.3.5 Timer Status Register (TSR)
- 10.3.6 Timer Counter (TCNT)
- 10.3.7 Timer General Register (TGR)
- 10.3.8 Timer Start Register (TSTR)
- 10.3.9 Timer Synchro Register (TSYR)
- 10.4 Interface to Bus Master
- 10.4.1 16-Bit Registers
- 10.4.2 8-Bit Registers
- 10.5 Operation
- 10.5.1 Basic Functions
- 10.5.2 Synchronous Operation
- 10.5.3 Buffer Operation
- 10.5.4 PWM Modes
- 10.5.5 Phase Counting Mode
- 10.6 Interrupts
- 10.6.1 Interrupt Source and Priority
- 10.6.2 DTC Activation
- 10.6.3 DMAC Activation
- 10.6.4 A/D Converter Activation
- 10.7 Operation Timing
- 10.7.1 Input/Output Timing
- 10.7.2 Interrupt Signal Timing
- 10.8 Usage Notes
- Section 11 8-Bit Timers (TMR)
- 11.1 Features
- 11.2 Input/Output Pins
- 11.3 Register Descriptions
- 11.3.1 Timer Counters (TCNT)
- 11.3.2 Time Constant Registers A (TCORA)
- 11.3.3 Time Constant Registers B (TCORB)
- 11.3.4 Time Control Registers (TCR)
- 11.3.5 Timer Control/Status Registers (TCSR)
- 11.4 Operation
- 11.5 Operation Timing
- 11.5.1 TCNT Incrementation Timing
- 11.5.2 Setting of Compare Match Flags CMFA and CMFB
- 11.5.3 Timer Output Timing
- 11.5.4 Timing of Compare Match Clear
- 11.5.5 Timing of TCNT External Reset
- 11.5.6 Timing of Overflow Flag (OVF) Setting
- 11.6 Operation with Cascaded Connection
- 11.6.1 16-Bit Counter Mode
- 11.6.2 Compare Match Count Mode
- 11.7 Interrupts
- 11.7.1 Interrupt Sources and DTC Activation
- 11.7.2 A/D Converter Activation
- 11.8 Usage Notes
- 11.8.1 Contention between TCNT Write and Clear
- 11.8.2 Contention between TCNT Write and Increment
- 11.8.3 Contention between TCOR Write and Compare Match
- 11.8.4 Contention between Compare Matches A and B
- 11.8.5 Switching of Internal Clocks and TCNT Operation
- 11.8.6 Mode Setting with Cascaded Connection
- Section 12 Watchdog Timer
- 12.1 Features
- 12.2 Register Descriptions
- 12.2.1 Timer Counter (TCNT)
- 12.2.2 Timer Control/Status Register (TCSR)
- 12.2.3 Reset Control/Status Register (RSTCSR)
- 12.3 Operation
- 12.3.1 Watchdog Timer Mode
- 12.3.2 Timing of Setting of Watchdog Timer Overflow Flag (WOVF)
- 12.3.3 Interval Timer Mode
- 12.3.4 Timing of Setting of Overflow Flag (OVF)
- 12.4 Interrupts
- 12.5 Usage Notes
- 12.5.1 Notes on Register Access
- 12.5.2 Contention between Timer Counter (TCNT) Write and Increment
- 12.5.3 Changing Value of CKS2 to CKS0
- 12.5.4 Switching between Watchdog Timer Mode and Interval Timer Mode
- 12.5.5 Internal Reset in Watchdog Timer Mode
- Section 13 Serial Communication Interface
- 13.1 Features
- 13.2 Input/Output Pins
- 13.3 Register Descriptions
- 13.3.1 Receive Shift Register (RSR)
- 13.3.2 Receive Data Register (RDR)
- 13.3.3 Transmit Data Register (TDR)
- 13.3.4 Transmit Shift Register (TSR)
- 13.3.5 Serial Mode Register (SMR)
- 13.3.6 Serial Control Register (SCR)
- 13.3.7 Serial Status Register (SSR)
- 13.3.8 Smart Card Mode Register (SCMR)
- 13.3.9 Serial Extended Mode Register 0 (SEMR_0)
- 13.3.10 Bit Rate Register (BRR)
- 13.4 Operation in Asynchronous Mode
- 13.4.1 Data Transfer Format
- 13.4.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode
- 13.4.3 Clock
- 13.4.4 SCI Initialization (Asynchronous Mode)
- 13.4.5 Data Transmission (Asynchronous Mode)
- 13.4.6 Serial Data Reception (Asynchronous Mode)
- 13.5 Multiprocessor Communication Function
- 13.5.1 Multiprocessor Serial Data Transmission
- 13.5.2 Multiprocessor Serial Data Reception
- 13.6 Operation in Clocked Synchronous Mode
- 13.6.1 Clock
- 13.6.2 SCI Initialization (Clocked Synchronous Mode)
- 13.6.3 Serial Data Transmission (Clocked Synchronous Mode)
- 13.6.4 Serial Data Reception (Clocked Synchronous Mode)
- 13.6.5 Simultaneous Serial Data Transmission and Reception (Clocked Synchronous Mode)
- 13.7 SCI Select Function
- 13.8 Interrupts
- 13.8.1 Interrupts in Normal Serial Communication Interface Mode
- 13.9 Usage Notes
- 13.9.1 Break Detection and Processing (Asynchronous Mode Only)
- 13.9.2 Mark State and Break Detection (Asynchronous Mode Only)
- 13.9.3 Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only)
- 13.9.4 Restrictions on Use of DMAC or DTC
- 13.9.5 Operation in Case of Mode Transition
- 13.9.6 Switching from SCK Pin Function to Port Pin Function:
- Section 14 Boundary Scan Function
- 14.1 Features
- 14.2 Pin Configuration
- 14.3 Register Descriptions
- 14.3.1 Instruction Register (INSTR)
- 14.3.2 IDCODE Register (IDCODE)
- 14.3.3 BYPASS Register (BYPASS)
- 14.3.4 Boundary Scan Register (BSCANR)
- 14.4 Boundary Scan Function Operation
- 14.5 Usage Notes
- Section 15 Universal Serial Bus Interface (USB)
- 15.1 Features
- 15.2 Input/Output Pins
- 15.3 Register Descriptions
- 15.3.1 USB Endpoint Information Registers 00_0 to 22_4 (UEPIR00_0 to UEPIR22_4)
- 15.3.2 USB Control Register (UCTLR)
- 15.3.3 USB DMAC Transfer Request Register (UDMAR)
- 15.3.4 USB Device Resume Register (UDRR)
- 15.3.5 USB Trigger Register 0 (UTRG0)
- 15.3.6 USB Trigger Register 1 (UTRG1)
- 15.3.7 USBFIFO Clear Register 0 (UFCLR0)
- 15.3.8 USBFIFO Clear Register 1 (UFCLR1)
- 15.3.9 USB Endpoint Stall Register 0 (UESTL0)
- 15.3.10 USB Endpoint Stall Register 1 (UESTL1)
- 15.3.11 USB Endpoint Data Register 0s (UEDR0s)
- 15.3.12 USB Endpoint Data Register 0i (UEDR0i)
- 15.3.13 USB Endpoint Data Register 0o (UEDR0o)
- 15.3.14 USB Endpoint Data Register 1i (UEDR1i)
- 15.3.15 USB Endpoint Data Register 2i (UEDR2i)
- 15.3.16 USB Endpoint Data Register 2o (UEDR2o)
- 15.3.17 USB Endpoint Data Register 3i (UEDR3i)
- 15.3.18 USB Endpoint Data Register 3o (UEDR3o)
- 15.3.19 USB Endpoint Data Register 4i (UEDR4i)
- 15.3.20 USB Endpoint Data Register 4o (UEDR4o)
- 15.3.21 USB Endpoint Data Register 5i (UEDR5i)
- 15.3.22 USB Endpoint Receive Data Size Register 0o (UESZ0o)
- 15.3.23 USB Endpoint Receive Data Size Register 2o (UESZ2o)
- 15.3.24 USB Endpoint Receive Data Size Register 3o (UESZ3o)
- 15.3.25 USB Endpoint Receive Data Size Register 4o (UESZ4o)
- 15.3.26 USB Interrupt Flag Register 0 (UIFR0)
- 15.3.27 USB Interrupt Flag Register 1 (UIFR1)
- 15.3.28 USB Interrupt Flag Register 2 (UIFR2)
- 15.3.29 USB Interrupt Flag Register 3 (UIFR3)
- 15.3.30 USB Interrupt Enable Register 0 (UIER0)
- 15.3.31 USB Interrupt Enable Register 1 (UIER1)
- 15.3.32 USB Interrupt Enable Register 2 (UIER2)
- 15.3.33 USB Interrupt Enable Register 3 (UIER3)
- 15.3.34 USB Interrupt Select Register 0 (UISR0)
- 15.3.35 USB Interrupt Select Register 1 (UISR1)
- 15.3.36 USB Interrupt Select Register 2 (UISR2)
- 15.3.37 USB Interrupt Select Register 3 (UISR3)
- 15.3.38 USB Data Status Register (UDSR)
- 15.3.39 USB Configuration Value Register (UCVR)
- 15.3.40 USB Time Stamp Registers H, L (UTSRH, UTSRL)
- 15.3.41 USB Test Register 0 (UTSTR0)
- 15.3.42 USB Test Register 1 (UTSTR1)
- 15.3.43 USB Test Registers 2 and A to F (UTSTR2, UTSRA to UTSRF)
- 15.3.44 Module Stop Control Register B (MSTPCRB)
- 15.4 Interrupt Sources
- 15.5 Communication Operation
- 15.5.1 Initialization
- 15.5.2 USB Cable Connection/Disconnection
- 15.5.3 Suspend and Resume Operations
- 15.5.4 Control Transfer
- 15.5.5 Interrupt-In Transfer: (EP1i is specified as Endpoint)
- 15.5.6 Bulk-In Transfer (Dual FIFOs): (EP2i is specified as Endpoint)
- 15.5.7 Bulk-Out Transfer (Dual FIFOs): (EP2o is specified as Endpoint)
- 15.5.8 IsochronousIn Transfer (Dual-FIFO) (When EP3i is Specified as Endpoint)
- 15.5.9 IsochronousOut Transfer (Dual-FIFO) (When EP3o is Specified as Endpoint)
- 15.5.10 Processing of USB Standard Commands and Class/Vendor Commands
- 15.5.11 Stall Operations
- 15.6 DMA Transfer Specifications
- 15.6.1 Overview
- 15.6.2 On-Chip DMAC Settings
- 15.6.3 EP2i and EP4i DMA Transfer
- 15.6.4 EP2o and EP4o DMA Transfer
- 15.6.5 EP2iPKTE, EP4iPKTE, EP2oRDFN and EP4oRDFN Bits of UTRG
- 15.7 Endpoint Configuration Example
- 15.8 USB External Circuit Example
- 15.9 Usage Notes
- 15.9.1 Operating Frequency
- 15.9.2 Bus Interface
- 15.9.3 Setup Data Reception
- 15.9.4 FIFO Clear
- 15.9.5 IRQ6 Interrupt
- 15.9.6 Data Register Overread or Overwrite
- 15.9.7 EP3o Isochronous Transfer
- 15.9.8 Reset
- 15.9.9 EP0 Interrupt Assignment
- 15.9.10 Level Shifter for VBUS and IRQx Pins
- 15.9.11 USB Endpoint Data Read and Write
- 15.9.12 Restrictions for Software Standby Mode Transition
- 15.9.13 USB External Circuit Example
- Section 16 A/D Converter
- 16.1 Features
- 16.2 Input/Output Pins
- 16.3 Register Descriptions
- 16.3.1 A/D Data Registers A to D (ADDRA to ADDRD)
- 16.3.2 A/D Control/Status Register (ADCSR)
- 16.3.3 A/D Control Register (ADCR)
- 16.4 Interface to Bus Master
- 16.5 Operation
- 16.5.1 Single Mode
- 16.5.2 Scan Mode
- 16.5.3 Input Sampling and A/D Conversion Time
- 16.5.4 External Trigger Input Timing
- 16.6 Interrupts
- 16.7 A/D Conversion Precision Definitions
- 16.8 Usage Notes
- 16.8.1 Permissible Signal Source Impedance
- 16.8.2 Influences on Absolute Precision
- 16.8.3 Range of Analog Power Supply and Other Pin Settings
- 16.8.4 Notes on Board Design
- 16.8.5 Notes on Noise Countermeasures
- Section 17 D/A Converter
- 17.1 Features
- 17.2 Input/Output Pins
- 17.3 Register Description
- 17.3.1 D/A Data Register (DADR)
- 17.3.2 D/A Control Register (DACR)
- 17.4 Operation
- Section 18 RAM
- Section 19 Flash Memory (F-ZTAT Version)
- 19.1 Features
- 19.2 Mode Transitions
- 19.3 Block Configuration
- 19.4 Input/Output Pins
- 19.5 Register Descriptions
- 19.5.1 Flash Memory Control Register 1 (FLMCR1)
- 19.5.2 Flash Memory Control Register 2 (FLMCR2)
- 19.5.3 Erase Block Register 1 (EBR1)
- 19.5.4 Erase Block Register 2 (EBR2)
- 19.5.5 RAM Emulation Register (RAMER)
- 19.5.6 Serial Control Register X (SCRX)
- 19.6 On-Board Programming Modes
- 19.6.1 SCI Boot Mode (HD64F2215)
- 19.6.2 USB Boot Mode (HD64F2215U)
- 19.6.3 Programming/Erasing in User Program Mode
- 19.7 Flash Memory Emulation in RAM
- 19.8 Flash Memory Programming/Erasing
- 19.8.1 Program/Program-Verify
- 19.8.2 Erase/Erase-Verify
- 19.9 Program/Erase Protection
- 19.9.1 Hardware Protection
- 19.9.2 Software Protection
- 19.9.3 Error Protection
- 19.10 Interrupt Handling when Programming/Erasing Flash Memory
- 19.11 Programmer Mode
- 19.12 Power-Down States for Flash Memory
- 19.13 Flash Memory Programming and Erasing Precautions
- 19.14 Note on Switching from F-ZTAT Version to Masked ROM Version
- Section 20 Masked ROM
- Section 21 Clock Pulse Generator
- 21.1 Register Descriptions
- 21.1.1 System Clock Control Register (SCKCR)
- 21.1.2 Low-Power Control Register (LPWRCR)
- 21.2 System Clock Oscillator
- 21.2.1 Connecting a Crystal Resonator
- 21.2.2 Inputting an External Clock
- 21.3 Duty Adjustment Circuit
- 21.4 Medium-Speed Clock Divider
- 21.5 Bus Master Clock Selection Circuit
- 21.6 USB Operating Clock
- 21.6.1 Connecting a Ceramic Resonator
- 21.6.2 Inputting an 48-MHz External Clock
- 21.6.3 Pin Handling when 48-MHz External Clock is not Needed (On-chip PLL Circuit is Used)
- 21.7 PLL Circuit for USB
- 21.8 Usage Notes
- 21.8.1 Note on Crystal Resonator
- 21.8.2 Note on Board Design
- 21.8.3 Note on Switchover of External Clock
- Section 22 Power-Down Modes
- 22.1 Register Descriptions
- 22.1.1 Standby Control Register (SBYCR)
- 22.1.2 System Clock Control Register (SCKCR)
- 22.1.3 Module Stop Control Registers A to C (MSTPCRA to MSTPCRC)
- 22.2 Medium-Speed Mode
- 22.3 Sleep Mode
- 22.3.1 Transition to Sleep Mode
- 22.3.2 Exiting Sleep Mode
- 22.4 Software Standby Mode
- 22.4.1 Transition to Software Standby Mode
- 22.4.2 Clearing Software Standby Mode
- 22.4.3 Setting Oscillation Stabilization Time after Clearing Software Standby Mode
- 22.4.4 Software Standby Mode Application Example
- 22.5 Hardware Standby Mode
- 22.5.1 Transition to Hardware Standby Mode
- 22.5.2 Clearing Hardware Standby Mode
- 22.5.3 Hardware Standby Mode Timing
- 22.5.4 Hardware Standby Mode Timings
- 22.6 Module Stop Mode
- 22.7 Clock Output Disabling Function
- 22.8 Usage Notes
- 22.8.1 I/O Port Status
- 22.8.2 Current Dissipation during Oscillation Stabilization Wait Period
- 22.8.3 DMAC and DTC Module Stop
- 22.8.4 On-Chip Supporting Module Interrupt
- Section 23 List of Registers
- 23.1 Register Addresses (Address Order)
- 23.2 Register Bits
- 23.3 Register States in Each Operating Mode
- Section 24 Electrical Characteristics
- 24.1 Absolute Maximum Ratings
- 24.2 Power Supply Voltage and Operating Frequency Range
- 24.3 DC Characteristics
- 24.4 AC Characteristics
- 24.4.1 Clock Timing
- 24.4.2 Control Signal Timing
- 24.4.3 Bus Timing
- 24.4.4 Timing of On-Chip Supporting Modules
- 24.5 UBS Characteristics
- 24.6 A/D Conversion Characteristics
- 24.7 D/A Conversion Characteristics
- 24.8 Flash Memory Characteristics
- 24.9 Usage Note
- Appendix
- A. I/O Port States in Each Processing State
- B. Product Model Lineup
- C. Package Dimensions
- Index
- Colophon
Regarding the change of names mentioned in the document, such as Hitachi
Electric and Hitachi XX, to Renesas Technology Corp.
The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas
Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog
and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)
Accordingly, although Hitachi, Hitachi, Ltd., Hitachi Semiconductors, and other Hitachi brand
names are mentioned in the document, these names have in fact all been changed to Renesas
Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and
corporate statement, no changes whatsoever have been made to the contents of the document, and
these changes do not constitute any alteration to the contents of the document itself.
Renesas Technology Home Page: http://www.renesas.com
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
To all our customers
Cautions
Keep safety first in your circuit designs!
1.
Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but
there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire
or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i)
placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or
mishap.
Notes regarding these materials
1.
These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corporation
product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any
other rights, belonging to Renesas Technology Corporation or a third party.
2.
Renesas Technology Corporation assumes no responsibility for any damage, or infringement of any third-party's rights,
originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in
these materials.
3.
All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents
information on products at the time of publication of these materials, and are subject to change by Renesas Technology
Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact
Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor for the latest product
information before purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors.
Renesas Technology Corporation assumes no responsibility for any damage, liability, or other loss rising from these
inaccuracies or errors.
Please also pay attention to information published by Renesas Technology Corporation by various means, including the
Renesas Technology Corporation Semiconductor home page (http://www.renesas.com).
4.
When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and
algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of
the information and products. Renesas Technology Corporation assumes no responsibility for any damage, liability or other
loss resulting from the information contained herein.
5.
Renesas Technology Corporation semiconductors are not designed or manufactured for use in a device or system that is used
under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corporation or an
authorized Renesas Technology Corporation product distributor when considering the use of a product contained herein for
any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea
repeater use.
6.
The prior written approval of Renesas Technology Corporation is necessary to reprint or reproduce in whole or in part these
materials.
7.
If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license
from the Japanese government and cannot be imported into a country other than the approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is
prohibited.
8.
Please contact Renesas Technology Corporation for further details on these materials or the products contained therein.
Hitachi Single-Chip Microcomputer
H8S/2215 Series
Hardware Manual
ADE-602-217B
Rev. 3.0
10/04/02
Hitachi Ltd.
The revision list can be viewed directly by
clicking the title page.
The revision list summarizes the locations of
revisions and additions. Details should always
be checked by referring to the relevant text.
Rev. 3.0, 10/02, page ii of lviii
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi's or any third party's
patent, copyright, trademark, or other intellectual property rights for information contained in
this document. Hitachi bears no responsibility for problems that may arise with third party's
rights, including intellectual property rights, in connection with use of the information
contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you
have received the latest product standards or specifications before final design, purchase or
use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability.
However, contact Hitachi's sales office before using the product in an application that
demands especially high quality and reliability or where its failure or malfunction may directly
threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear
power, combustion control, transportation, traffic, safety equipment or medical equipment for
life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi
particularly for maximum rating, operating supply voltage range, heat radiation characteristics,
installation conditions and other characteristics. Hitachi bears no responsibility for failure or
damage when used beyond the guaranteed ranges. Even within the guaranteed ranges,
consider normally foreseeable failure rates or failure modes in semiconductor devices and
employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi
product does not cause bodily injury, fire or other consequential damage due to operation of
the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document
without written approval from Hitachi.
7. Contact Hitachi's sales office for any questions regarding this document or Hitachi
semiconductor products.
Rev. 3.0, 10/02, page iii of lviii
General Precautions on the Handling of Products
1. Treatment of NC Pins
Note:
Do not connect anything to the NC pins.
The NC (not connected) pins are either not connected to any of the internal circuitry or are
used as test pins or to reduce noise. If something is connected to the NC pins, the operation
of the LSI is not guaranteed.
2. Treatment of Unused Input Pins
Note:
Fix all unused input pins to high or low level.
Generally, the input pins of CMOS products are high-impedance input pins. If unused pins
are in their open states, intermediate levels are induced by noise in the vicinity, a pass-
through current flows internally, and a malfunction may occur.
3. Processing before Initialization
Note:
When power is first supplied, the product's state is undefined. The states of internal
circuits are undefined until full power is supplied throughout the chip and a low level is
input on the reset pin. During the period where the states are undefined, the register
settings and the output state of each pin are also undefined. Design your system so that it
does not malfunction because of processing while it is in this undefined state. For those
products which have a reset function, reset the LSI immediately after the power supply has
been turned on.
4. Prohibition of Access to Undefined or Reserved Address
Note:
Access to undefined or reserved addresses is prohibited.
The undefined or reserved addresses may be used to expand functions, or test registers
may have been be allocated to these address. Do not access these registers: the system's
operation is not guaranteed if they are accessed.