Document Outline

• Cover
• Cautions
• General Precautions on Handling of Product
• Configuration of This Manual
• Preface
• Main Revisions and Additions in this Edition
• Contents
  • Figures
  • Tables
• Section 1 Overview
  • 1.1 Features
  • 1.2 Block Diagram
  • 1.3 Pin Description
    • 1.3.1 Pin Arrangement
    • 1.3.2 Pin Arrangement in Each Operating Mode
    • 1.3.3 Pin Functions
• Section 2 CPU
  • 2.1 Features
    • 2.1.1 Differences between H8S/2600 CPU and H8S/2000 CPU
    • 2.1.2 Differences from H8/300 CPU
    • 2.1.3 Differences from H8/300H CPU
  • 2.2 CPU Operating Modes
    • 2.2.1 Normal Mode
    • 2.2.2 Advanced Mode
  • 2.3 Address Space
  • 2.4 Register Configuration
    • 2.4.1 General Registers
    • 2.4.2 Program Counter (PC)
    • 2.4.3 Extended Control Register (EXR)
    • 2.4.4 Condition-Code Register (CCR)
    • 2.4.5 Initial Register Values
  • 2.5 Data Formats
    • 2.5.1 General Register Data Formats
    • 2.5.2 Memory Data Formats
  • 2.6 Instruction Set
    • 2.6.1 Table of Instructions Classified by Function
    • 2.6.2 Basic Instruction Formats
  • 2.7 Addressing Modes and Effective Address Calculation
    • 2.7.1 Register Direct�Rn
    • 2.7.2 Register Indirect�@ERn
    • 2.7.3 Register Indirect with Displacement�@(d:16, ERn) or @(d:32, ERn)
    • 2.7.4 Register Indirect with Post-Increment or Pre-Decrement�@ERn+ or @-ERn
    • 2.7.5 Absolute Address�@aa:8, @aa:16, @aa:24, or @aa:32
    • 2.7.6 Immediate�#xx:8, #xx:16, or #xx:32
    • 2.7.7 Program-Counter Relative�@(d:8, PC) or @(d:16, PC)
    • 2.7.8 Memory Indirect�@@aa:8
    • 2.7.9 Effective Address Calculation
  • 2.8 Processing States
  • 2.9 Usage Note
    • 2.9.1 Note on Bit Manipulation Instructions
• Section 3 MCU Operating Modes
  • 3.1 Operating Mode Selection
  • 3.2 Register Descriptions
    • 3.2.1 Mode Control Register (MDCR)
    • 3.2.2 System Control Register (SYSCR)
  • 3.3 Operating Mode Descriptions
    • 3.3.1 Mode 1
    • 3.3.2 Mode 2
    • 3.3.3 Mode 3
    • 3.3.4 Mode 4
    • 3.3.5 Mode 7
    • 3.3.6 Pin Functions
  • 3.4 Memory Map in Each Operating Mode
• Section 4 Exception Handling
  • 4.1 Exception Handling Types and Priority
  • 4.2 Exception Sources and Exception Vector Table
  • 4.3 Reset
    • 4.3.1 Reset Exception Handling
    • 4.3.2 Interrupts after Reset
    • 4.3.3 On-Chip Peripheral Functions after Reset Release
  • 4.4 Traces
  • 4.5 Interrupts
  • 4.6 Trap Instruction
  • 4.7 Stack Status after Exception Handling
  • 4.8 Usage Notes
• Section 5 Interrupt Controller
  • 5.1 Features
  • 5.2 Input/Output Pins
  • 5.3 Register Descriptions
    • 5.3.1 Interrupt Control Register (INTCR)
    • 5.3.2 Interrupt Priority Registers A to K (IPRA to IPRK)
    • 5.3.3 IRQ Enable Register (IER)
    • 5.3.4 IRQ Sense Control Register L (ISCRL)
    • 5.3.5 IRQ Status Register (ISR)
    • 5.3.6 IRQ Pin Select Register (ITSR)
    • 5.3.7 Software Standby Release IRQ Enable Register (SSIER)
  • 5.4 Interrupt Sources
    • 5.4.1 External Interrupts
    • 5.4.2 Internal Interrupts
  • 5.5 Interrupt Exception Handling Vector Table
  • 5.6 Interrupt Control Modes and Interrupt Operation
    • 5.6.1 Interrupt Control Mode 0
    • 5.6.2 Interrupt Control Mode 2
    • 5.6.3 Interrupt Exception Handling Sequence
    • 5.6.4 Interrupt Response Times
    • 5.6.5 DTC and DMAC* Activation by Interrupt
  • 5.7 Usage Notes
    • 5.7.1 Contention between Interrupt Generation and Disabling
    • 5.7.2 Instructions that Disable Interrupts
    • 5.7.3 Times when Interrupts are Disabled
    • 5.7.4 Interrupts during Execution of EEPMOV Instruction
    • 5.7.5 Change of IRQ Pin Select Register (ITSR) Setting
    • 5.7.6 Note on IRQ Status Register (ISR)
• Section 6 Bus Controller (BSC)
  • 6.1 Features
  • 6.2 Input/Output Pins
  • 6.3 Register Descriptions
    • 6.3.1 Bus Width Control Register (ABWCR)
    • 6.3.2 Access State Control Register (ASTCR)
    • 6.3.3 Wait Control Registers AH, AL, BH, and BL (WTCRAH, WTCRAL, WTCRBH, and WTCRBL)
    • 6.3.4 Read Strobe Timing Control Register (RDNCR)
    • 6.3.5 CS Assertion Period Control Registers H, L (CSACRH, CSACRL)
    • 6.3.6 Area 0 Burst ROM Interface Control Register (BROMCRH) Area 1 Burst ROM Interface Control Register (BROMCRL)
    • 6.3.7 Bus Control Register (BCR)
    • 6.3.8 DRAM Control Register (DRAMCR)
    • 6.3.9 DRAM Access Control Register (DRACCR)
    • 6.3.10 Refresh Control Register (REFCR)
    • 6.3.11 Refresh Timer Counter (RTCNT)
    • 6.3.12 Refresh Time Constant Register (RTCOR)
  • 6.4 Operation
    • 6.4.1 Area Division
    • 6.4.2 Bus Specifications
    • 6.4.3 Memory Interfaces
    • 6.4.4 Chip Select Signals
  • 6.5 Basic Bus Interface
    • 6.5.1 Data Size and Data Alignment
    • 6.5.2 Valid Strobes
    • 6.5.3 Basic Timing
    • 6.5.4 Wait Control
    • 6.5.5 Read Strobe (RD) Timing
    • 6.5.6 Extension of Chip Select (CS) Assertion Period
  • 6.6 DRAM Interface
    • 6.6.1 Setting DRAM Space
    • 6.6.2 Address Multiplexing
    • 6.6.3 Data Bus
    • 6.6.4 Pins Used for DRAM Interface
    • 6.6.5 Basic Timing
    • 6.6.6 Column Address Output Cycle Control
    • 6.6.7 Row Address Output State Control
    • 6.6.8 Precharge State Control
    • 6.6.9 Wait Control
    • 6.6.10 Byte Access Control
    • 6.6.11 Burst Operation
    • 6.6.12 Refresh Control
    • 6.6.13 DMAC Single Address Transfer Mode and DRAM Interface
  • 6.7 Burst ROM Interface
    • 6.7.1 Basic Timing
    • 6.7.2 Wait Control
    • 6.7.3 Write Access
  • 6.8 Idle Cycle
    • 6.8.1 Operation
    • 6.8.2 Pin States in Idle Cycle
  • 6.9 Write Data Buffer Function
  • 6.10 Bus Release
    • 6.10.1 Operation
    • 6.10.2 Pin States in External Bus Released State
    • 6.10.3 Transition Timing
  • 6.11 Bus Arbitration
    • 6.11.1 Operation
    • 6.11.2 Bus Transfer Timing
  • 6.12 Bus Controller Operation in Reset
  • 6.13 Usage Notes
    • 6.13.1 External Bus Release Function and All-Module-Clocks-Stopped Mode
    • 6.13.2 External Bus Release Function and Software Standby
    • 6.13.3 External Bus Release Function and CBR Refreshing
    • 6.13.4 BREQO Output Timing
• Section 7 DMA Controller (DMAC)
  • 7.1 Features
  • 7.2 Input/Output Pins
  • 7.3 Register Descriptions
    • 7.3.1 Memory Address Registers (MARA and MARB)
    • 7.3.2 I/O Address Registers (IOARA and IOARB)
    • 7.3.3 Execute Transfer Count Registers (ETCRA and ETCRB)
    • 7.3.4 DMA Control Registers (DMACRA and DMACRB)
    • 7.3.5 DMA Band Control Registers H and L (DMABCRH and DMABCRL)
    • 7.3.6 DMA Write Enable Register (DMAWER)
    • 7.3.7 DMA Terminal Control Register (DMATCR)
  • 7.4 Activation Sources
    • 7.4.1 Activation by Internal Interrupt Request
    • 7.4.2 Activation by External Request
    • 7.4.3 Activation by Auto-Request
  • 7.5 Operation
    • 7.5.1 Transfer Modes
    • 7.5.2 Sequential Mode
    • 7.5.3 Idle Mode
    • 7.5.4 Repeat Mode
    • 7.5.5 Single Address Mode
    • 7.5.6 Normal Mode
    • 7.5.7 Block Transfer Mode
    • 7.5.8 Basic Bus Cycles
    • 7.5.9 DMA Transfer (Dual Address Mode) Bus Cycles
    • 7.5.10 DMA Transfer (Single Address Mode) Bus Cycles
    • 7.5.11 Write Data Buffer Function
    • 7.5.12 Multi-Channel Operation
    • 7.5.13 Relation between DMAC and External Bus Requests and Refresh Cycles
    • 7.5.14 DMAC and NMI Interrupts
    • 7.5.15 Forced Termination of DMAC Operation
    • 7.5.16 Clearing Full Address Mode
  • 7.6 Interrupt Sources
  • 7.7 Usage Notes
    • 7.7.1 DMAC Register Access during Operation
    • 7.7.2 Module Stop
    • 7.7.3 Write Data Buffer Function
    • 7.7.4 TEND Output
    • 7.7.5 Activation by Falling Edge on DREQ Pin
    • 7.7.6 Activation Source Acceptance
    • 7.7.7 Internal Interrupt after End of Transfer
    • 7.7.8 Channel Re-Setting
• Section 8 Data Transfer Controller (DTC)
  • 8.1 Features
  • 8.2 Register Descriptions
    • 8.2.1 DTC Mode Register A (MRA)
    • 8.2.2 DTC Mode Register B (MRB)
    • 8.2.3 DTC Source Address Register (SAR)
    • 8.2.4 DTC Destination Address Register (DAR)
    • 8.2.5 DTC Transfer Count Register A (CRA)
    • 8.2.6 DTC Transfer Count Register B (CRB)
    • 8.2.7 DTC Enable Registers A to G (DTCERA to DTCERG)
    • 8.2.8 DTC Vector Register (DTVECR)
  • 8.3 Activation Sources
  • 8.4 Location of Register Information and DTC Vector Table
  • 8.5 Operation
    • 8.5.1 Normal Mode
    • 8.5.2 Repeat Mode
    • 8.5.3 Block Transfer Mode
    • 8.5.4 Chain Transfer
    • 8.5.5 Interrupts
    • 8.5.6 Operation Timing
    • 8.5.7 Number of DTC Execution States
  • 8.6 Procedures for Using DTC
    • 8.6.1 Activation by Interrupt
    • 8.6.2 Activation by Software
  • 8.7 Examples of Use of the DTC
    • 8.7.1 Normal Mode
    • 8.7.2 Chain Transfer
    • 8.7.3 Chain Transfer when Counter = 0
    • 8.7.4 Software Activation
  • 8.8 Usage Notes
    • 8.8.1 Module Stop Mode Setting
    • 8.8.2 On-Chip RAM
    • 8.8.3 DTCE Bit Setting
    • 8.8.4 DMAC Transfer End Interrupt
    • 8.8.5 Chain Transfer
• Section 9 I/O Ports
  • 9.1 Port 1
    • 9.1.1 Port 1 Data Direction Register (P1DDR)
    • 9.1.2 Port 1 Data Register (P1DR)
    • 9.1.3 Port 1 Register (PORT1)
    • 9.1.4 Pin Functions
  • 9.2 Port 2
    • 9.2.1 Port 2 Data Direction Register (P2DDR)
    • 9.2.2 Port 2 Data Register (P2DR)
    • 9.2.3 Port 2 Register (PORT2)
    • 9.2.4 Pin Functions
  • 9.3 Port 3
    • 9.3.1 Port 3 Data Direction Register (P3DDR)
    • 9.3.2 Port 3 Data Register (P3DR)
    • 9.3.3 Port 3 Register (PORT3)
    • 9.3.4 Port 3 Open Drain Control Register (P3ODR)
    • 9.3.5 Port Function Control Register 2 (PFCR2)
    • 9.3.6 Pin Functions
  • 9.4 Port 4
    • 9.4.1 Port 4 Register (PORT4)
    • 9.4.2 Pin Functions
  • 9.5 Port 5
    • 9.5.1 Port 5 Data Direction Register (P5DDR)
    • 9.5.2 Port 5 Data Register (P5DR)
    • 9.5.3 Port 5 Register (PORT5)
    • 9.5.4 Pin Functions
  • 9.6 Port 8
    • 9.6.1 Port 8 Data Direction Register (P8DDR)
    • 9.6.2 Port 8 Data Register (P8DR)
    • 9.6.3 Port 8 Register (PORT8)
    • 9.6.4 Pin Functions
  • 9.7 Port 9
    • 9.7.1 Port 9 Register (PORT9)
    • 9.7.2 Pin Functions
  • 9.8 Port A
    • 9.8.1 Port A Data Direction Register (PADDR)
    • 9.8.2 Port A Data Register (PADR)
    • 9.8.3 Port A Register (PORTA)
    • 9.8.4 Port A MOS Pull-Up Control Register (PAPCR)
    • 9.8.5 Port A Open Drain Control Register (PAODR)
    • 9.8.6 Port Function Control Register 0 (PFCR0)
    • 9.8.7 Port Function Control Register 1 (PFCR1)
    • 9.8.8 Pin Functions
    • 9.8.9 Port A MOS Input Pull-Up States
  • 9.9 Port B
    • 9.9.1 Port B Data Direction Register (PBDDR)
    • 9.9.2 Port B Data Register (PBDR)
    • 9.9.3 Port B Register (PORTB)
    • 9.9.4 Port B MOS Pull-Up Control Register (PBPCR)
    • 9.9.5 Pin Functions
    • 9.9.6 Port B MOS Input Pull-Up States
  • 9.10 Port C
    • 9.10.1 Port C Data Direction Register (PCDDR)
    • 9.10.2 Port C Data Register (PCDR)
    • 9.10.3 Port C Register (PORTC)
    • 9.10.4 Port C MOS Pull-Up Control Register (PCPCR)
    • 9.10.5 Pin Functions
    • 9.10.6 Port C MOS Input Pull-Up States
  • 9.11 Port D
    • 9.11.1 Port D Data Direction Register (PDDDR)
    • 9.11.2 Port D Data Register (PDDR)
    • 9.11.3 Port D Register (PORTD)
    • 9.11.4 Port D Pull-up Control Register (PDPCR)
    • 9.11.5 Pin Functions
    • 9.11.6 Port D MOS Input Pull-Up States
  • 9.12 Port E
    • 9.12.1 Port E Data Direction Register (PEDDR)
    • 9.12.2 Port E Data Register (PEDR)
    • 9.12.3 Port E Register (PORTE)
    • 9.12.4 Port E Pull-up Control Register (PEPCR)
    • 9.12.5 Pin Functions
    • 9.12.6 Port E MOS Input Pull-Up States
  • 9.13 Port F
    • 9.13.1 Port F Data Direction Register (PFDDR)
    • 9.13.2 Port F Data Register (PFDR)
    • 9.13.3 Port F Register (PORTF)
    • 9.13.4 Pin Functions
  • 9.14 Port G
    • 9.14.1 Port G Data Direction Register (PGDDR)
    • 9.14.2 Port G Data Register (PGDR)
    • 9.14.3 Port G Register (PORTG)
    • 9.14.4 Pin Functions
• Section 10 16-Bit Timer Pulse Unit (TPU)
  • 10.1 Features
  • 10.2 Input/Output Pins
  • 10.3 Register Descriptions
    • 10.3.1 Timer Control Register (TCR)
    • 10.3.2 Timer Mode Register (TMDR)
    • 10.3.3 Timer I/O Control Register (TIOR)
    • 10.3.4 Timer Interrupt Enable Register (TIER)
    • 10.3.5 Timer Status Register (TSR)
    • 10.3.6 Timer Counter (TCNT)
    • 10.3.7 Timer General Register (TGR)
    • 10.3.8 Timer Start Register (TSTR)
    • 10.3.9 Timer Synchronous Register (TSYR)
  • 10.4 Operation
    • 10.4.1 Basic Functions
    • 10.4.2 Synchronous Operation
    • 10.4.3 Buffer Operation
    • 10.4.4 Cascaded Operation
    • 10.4.5 PWM Modes
    • 10.4.6 Phase Counting Mode
  • 10.5 Interrupts
  • 10.6 DTC Activation
  • 10.7 DMAC Activation
  • 10.8 A/D Converter Activation
  • 10.9 Operation Timing
    • 10.9.1 Input/Output Timing
    • 10.9.2 Interrupt Signal Timing
  • 10.10 Usage Notes
    • 10.10.1 Module Stop Mode Setting
    • 10.10.2 Input Clock Restrictions
    • 10.10.3 Caution on Cycle Setting
    • 10.10.4 Contention between TCNT Write and Clear Operations
    • 10.10.5 Contention between TCNT Write and Increment Operations
    • 10.10.6 Contention between TGR Write and Compare Match
    • 10.10.7 Contention between Buffer Register Write and Compare Match
    • 10.10.8 Contention between TGR Read and Input Capture
    • 10.10.9 Contention between TGR Write and Input Capture
    • 10.10.10 Contention between Buffer Register Write and Input Capture
    • 10.10.11 Contention between Overflow/Underflow and Counter Clearing
    • 10.10.12 Contention between TCNT Write and Overflow/Underflow
    • 10.10.13 Multiplexing of I/O Pins
    • 10.10.14 Interrupts and Module Stop Mode
• Section 11 Programmable Pulse Generator (PPG)
  • 11.1 Features
  • 11.2 Input/Output Pins
  • 11.3 Register Descriptions
    • 11.3.1 Next Data Enable Registers H, L (NDERH, NDERL)
    • 11.3.2 Output Data Registers H, L (PODRH, PODRL)
    • 11.3.3 Next Data Registers H, L (NDRH, NDRL)
    • 11.3.4 PPG Output Control Register (PCR)
    • 11.3.5 PPG Output Mode Register (PMR)
  • 11.4 Operation
    • 11.4.1 Output Timing
    • 11.4.2 Sample Setup Procedure for Normal Pulse Output
    • 11.4.3 Example of Normal Pulse Output (Example of Five-Phase Pulse Output)
    • 11.4.4 Non-Overlapping Pulse Output
    • 11.4.5 Sample Setup Procedure for Non-Overlapping Pulse Output
    • 11.4.6 Example of Non-Overlapping Pulse Output (Example of Four-Phase Complementary Non-Overlapping Output)
    • 11.4.7 Inverted Pulse Output
    • 11.4.8 Pulse Output Triggered by Input Capture
  • 11.5 Usage Notes
    • 11.5.1 Module Stop Mode Setting
    • 11.5.2 Operation of Pulse Output Pins
• Section 12 8-Bit Timers (TMR)
  • 12.1 Features
  • 12.2 Input/Output Pins
  • 12.3 Register Descriptions
    • 12.3.1 Timer Counter (TCNT)
    • 12.3.2 Time Constant Register A (TCORA)
    • 12.3.3 Time Constant Register B (TCORB)
    • 12.3.4 Timer Control Register (TCR)
    • 12.3.5 Timer Control/Status Register (TCSR)
  • 12.4 Operation
    • 12.4.1 Pulse Output
  • 12.5 Operation Timing
    • 12.5.1 TCNT Incrementation Timing
    • 12.5.2 Timing of CMFA and CMFB Setting when Compare-Match Occurs
    • 12.5.3 Timing of Timer Output when Compare-Match Occurs
    • 12.5.4 Timing of Compare Match Clear
    • 12.5.5 Timing of TCNT External Reset
    • 12.5.6 Timing of Overflow Flag (OVF) Setting
  • 12.6 Operation with Cascaded Connection
    • 12.6.1 16-Bit Counter Mode
    • 12.6.2 Compare Match Count Mode
  • 12.7 Interrupts
    • 12.7.1 Interrupt Sources and DTC Activation
    • 12.7.2 A/D Converter Activation
  • 12.8 Usage Notes
    • 12.8.1 Contention between TCNT Write and Clear
    • 12.8.2 Contention between TCNT Write and Increment
    • 12.8.3 Contention between TCOR Write and Compare Match
    • 12.8.4 Contention between Compare Matches A and B
    • 12.8.5 Switching of Internal Clocks and TCNT Operation
    • 12.8.6 Mode Setting with Cascaded Connection
    • 12.8.7 Interrupts in Module Stop Mode
• Section 13 Watchdog Timer
  • 13.1 Features
  • 13.2 Input/Output Pin
  • 13.3 Register Descriptions
    • 13.3.1 Timer Counter (TCNT)
    • 13.3.2 Timer Control/Status Register (TCSR)
    • 13.3.3 Reset Control/Status Register (RSTCSR)
  • 13.4 Operation
    • 13.4.1 Watchdog Timer Mode
    • 13.4.2 Interval Timer Mode
  • 13.5 Interrupts
  • 13.6 Usage Notes
    • 13.6.1 Notes on Register Access
    • 13.6.2 Contention between Timer Counter (TCNT) Write and Increment
    • 13.6.3 Changing Value of CKS2 to CKS0
    • 13.6.4 Switching between Watchdog Timer Mode and Interval Timer Mode
    • 13.6.5 Internal Reset in Watchdog Timer Mode
    • 13.6.6 System Reset by WDTOVF Signal
• Section 14 Serial Communication Interface (SCI, IrDA)
  • 14.1 Features
  • 14.2 Input/Output Pins
  • 14.3 Register Descriptions
    • 14.3.1 Receive Shift Register (RSR)
    • 14.3.2 Receive Data Register (RDR)
    • 14.3.3 Transmit Data Register (TDR)
    • 14.3.4 Transmit Shift Register (TSR)
    • 14.3.5 Serial Mode Register (SMR)
    • 14.3.6 Serial Control Register (SCR)
    • 14.3.7 Serial Status Register (SSR)
    • 14.3.8 Smart Card Mode Register (SCMR)
    • 14.3.9 Bit Rate Register (BRR)
    • 14.3.10 IrDA Control Register (IrCR)
    • 14.3.11 Serial Extension Mode Register (SEMR)
  • 14.4 Operation in Asynchronous Mode
    • 14.4.1 Data Transfer Format
    • 14.4.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode
    • 14.4.3 Clock
    • 14.4.4 SCI Initialization (Asynchronous Mode)
    • 14.4.5 Data Transmission (Asynchronous Mode)
    • 14.4.6 Serial Data Reception (Asynchronous Mode)
  • 14.5 Multiprocessor Communication Function
    • 14.5.1 Multiprocessor Serial Data Transmission
    • 14.5.2 Multiprocessor Serial Data Reception
  • 14.6 Operation in Clocked Synchronous Mode
    • 14.6.1 Clock
    • 14.6.2 SCI Initialization (Clocked Synchronous Mode)
    • 14.6.3 Serial Data Transmission (Clocked Synchronous Mode)
    • 14.6.4 Serial Data Reception (Clocked Synchronous Mode)
    • 14.6.5 Simultaneous Serial Data Transmission and Reception (Clocked Synchronous Mode)
  • 14.7 Operation in Smart Card Interface Mode
    • 14.7.1 Pin Connection Example
    • 14.7.2 Data Format (Except for Block Transfer Mode)
    • 14.7.3 Block Transfer Mode
    • 14.7.4 Receive Data Sampling Timing and Reception Margin
    • 14.7.5 Initialization
    • 14.7.6 Data Transmission (Except for Block Transfer Mode)
    • 14.7.7 Serial Data Reception (Except for Block Transfer Mode)
    • 14.7.8 Clock Output Control
  • 14.8 IrDA Operation
  • 14.9 SCI Interrupts
    • 14.9.1 Interrupts in Normal Serial Communication Interface Mode
    • 14.9.2 Interrupts in Smart Card Interface Mode
  • 14.10 Usage Notes
    • 14.10.1 Module Stop Mode Setting
    • 14.10.2 Break Detection and Processing
    • 14.10.3 Mark State and Break Sending
    • 14.10.4 Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only)
    • 14.10.5 Relation between Writes to TDR and the TDRE Flag
    • 14.10.6 Restrictions on Use of DMAC* or DTC
    • 14.10.7 Operation in Case of Mode Transition
• Section 15 I2C Bus Interface2 (IIC2) (Option)
  • 15.1 Features
  • 15.2 Input/Output Pins
  • 15.3 Register Descriptions
    • 15.3.1 I2C Bus Control Register A (ICCRA)
    • 15.3.2 I2C Bus Control Register B (ICCRB)
    • 15.3.3 I2C Bus Mode Register (ICMR)
    • 15.3.4 I2C Bus Interrupt Enable Register (ICIER)
    • 15.3.5 I2C Bus Status Register (ICSR)
    • 15.3.6 Slave Address Register (SAR)
    • 15.3.7 I2C Bus Transmit Data Register (ICDRT)
    • 15.3.8 I2C Bus Receive Data Register (ICDRR)
    • 15.3.9 I2C Bus Shift Register (ICDRS)
  • 15.4 Operation
    • 15.4.1 I2C Bus Format
    • 15.4.2 Master Transmit Operation
    • 15.4.3 Master Receive Operation
    • 15.4.4 Slave Transmit Operation
    • 15.4.5 Slave Receive Operation
    • 15.4.6 Noise Canceler
    • 15.4.7 Example of Use
  • 15.5 Interrupt Request
  • 15.6 Bit Synchronous Circuit
• Section 16 A/D Converter
  • 16.1 Features
  • 16.2 Input/Output Pins
  • 16.3 Register Descriptions
    • 16.3.1 A/D Data Registers A to H (ADDRA to ADDRH)
    • 16.3.2 A/D Control/Status Register (ADCSR)
    • 16.3.3 A/D Control Register (ADCR)
  • 16.4 Operation
    • 16.4.1 Single Mode
    • 16.4.2 Scan Mode
    • 16.4.3 Input Sampling and A/D Conversion Time
    • 16.4.4 External Trigger Input Timing
  • 16.5 Interrupts
  • 16.6 A/D Conversion Precision Definitions
  • 16.7 Usage Notes
    • 16.7.1 Module Stop Mode Setting
    • 16.7.2 Permissible Signal Source Impedance
    • 16.7.3 Influences on Absolute Precision
    • 16.7.4 Setting Range of Analog Power Supply and Other Pins
    • 16.7.5 Notes on Board Design
    • 16.7.6 Notes on Noise Countermeasures
• Section 17 D/A Converter
  • 17.1 Features
  • 17.2 Input/Output Pins
  • 17.3 Register Descriptions
    • 17.3.1 D/A Data Registers 2 and 3 (DADR2 and DADR3)
    • 17.3.2 D/A Control Register 23 (DACR23)
  • 17.4 Operation
  • 17.5 Usage Notes
    • 17.5.1 Setting for Module Stop Mode
    • 17.5.2 D/A Output Hold Function in Software Standby Mode
• Section 18 RAM
• Section 19 Flash Memory (F-ZTAT Version)
  • 19.1 Features
  • 19.2 Mode Transitions
  • 19.3 Block Configuration
  • 19.4 Input/Output Pins
  • 19.5 Register Descriptions
    • 19.5.1 Flash Memory Control Register 1 (FLMCR1)
    • 19.5.2 Flash Memory Control Register 2 (FLMCR2)
    • 19.5.3 Erase Block Register 1 (EBR1)
    • 19.5.4 Erase Block Register 2 (EBR2)
    • 19.5.5 RAM Emulation Register (RAMER)
  • 19.6 On-Board Programming Modes
    • 19.6.1 Boot Mode
    • 19.6.2 User Program Mode
  • 19.7 Flash Memory Emulation in RAM
  • 19.8 Flash Memory Programming/Erasing
    • 19.8.1 Program/Program-Verify
    • 19.8.2 Erase/Erase-Verify
    • 19.8.3 Interrupt Handling when Programming/Erasing Flash Memory
  • 19.9 Program/Erase Protection
    • 19.9.1 Hardware Protection
    • 19.9.2 Software Protection
    • 19.9.3 Error Protection
  • 19.10 Programmer Mode
  • 19.11 Power-Down States for Flash Memory
  • 19.12 Usage Notes
• Section 20 Mask ROM
• Section 21 Clock Pulse Generator
  • 21.1 Register Descriptions
    • 21.1.1 System Clock Control Register (SCKCR)
    • 21.1.2 PLL Control Register (PLLCR)
  • 21.2 Oscillator
    • 21.2.1 Connecting a Crystal Oscillator
    • 21.2.2 External Clock Input
  • 21.3 PLL Circuit
  • 21.4 Frequency Divider
  • 21.5 Usage Notes
    • 21.5.1 Notes on Clock Pulse Generator
    • 21.5.2 Notes on Oscillator
    • 21.5.3 Notes on Board Design
• Section 22 Power-Down Modes
  • 22.1 Register Descriptions
    • 22.1.1 Standby Control Register (SBYCR)
    • 22.1.2 Module Stop Control Registers H and L (MSTPCRH, MSTPCRL)
    • 22.1.3 Extension Module Stop Control Registers H and L (EXMSTPCRH, EXMSTPCRL)
  • 22.2 Operation
    • 22.2.1 Clock Division Mode
    • 22.2.2 Sleep Mode
    • 22.2.3 Software Standby Mode
    • 22.2.4 Hardware Standby Mode
    • 22.2.5 Module Stop Mode
    • 22.2.6 All-Module-Clocks-Stop Mode
  • ��
  • 22.4 Usage Notes
    • 22.4.1 I/O Port Status
    • 22.4.2 Current Dissipation during Oscillation Stabilization Standby Period
    • 22.4.3 DMAC/DTC Module Stop
    • 22.4.4 On-Chip Peripheral Module Interrupts
    • 22.4.5 Writing to MSTPCR, EXMSTPCR
    • 22.4.6 Notes on Clock Division Mode
• Section 23 List of Registers
  • 23.1 Register Addresses (Address Order)
  • 23.2 Register Bits
  • 23.3 Register States in Each Operating Mode
• Section 24 Electrical Characteristics
  • 24.1 Electrical Characteristics of Masked ROM and ROMless Versions
    • 24.1.1 Absolute Maximum Ratings
    • 24.1.2 DC Characteristics
    • 24.1.3 AC Characteristics
    • 24.1.4 A/D Conversion Characteristics
    • 24.1.5 D/A Conversion Characteristics
  • 24.2 Electrical Characteristics of F-ZTAT Version
    • 24.2.1 Absolute Maximum Ratings
    • 24.2.2 DC Characteristics
    • 24.2.3 A/D Conversion Characteristics
    • 24.2.4 D/A Conversion Characteristics
  • 24.3 Flash Memory Characteristics
  • 24.4 Usage Note
• Appendix
  • A. I/O Port States in Each Pin State
  • B. Product Lineup
  • C. Package Dimensions
  • D. Bus State during Execution of Instructions
• Index
• Colophon