Document Outline
- Cover
- Cautions
- General Precautions on Handling of Product
- Preface
- Main Revisions and Additions in this Edition
- Contents
- Section 1 Overview
- 1.1 Overview
- 1.2 Block Diagram
- 1.3 Pin Description
- 1.3.1 Pin Arrangement
- 1.3.2 Pin Functions in Each Operating Mode
- 1.3.3 Pin Functions
- Section 2 CPU
- 2.1 Overview
- 2.1.1 Features
- 2.1.2 Differences between H8S/2600 CPU and H8S/2000 CPU
- 2.1.3 Differences from H8/300 CPU
- 2.1.4 Differences from H8/300H CPU
- 2.2 CPU Operating Modes
- 2.3 Address Space
- 2.4 Register Configuration
- 2.4.1 Overview
- 2.4.2 General Registers
- 2.4.3 Control Registers
- 2.4.4 Initial Register Values
- 2.5 Data Formats
- 2.5.1 General Register Data Formats
- 2.5.2 Memory Data Formats
- 2.6 Instruction Set
- 2.6.1 Overview
- 2.6.2 Instructions and Addressing Modes
- 2.6.3 Table of Instructions Classified by Function
- 2.6.4 Basic Instruction Formats
- 2.7 Addressing Modes and Effective Address Calculation
- 2.7.1 Addressing Mode
- 2.7.2 Effective Address Calculation
- 2.8 Processing States
- 2.8.1 Overview
- 2.8.2 Reset State
- 2.8.3 Exception-Handling State
- 2.8.4 Program Execution State
- 2.8.5 Bus-Released State
- 2.8.6 Power-Down State
- 2.9 Basic Timing
- 2.9.1 Overview
- 2.9.2 On-Chip Memory (ROM, RAM)
- 2.9.3 On-Chip Supporting Module Access Timing
- 2.9.4 External Address Space Access Timing
- 2.10 Usage Note
- Section 3 MCU Operating Modes
- 3.1 Overview
- 3.1.1 Operating Mode Selection (H8S/2357 F-ZTAT Only)
- 3.1.2 Operating Mode Selection (ZTAT, Mask ROM, ROMless Version, and H8S/2398 F-ZTAT)
- 3.1.3 Register Configuration
- 3.2 Register Descriptions
- 3.2.1 Mode Control Register (MDCR)
- 3.2.2 System Control Register (SYSCR)
- 3.2.3 System Control Register 2 (SYSCR2) (F-ZTAT Version Only)
- 3.3 Operating Mode Descriptions
- 3.3.1 Mode 1
- 3.3.2 Mode 2 (H8S/2398 F-ZTAT Only)
- 3.3.3 Mode 3 (H8S/2398 F-ZTAT Only)
- 3.3.4 Mode 4 (On-Chip ROM Disabled Expansion Mode)
- 3.3.5 Mode 5 (On-Chip ROM Disabled Expansion Mode)
- 3.3.6 Mode 6 (On-Chip ROM Enabled Expansion Mode)
- 3.3.7 Mode 7 (Single-Chip Mode)
- 3.3.8 Modes 8 and 9
- 3.3.9 Mode 10 (H8S/2357 F-ZTAT Only)
- 3.3.10 Mode 11 (H8S/2357 F-ZTAT Only)
- 3.3.11 Modes 12 and 13 (H8S/2357 F-ZTAT Only)
- 3.3.12 Mode 14 (H8S/2357 F-ZTAT Only)
- 3.3.13 Mode 15 (H8S/2357 F-ZTAT Only)
- 3.4 Pin Functions in Each Operating Mode
- 3.5 Memory Map in Each Operating Mode
- Section 4 Exception Handling
- 4.1 Overview
- 4.1.1 Exception Handling Types and Priority
- 4.1.2 Exception Handling Operation
- 4.1.3 Exception Vector Table
- 4.2 Reset
- 4.2.1 Overview
- 4.2.2 Reset Types
- 4.2.3 Reset Sequence
- 4.2.4 Interrupts after Reset
- 4.2.5 State of On-Chip Supporting Modules after Reset Release
- 4.3 Traces
- 4.4 Interrupts
- 4.5 Trap Instruction
- 4.6 Stack Status after Exception Handling
- 4.7 Notes on Use of the Stack
- Section 5 Interrupt Controller
- 5.1 Overview
- 5.1.1 Features
- 5.1.2 Block Diagram
- 5.1.3 Pin Configuration
- 5.1.4 Register Configuration
- 5.2 Register Descriptions
- 5.2.1 System Control Register (SYSCR)
- 5.2.2 Interrupt Priority Registers A to K (IPRA to IPRK)
- 5.2.3 IRQ Enable Register (IER)
- 5.2.4 IRQ Sense Control Registers H and L (ISCRH, ISCRL)
- 5.2.5 IRQ Status Register (ISR)
- 5.3 Interrupt Sources
- 5.3.1 External Interrupts
- 5.3.2 Internal Interrupts
- 5.3.3 Interrupt Exception Handling Vector Table
- 5.4 Interrupt Operation
- 5.4.1 Interrupt Control Modes and Interrupt Operation
- 5.4.2 Interrupt Control Mode 0
- 5.4.3 Interrupt Control Mode 2
- 5.4.4 Interrupt Exception Handling Sequence
- 5.4.5 Interrupt Response Times
- 5.5 Usage Notes
- 5.5.1 Contention between Interrupt Generation and Disabling
- 5.5.2 Instructions that Disable Interrupts
- 5.5.3 Times when Interrupts are Disabled
- 5.5.4 Interrupts during Execution of EEPMOV Instruction
- 5.6 DTC and DMAC Activation by Interrupt
- 5.6.1 Overview
- 5.6.2 Block Diagram
- 5.6.3 Operation
- Section 6 Bus Controller
- 6.1 Overview
- 6.1.1 Features
- 6.1.2 Block Diagram
- 6.1.3 Pin Configuration
- 6.1.4 Register Configuration
- 6.2 Register Descriptions
- 6.2.1 Bus Width Control Register (ABWCR)
- 6.2.2 Access State Control Register (ASTCR)
- 6.2.3 Wait Control Registers H and L (WCRH, WCRL)
- 6.2.4 Bus Control Register H (BCRH)
- 6.2.5 Bus Control Register L (BCRL)
- 6.2.6 Memory Control Register (MCR)
- 6.2.7 DRAM Control Register (DRAMCR)
- 6.2.8 Refresh Timer/Counter (RTCNT)
- 6.2.9 Refresh Time Constant Register (RTCOR)
- 6.3 Overview of Bus Control
- 6.3.1 Area Partitioning
- 6.3.2 Bus Specifications
- 6.3.3 Memory Interfaces
- 6.3.4 Advanced Mode
- 6.3.5 Chip Select Signals
- 6.4 Basic Bus Interface
- 6.4.1 Overview
- 6.4.2 Data Size and Data Alignment
- 6.4.3 Valid Strobes
- 6.4.4 Basic Timing
- 6.4.5 Wait Control
- 6.5 DRAM Interface
- 6.5.1 Overview
- 6.5.2 Setting DRAM Space
- 6.5.3 Address Multiplexing
- 6.5.4 Data Bus
- 6.5.5 Pins Used for DRAM Interface
- 6.5.6 Basic Timing
- 6.5.7 Precharge State Control
- 6.5.8 Wait Control
- 6.5.9 Byte Access Control
- 6.5.10 Burst Operation
- 6.5.11 Refresh Control
- 6.6 DMAC Single Address Mode and DRAM Interface
- 6.6.1 When DDS = 1
- 6.6.2 When DDS = 0
- 6.7 Burst ROM Interface
- 6.7.1 Overview
- 6.7.2 Basic Timing
- 6.7.3 Wait Control
- 6.8 Idle Cycle
- 6.8.1 Operation
- 6.8.2 Pin States in Idle Cycle
- 6.9 Write Data Buffer Function
- 6.10 Bus Release
- 6.10.1 Overview
- 6.10.2 Operation
- 6.10.3 Pin States in External Bus Released State
- 6.10.4 Transition Timing
- 6.10.5 Usage Note
- 6.11 Bus Arbitration
- 6.11.1 Overview
- 6.11.2 Operation
- 6.11.3 Bus Transfer Timing
- 6.11.4 External Bus Release Usage Note
- 6.12 Resets and the Bus Controller
- Section 7 DMA Controller
- 7.1 Overview
- 7.1.1 Features
- 7.1.2 Block Diagram
- 7.1.3 Overview of Functions
- 7.1.4 Pin Configuration
- 7.1.5 Register Configuration
- 7.2 Register Descriptions (1) (Short Address Mode)
- 7.2.1 Memory Address Registers (MAR)
- 7.2.2 I/O Address Register (IOAR)
- 7.2.3 Execute Transfer Count Register (ETCR)
- 7.2.4 DMA Control Register (DMACR)
- 7.2.5 DMA Band Control Register (DMABCR)
- 7.3 Register Descriptions (2) (Full Address Mode)
- 7.3.1 Memory Address Register (MAR)
- 7.3.2 I/O Address Register (IOAR)
- 7.3.3 Execute Transfer Count Register (ETCR)
- 7.3.4 DMA Control Register (DMACR)
- 7.3.5 DMA Band Control Register (DMABCR)
- 7.4 Register Descriptions (3)
- 7.4.1 DMA Write Enable Register (DMAWER)
- 7.4.2 DMA Terminal Control Register (DMATCR)
- 7.4.3 Module Stop Control Register (MSTPCR)
- 7.5 Operation
- 7.5.1 Transfer Modes
- 7.5.2 Sequential Mode
- 7.5.3 Idle Mode
- 7.5.4 Repeat Mode
- 7.5.5 Single Address Mode
- 7.5.6 Normal Mode
- 7.5.7 Block Transfer Mode
- 7.5.8 DMAC Activation Sources
- 7.5.9 Basic DMAC Bus Cycles
- 7.5.10 DMAC Bus Cycles (Dual Address Mode)
- 7.5.11 DMAC Bus Cycles (Single Address Mode)
- 7.5.12 Write Data Buffer Function
- 7.5.13 DMAC Multi-Channel Operation
- 7.5.14 Relation between External Bus Requests, Refresh Cycles, the DTC, and the DMAC
- 7.5.15 NMI Interrupts and DMAC
- 7.5.16 Forced Termination of DMAC Operation
- 7.5.17 Clearing Full Address Mode
- 7.6 Interrupts
- 7.7 Usage Notes
- Section 8 Data Transfer Controller
- 8.1 Overview
- 8.1.1 Features
- 8.1.2 Block Diagram
- 8.1.3 Register Configuration
- 8.2 Register Descriptions
- 8.2.1 DTC Mode Register A (MRA)
- 8.2.2 DTC Mode Register B (MRB)
- 8.2.3 DTC Source Address Register (SAR)
- 8.2.4 DTC Destination Address Register (DAR)
- 8.2.5 DTC Transfer Count Register A (CRA)
- 8.2.6 DTC Transfer Count Register B (CRB)
- 8.2.7 DTC Enable Registers (DTCER)
- 8.2.8 DTC Vector Register (DTVECR)
- 8.2.9 Module Stop Control Register (MSTPCR)
- 8.3 Operation
- 8.3.1 Overview
- 8.3.2 Activation Sources
- 8.3.3 DTC Vector Table
- 8.3.4 Location of Register Information in Address Space
- 8.3.5 Normal Mode
- 8.3.6 Repeat Mode
- 8.3.7 Block Transfer Mode
- 8.3.8 Chain Transfer
- 8.3.9 Operation Timing
- 8.3.10 Number of DTC Execution States
- 8.3.11 Procedures for Using DTC
- 8.3.12 Examples of Use of the DTC
- 8.4 Interrupts
- 8.5 Usage Notes
- Section 9 I/O Ports
- 9.1 Overview
- 9.2 Port 1
- 9.2.1 Overview
- 9.2.2 Register Configuration
- 9.2.3 Pin Functions
- 9.3 Port 2
- 9.3.1 Overview
- 9.3.2 Register Configuration
- 9.3.3 Pin Functions
- 9.4 Port 3
- 9.4.1 Overview
- 9.4.2 Register Configuration
- 9.4.3 Pin Functions
- 9.5 Port 4
- 9.5.1 Overview
- 9.5.2 Register Configuration
- 9.5.3 Pin Functions
- 9.6 Port 5
- 9.6.1 Overview
- 9.6.2 Register Configuration
- 9.6.3 Pin Functions
- 9.7 Port 6
- 9.7.1 Overview
- 9.7.2 Register Configuration
- 9.7.3 Pin Functions
- 9.8 Port A
- 9.8.1 Overview
- 9.8.2 Register Configuration
- 9.8.3 Pin Functions
- 9.8.4 MOS Input Pull-Up Function (On-Chip ROM Version Only)
- 9.9 Port B
- 9.9.1 Overview
- 9.9.2 Register Configuration (On-Chip ROM Version Only)
- 9.9.3 Pin Functions
- 9.9.4 MOS Input Pull-Up Function (On-Chip ROM Version Only)
- 9.10 Port C
- 9.10.1 Overview
- 9.10.2 Register Configuration (On-Chip ROM Version Only)
- 9.10.3 Pin Functions
- 9.10.4 MOS Input Pull-Up Function (On-Chip ROM Version Only)
- 9.11 Port D
- 9.11.1 Overview
- 9.11.2 Register Configuration (On-Chip ROM Version Only)
- 9.11.3 Pin Functions
- 9.11.4 MOS Input Pull-Up Function (On-Chip ROM Version Only)
- 9.12 Port E
- 9.12.1 Overview
- 9.12.2 Register Configuration
- 9.12.3 Pin Functions
- 9.12.4 MOS Input Pull-Up Function (On-Chip ROM Version Only)
- 9.13 Port F
- 9.13.1 Overview
- 9.13.2 Register Configuration
- 9.13.3 Pin Functions
- 9.14 Port G
- 9.14.1 Overview
- 9.14.2 Register Configuration
- 9.14.3 Pin Functions
- Section 10 16-Bit Timer Pulse Unit (TPU)
- 10.1 Overview
- 10.1.1 Features
- 10.1.2 Block Diagram
- 10.1.3 Pin Configuration
- 10.1.4 Register Configuration
- 10.2 Register Descriptions
- 10.2.1 Timer Control Register (TCR)
- 10.2.2 Timer Mode Register (TMDR)
- 10.2.3 Timer I/O Control Register (TIOR)
- 10.2.4 Timer Interrupt Enable Register (TIER)
- 10.2.5 Timer Status Register (TSR)
- 10.2.6 Timer Counter (TCNT)
- 10.2.7 Timer General Register (TGR)
- 10.2.8 Timer Start Register (TSTR)
- 10.2.9 Timer Synchro Register (TSYR)
- 10.2.10 Module Stop Control Register (MSTPCR)
- 10.3 Interface to Bus Master
- 10.3.1 16-Bit Registers
- 10.3.2 8-Bit Registers
- 10.4 Operation
- 10.4.1 Overview
- 10.4.2 Basic Functions
- 10.4.3 Synchronous Operation
- 10.4.4 Buffer Operation
- 10.4.5 Cascaded Operation
- 10.4.6 PWM Modes
- 10.4.7 Phase Counting Mode
- 10.5 Interrupts
- 10.5.1 Interrupt Sources and Priorities
- 10.5.2 DTC/DMAC Activation
- 10.5.3 A/D Converter Activation
- 10.6 Operation Timing
- 10.6.1 Input/Output Timing
- 10.6.2 Interrupt Signal Timing
- 10.7 Usage Notes
- Section 11 Programmable Pulse Generator (PPG)
- 11.1 Overview
- 11.1.1 Features
- 11.1.2 Block Diagram
- 11.1.3 Pin Configuration
- 11.1.4 Registers
- 11.2 Register Descriptions
- 11.2.1 Next Data Enable Registers H and L (NDERH, NDERL)
- 11.2.2 Output Data Registers H and L (PODRH, PODRL)
- 11.2.3 Next Data Registers H and L (NDRH, NDRL)
- 11.2.4 Notes on NDR Access
- 11.2.5 PPG Output Control Register (PCR)
- 11.2.6 PPG Output Mode Register (PMR)
- 11.2.7 Port 1 Data Direction Register (P1DDR)
- 11.2.8 Port 2 Data Direction Register (P2DDR)
- 11.2.9 Module Stop Control Register (MSTPCR)
- 11.3 Operation
- 11.3.1 Overview
- 11.3.2 Output Timing
- 11.3.3 Normal Pulse Output
- 11.3.4 Non-Overlapping Pulse Output
- 11.3.5 Inverted Pulse Output
- 11.3.6 Pulse Output Triggered by Input Capture
- 11.4 Usage Notes
- Section 12 8-Bit Timers
- 12.1 Overview
- 12.1.1 Features
- 12.1.2 Block Diagram
- 12.1.3 Pin Configuration
- 12.1.4 Register Configuration
- 12.2 Register Descriptions
- 12.2.1 Timer Counters 0 and 1 (TCNT0, TCNT1)
- 12.2.2 Time Constant Registers A0 and A1 (TCORA0, TCORA1)
- 12.2.3 Time Constant Registers B0 and B1 (TCORB0, TCORB1)
- 12.2.4 Time Control Registers 0 and 1 (TCR0, TCR1)
- 12.2.5 Timer Control/Status Registers 0 and 1 (TCSR0, TCSR1)
- 12.2.6 Module Stop Control Register (MSTPCR)
- 12.3 Operation
- 12.3.1 TCNT Incrementation Timing
- 12.3.2 Compare Match Timing
- 12.3.3 Timing of External RESET on TCNT
- 12.3.4 Timing of Overflow Flag (OVF) Setting
- 12.3.5 Operation with Cascaded Connection
- 12.4 Interrupts
- 12.4.1 Interrupt Sources and DTC Activation
- 12.4.2 A/D Converter Activation
- 12.5 Sample Application
- 12.6 Usage Notes
- 12.6.1 Contention between TCNT Write and Clear
- 12.6.2 Contention between TCNT Write and Increment
- 12.6.3 Contention between TCOR Write and Compare Match
- 12.6.4 Contention between Compare Matches A and B
- 12.6.5 Switching of Internal Clocks and TCNT Operation
- 12.6.6 Interrupts and Module Stop Mode
- Section 13 Watchdog Timer
- 13.1 Overview
- 13.1.1 Features
- 13.1.2 Block Diagram
- 13.1.3 Pin Configuration
- 13.1.4 Register Configuration
- 13.2 Register Descriptions
- 13.2.1 Timer Counter (TCNT)
- 13.2.2 Timer Control/Status Register (TCSR)
- 13.2.3 Reset Control/Status Register (RSTCSR)
- 13.2.4 Notes on Register Access
- 13.3 Operation
- 13.3.1 Watchdog Timer Operation
- 13.3.2 Interval Timer Operation
- 13.3.3 Timing of Setting Overflow Flag (OVF)
- 13.3.4 Timing of Setting of Watchdog Timer Overflow Flag (WOVF)
- 13.4 Interrupts
- 13.5 Usage Notes
- 13.5.1 Contention between Timer Counter (TCNT) Write and Increment
- 13.5.2 Changing Value of CKS2 to CKS0
- 13.5.3 Switching between Watchdog Timer Mode and Interval Timer Mode
- 13.5.4 System Reset by WDTOVF Signal
- 13.5.5 Internal Reset in Watchdog Timer Mode
- Section 14 Serial Communication Interface (SCI)
- 14.1 Overview
- 14.1.1 Features
- 14.1.2 Block Diagram
- 14.1.3 Pin Configuration
- 14.1.4 Register Configuration
- 14.2 Register Descriptions
- 14.2.1 Receive Shift Register (RSR)
- 14.2.2 Receive Data Register (RDR)
- 14.2.3 Transmit Shift Register (TSR)
- 14.2.4 Transmit Data Register (TDR)
- 14.2.5 Serial Mode Register (SMR)
- 14.2.6 Serial Control Register (SCR)
- 14.2.7 Serial Status Register (SSR)
- 14.2.8 Bit Rate Register (BRR)
- 14.2.9 Smart Card Mode Register (SCMR)
- 14.2.10 Module Stop Control Register (MSTPCR)
- 14.3 Operation
- 14.3.1 Overview
- 14.3.2 Operation in Asynchronous Mode
- 14.3.3 Multiprocessor Communication Function
- 14.3.4 Operation in Clocked Synchronous Mode
- 14.4 SCI Interrupts
- 14.5 Usage Notes
- Section 15 Smart Card Interface
- 15.1 Overview
- 15.1.1 Features
- 15.1.2 Block Diagram
- 15.1.3 Pin Configuration
- 15.1.4 Register Configuration
- 15.2 Register Descriptions
- 15.2.1 Smart Card Mode Register (SCMR)
- 15.2.2 Serial Status Register (SSR)
- 15.2.3 Serial Mode Register (SMR)
- 15.2.4 Serial Control Register (SCR)
- 15.3 Operation
- 15.3.1 Overview
- 15.3.2 Pin Connections
- 15.3.3 Data Format
- 15.3.4 Register Settings
- 15.3.5 Clock
- 15.3.6 Data Transfer Operations
- 15.3.7 Operation in GSM Mode
- 15.4 Usage Notes
- Section 16 A/D Converter
- 16.1 Overview
- 16.1.1 Features
- 16.1.2 Block Diagram
- 16.1.3 Pin Configuration
- 16.1.4 Register Configuration
- 16.2 Register Descriptions
- 16.2.1 A/D Data Registers A to D (ADDRA to ADDRD)
- 16.2.2 A/D Control/Status Register (ADCSR)
- 16.2.3 A/D Control Register (ADCR)
- 16.2.4 Module Stop Control Register (MSTPCR)
- 16.3 Interface to Bus Master
- 16.4 Operation
- 16.4.1 Single Mode (SCAN = 0)
- 16.4.2 Scan Mode (SCAN = 1)
- 16.4.3 Input Sampling and A/D Conversion Time
- 16.4.4 External Trigger Input Timing
- 16.5 Interrupts
- 16.6 Usage Notes
- Section 17 D/A Converter
- 17.1 Overview
- 17.1.1 Features
- 17.1.2 Block Diagram
- 17.1.3 Pin Configuration
- 17.1.4 Register Configuration
- 17.2 Register Descriptions
- 17.2.1 D/A Data Registers 0 and 1 (DADR0, DADR1)
- 17.2.2 D/A Control Register (DACR)
- 17.2.3 Module Stop Control Register (MSTPCR)
- 17.3 Operation
- Section 18 RAM
- 18.1 Overview
- 18.1.1 Block Diagram
- 18.1.2 Register Configuration
- 18.2 Register Descriptions
- 18.2.1 System Control Register (SYSCR)
- 18.3 Operation
- 18.4 Usage Note
- Section 19 ROM
- 19.1 Overview
- 19.1.1 Block Diagram
- 19.1.2 Register Configuration
- 19.2 Register Descriptions
- 19.2.1 Mode Control Register (MDCR)
- 19.2.2 Bus Control Register L (BCRL)
- 19.3 Operation
- 19.4 PROM Mode (H8S/2357 ZTAT)
- 19.4.1 PROM Mode Setting
- 19.4.2 Socket Adapter and Memory Map
- 19.5 Programming (H8S/2357 ZTAT)
- 19.5.1 Overview
- 19.5.2 Programming and Verification
- 19.5.3 Programming Precautions
- 19.5.4 Reliability of Programmed Data
- 19.6 Overview of Flash Memory (H8S/2357 F-ZTAT)
- 19.6.1 Features
- 19.6.2 Block Diagram
- 19.6.3 Flash Memory Operating Modes
- 19.6.4 Pin Configuration
- 19.6.5 Register Configuration
- 19.7 Register Descriptions
- 19.7.1 Flash Memory Control Register 1 (FLMCR1)
- 19.7.2 Flash Memory Control Register 2 (FLMCR2)
- 19.7.3 Erase Block Registers 1 and 2 (EBR1, EBR2)
- 19.7.4 System Control Register 2 (SYSCR2)
- 19.7.5 RAM Emulation Register (RAMER)
- 19.8 On-Board Programming Modes
- 19.8.1 Boot Mode
- 19.8.2 User Program Mode
- 19.9 Programming/Erasing Flash Memory
- 19.9.1 Program Mode
- 19.9.2 Program-Verify Mode
- 19.9.3 Erase Mode
- 19.9.4 Erase-Verify Mode
- 19.10 Flash Memory Protection
- 19.10.1 Hardware Protection
- 19.10.2 Software Protection
- 19.10.3 Error Protection
- 19.11 Flash Memory Emulation in RAM
- 19.11.1 Emulation in RAM
- 19.11.2 RAM Overlap
- 19.12 Interrupt Handling when Programming/Erasing Flash Memory
- 19.13 Flash Memory Programmer Mode
- 19.13.1 Programmer Mode Setting
- 19.13.2 Socket Adapters and Memory Map
- 19.13.3 Programmer Mode Operation
- 19.13.4 Memory Read Mode
- 19.13.5 Auto-Program Mode
- 19.13.6 Auto-Erase Mode
- 19.13.7 Status Read Mode
- 19.13.8 Status Polling
- 19.13.9 Programmer Mode Transition Time
- 19.13.10 Notes on Memory Programming
- 19.14 Flash Memory Programming and Erasing Precautions
- 19.15 Overview of Flash Memory (H8S/2398 F-ZTAT)
- 19.15.1 Features
- 19.15.2 Overview
- 19.15.3 Flash Memory Operating Modes
- 19.15.4 On-Board Programming Modes
- 19.15.5 Flash Memory Emulation in RAM
- 19.15.6 Differences between Boot Mode and User Program Mode
- 19.15.7 Block Configuration
- 19.15.8 Pin Configuration
- 19.15.9 Register Configuration
- 19.16 Register Descriptions
- 19.16.1 Flash Memory Control Register 1 (FLMCR1)
- 19.16.2 Flash Memory Control Register 2 (FLMCR2)
- 19.16.3 Erase Block Register 1 (EBR1)
- 19.16.4 Erase Block Registers 2 (EBR2)
- 19.16.5 System Control Register 2 (SYSCR2)
- 19.16.6 RAM Emulation Register (RAMER)
- 19.17 On-Board Programming Modes
- 19.17.1 Boot Mode
- 19.17.2 User Program Mode
- 19.18 Programming/Erasing Flash Memory
- 19.18.1 Program Mode
- 19.18.2 Program-Verify Mode
- 19.18.3 Erase Mode
- 19.18.4 Erase-Verify Mode
- 19.19 Flash Memory Protection
- 19.19.1 Hardware Protection
- 19.19.2 Software Protection
- 19.19.3 Error Protection
- 19.20 Flash Memory Emulation in RAM
- 19.20.1 Emulation in RAM
- 19.20.2 RAM Overlap
- 19.21 Interrupt Handling when Programming/Erasing Flash Memory
- 19.22 Flash Memory Programmer Mode
- 19.22.1 Programmer Mode Setting
- 19.22.2 Socket Adapters and Memory Map
- 19.22.3 Programmer Mode Operation
- 19.22.4 Memory Read Mode
- 19.22.5 Auto-Program Mode
- 19.22.6 Auto-Erase Mode
- 19.22.7 Status Read Mode
- 19.22.8 Status Polling
- 19.22.9 Programmer Mode Transition Time
- 19.22.10 Notes on Memory Programming
- 19.23 Flash Memory Programming and Erasing Precautions
- Section 20 Clock Pulse Generator
- 20.1 Overview
- 20.1.1 Block Diagram
- 20.1.2 Register Configuration
- 20.2 Register Descriptions
- 20.2.1 System Clock Control Register (SCKCR)
- 20.3 Oscillator
- 20.3.1 Connecting a Crystal Resonator
- 20.3.2 External Clock Input
- 20.4 Duty Adjustment Circuit
- 20.5 Medium-Speed Clock Divider
- 20.6 Bus Master Clock Selection Circuit
- Section 21 Power-Down Modes
- 21.1 Overview
- 21.1.1 Register Configuration
- 21.2 Register Descriptions
- 21.2.1 Standby Control Register (SBYCR)
- 21.2.2 System Clock Control Register (SCKCR)
- 21.2.3 Module Stop Control Register (MSTPCR)
- 21.3 Medium-Speed Mode
- 21.4 Sleep Mode
- 21.5 Module Stop Mode
- 21.5.1 Module Stop Mode
- 21.5.2 Usage Notes
- 21.6 Software Standby Mode
- 21.6.1 Software Standby Mode
- 21.6.2 Clearing Software Standby Mode
- 21.6.3 Setting Oscillation Stabilization Time after Clearing Software Standby Mode
- 21.6.4 Software Standby Mode Application Example
- 21.6.5 Usage Notes
- 21.7 Hardware Standby Mode
- 21.7.1 Hardware Standby Mode
- 21.7.2 Hardware Standby Mode Timing
- 21.8 Clock Output Disabling Function
- Section 22 Electrical Characteristics
- 22.1 Electrical Characteristics of Mask ROM Version (H8S/2398) and ROMless Versions (H8S/2394, H8S/2392, and H8S/2390)
- 22.1.1 Absolute Maximum Ratings
- 22.1.2 DC Characteristics
- 22.1.3 AC Characteristics
- 22.1.4 A/D Conversion Characteristics
- 22.1.5 D/A Conversion Characteristics
- 22.2 Usage Note (Internal Voltage Step Down for the H8S/2398, H8S/2394, H8S/2392, and H8S/2390)
- 22.3 Electrical Characteristics of H8S/2398 F-ZTAT
- 22.3.1 Absolute Maximum Ratings
- 22.3.2 DC Characteristics
- 22.3.3 AC Characteristics
- 22.3.4 A/D Conversion Characteristics
- 22.3.5 D/A Conversion Characteristics
- 22.3.6 Flash Memory Characteristics
- 22.4 Notes on Use
- 22.5 Usage Note (Internal Voltage Step Down for the H8S/2398 F-ZTAT)
- 22.6 Electrical Characteristics of H8S/2357 Mask ROM and ZTAT Versions, and H8S/2352
- 22.6.1 Absolute Maximum Ratings
- 22.6.2 DC Characteristics
- 22.6.3 AC Characteristics
- 22.6.4 A/D Conversion Characteristics
- 22.6.5 D/A Convervion Characteristics
- 22.7 Electrical Characteristics of H8S/2357 F-ZTAT Version
- 22.7.1 Absolute Maximum Ratings
- 22.7.2 DC Characteristics
- 22.7.3 AC Characteristics
- 22.7.4 A/D Conversion Characteristics
- 22.7.5 D/A Conversion Characteristics
- 22.7.6 Flash Memory Characteristics
- 22.8 Usage Note
- Appendix
- Appendix A Instruction Set
- A.1 Instruction List
- A.2 Instruction Codes
- A.3 Operation Code Map
- A.4 Number of States Required for Instruction Execution
- A.5 Bus States During Instruction Execution
- A.6 Condition Code Modification
- Appendix B Internal I/O Register
- B.1 Addresses
- B.2 Functions
- Appendix C I/O Port Block Diagrams
- C.1 Port 1 Block Diagram
- C.2 Port 2 Block Diagram
- C.3 Port 3 Block Diagram
- C.4 Port 4 Block Diagram
- C.5 Port 5 Block Diagram
- C.6 Port 6 Block Diagram
- C.7 Port A Block Diagram
- C.8 Port B Block Diagram
- C.9 Port C Block Diagram
- C.10 Port D Block Diagram
- C.11 Port E Block Diagram
- C.12 Port F Block Diagram
- C.13 Port G Block Diagram
- Appendix D Pin States
- D.1 Port States in Each Mode
- Appendix E Pin States at Power-On
- E.1 When Pins Settle from an Indeterminate State at Power-On
- E.2 When Pins Settle from the High-Impedance State at Power-On
- Appendix F Timing of Transition to and Recovery from Hardware Standby Mode
- F.1 Timing of Transition to Hardware Standby Mode
- F.2 Timing of Recovery from Hardware Standby Mode
- Appendix G Product Code Lineup
- Appendix H Package Dimensions
- colophon
Regarding the change of names mentioned in the document, such as Hitachi
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The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas
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Renesas Technology Home Page: http://www.renesas.com
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
To all our customers
Cautions
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Hitachi 16-Bit Single-chip Microcomputer
H8S/2357 Series,
H8S/2357
H8S/2352
H8S/2390
H8S/2392
H8S/2394
H8S/2398
H8S/2357F-ZTAT
TM
H8S/2398F-ZTAT
TM
Hardware Manual
ADE-602-146D
Rev. 5.0
11/22/02
Hitachi, Ltd.
The revision list can be viewed directly by
clicking the title page.
The rivision list summarizes the locations of
revisions and additions. Details should always
be checked by referring to the relevant text.
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi's or any third party's
patent, copyright, trademark, or other intellectual property rights for information contained in
this document. Hitachi bears no responsibility for problems that may arise with third party's
rights, including intellectual property rights, in connection with use of the information
contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you
have received the latest product standards or specifications before final design, purchase or
use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability.
However, contact Hitachi's sales office before using the product in an application that
demands especially high quality and reliability or where its failure or malfunction may directly
threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear
power, combustion control, transportation, traffic, safety equipment or medical equipment for
life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi
particularly for maximum rating, operating supply voltage range, heat radiation characteristics,
installation conditions and other characteristics. Hitachi bears no responsibility for failure or
damage when used beyond the guaranteed ranges. Even within the guaranteed ranges,
consider normally foreseeable failure rates or failure modes in semiconductor devices and
employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi
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the Hitachi product.
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6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document
without written approval from Hitachi.
7. Contact Hitachi's sales office for any questions regarding this document or Hitachi
semiconductor products.
General Precautions on Handling of Product
1. Treatment of NC Pins
Note: Do not connect anything to the NC pins.
The NC (not connected) pins are either not connected to any of the internal circuitry or are they
are used as test pins or to reduce noise. If something is connected to the NC pins, the operation
of the LSI is not guaranteed.
2. Treatment of Unused Input Pins
Note: Fix all unused input pins to high or low level.
Generally, the input pins of CMOS products are high-impedance input pins. If unused pins are
in their open states, intermediate levels are induced by noise in the vicinity, a pass-through
current flows internally, and a malfunction may occur.
3. Processing before Initialization
Note: When power is first supplied, the product's state is undefined.
The states of internal circuits are undefined until full power is supplied throughout the chip and
a low level is input on the reset pin. During the period where the states are undefined, the
register settings and the output state of each pin are also undefined. Design your system so
that it does not malfunction because of processing while it is in this undefined state. For those
products which have a reset function, reset the LSI immediately after the power supply has
been turned on.
4. Prohibition of Access to Undefined or Reserved Addresses
Note: Access to undefined or reserved addresses is prohibited.
The undefined or reserved addresses may be used to expand functions, or test registers may
have been be allocated to these addresses. Do not access these registers; the system's
operation is not guaranteed if they are accessed.