Document Outline
- Cover
- Cautions
- General Precautions on the Handling of Products
- Preface
- List of Items Revised or Added for This Version
- Comparison of H8S/2633,H8S/2632,H8S/2631, H8S/2633F-ZTAT,H8S/2633RF-ZTAT,and H8S/2695 Product Specifications
- Contents
- Section 1 Overview
- 1.1 Overview
- 1.2 Internal Block Diagram
- 1.3 Pin Description
- 1.3.1 Pin Arrangement
- 1.3.2 Pin Functions in Each Operating Mode
- 1.3.3 Pin Functions
- Section 2 CPU
- 2.1 Overview
- 2.1.1 Features
- 2.1.2 Differences between H8S/2600 CPU and H8S/2000 CPU
- 2.1.3 Differences from H8/300 CPU
- 2.1.4 Differences from H8/300H CPU
- 2.2 CPU Operating Modes
- 2.3 Address Space
- 2.4 Register Configuration
- 2.4.1 Overview
- 2.4.2 General Registers
- 2.4.3 Control Registers
- 2.4.4 Initial Register Values
- 2.5 Data Formats
- 2.5.1 General Register Data Formats
- 2.5.2 Memory Data Formats
- 2.6 Instruction Set
- 2.6.1 Overview
- 2.6.2 Instructions and Addressing Modes
- 2.6.3 Table of Instructions Classified by Function
- 2.6.4 Basic Instruction Formats
- 2.7 Addressing Modes and Effective Address Calculation
- 2.7.1 Addressing Mode
- 2.7.2 Effective Address Calculation
- 2.8 Processing States
- 2.8.1 Overview
- 2.8.2 Reset State
- 2.8.3 Exception-Handling State
- 2.8.4 Program Execution State
- 2.8.5 Bus-Released State
- 2.8.6 Power-Down State
- 2.9 Basic Timing
- 2.9.1 Overview
- 2.9.2 On-Chip Memory (ROM,RAM)
- 2.9.3 On-Chip Supporting Module Access Timing
- 2.9.4 External Address Space Access Timing
- 2.10 Usage Note
- Section 3 MCU Operating Modes
- 3.1 Overview
- 3.1.1 Operating Mode Selection
- 3.1.2 Register Configuration
- 3.2 Register Descriptions
- 3.2.1 Mode Control Register (MDCR)
- 3.2.2 System Control Register (SYSCR)
- 3.2.3 Pin Function Control Register (PFCR)
- 3.3 Operating Mode Descriptions
- 3.3.1 Mode 4
- 3.3.2 Mode 5
- 3.3.3 Mode 6
- 3.3.4 Mode 7
- 3.4 Pin Functions in Each Operating Mode
- 3.5 Address Map in Each Operating Mode
- Section 4 Exception Handling
- 4.1 Overview
- 4.1.1 Exception Handling Types and Priority
- 4.1.2 Exception Handling Operation
- 4.1.3 Exception Vector Table
- 4.2 Reset
- 4.2.1 Overview
- 4.2.2 Types of Reset
- 4.2.3 Reset Sequence
- 4.2.4 Interrupts after Reset
- 4.2.5 State of On-Chip Supporting Modules after Reset Release
- 4.3 Traces
- 4.4 Interrupts
- 4.5 Trap Instruction
- 4.6 Stack Status after Exception Handling
- 4.7 Notes on Use of the Stack
- Section 5 Interrupt Controller
- 5.1 Overview
- 5.1.1 Features
- 5.1.2 Block Diagram
- 5.1.3 Pin Configuration
- 5.1.4 Register Configuration
- 5.2 Register Descriptions
- 5.2.1 System Control Register (SYSCR)
- 5.2.2 Interrupt Priority Registers A to L,O (IPRA to IPRL,IPRO)
- 5.2.3 IRQ Enable Register (IER)
- 5.2.4 IRQ Sense Control Registers H and L (ISCRH,ISCRL)
- 5.2.5 IRQ Status Register (ISR)
- 5.3 Interrupt Sources
- 5.3.1 External Interrupts
- 5.3.2 Internal Interrupts
- 5.3.3 Interrupt Exception Handling Vector Table
- 5.4 Interrupt Operation
- 5.4.1 Interrupt Control Modes and Interrupt Operation
- 5.4.2 Interrupt Control Mode 0
- 5.4.3 Interrupt Control Mode 2
- 5.4.4 Interrupt Exception Handling Sequence
- 5.4.5 Interrupt Response Times
- 5.5 Usage Notes
- 5.5.1 Contention between Interrupt Generation and Disabling
- 5.5.2 Instructions that Disable Interrupts
- 5.5.3 Times when Interrupts are Disabled
- 5.5.4 Interrupts during Execution of EEPMOV Instruction
- 5.6 DTC and DMAC Activation by Interrupt (DMAC and DTC functions are not available in the H8S/2695 )
- 5.6.1 Overview
- 5.6.2 Block Diagram
- 5.6.3 Operation (DMAC and DTC functions are not available in the H8S/2695)
- Section 6 PC Break Controller (PBC) (This function is not available in the H8S/2695)
- 6.1 Overview
- 6.1.1 Features
- 6.1.2 Block Diagram
- 6.1.3 Register Configuration
- 6.2 Register Descriptions
- 6.2.1 Break Address Register A (BARA)
- 6.2.2 Break Address Register B (BARB)
- 6.2.3 Break Control Register A (BCRA)
- 6.2.4 Break Control Register B (BCRB)
- 6.2.5 Module Stop Control Register C (MSTPCRC)
- 6.3 Operation
- 6.3.1 PC Break Interrupt Due to Instruction Fetch
- 6.3.2 PC Break Interrupt Due to Data Access
- 6.3.3 Notes on PC Break Interrupt Handling
- 6.3.4 Operation in Transitions to Power-Down Modes
- 6.3.5 PC Break Operation in Continuous Data Transfer
- 6.3.6 When Instruction Execution is Delayed by One State
- 6.3.7 Additional Notes
- Section 7 Bus Controller
- 7.1 Overview
- 7.1.1 Features
- 7.1.2 Block Diagram
- 7.1.3 Pin Configuration
- 7.1.4 Register Configuration
- 7.2 Register Descriptions
- 7.2.1 Bus Width Control Register (ABWCR)
- 7.2.2 Access State Control Register (ASTCR)
- 7.2.3 Wait Control Registers H and L (WCRH,WCRL)
- 7.2.4 Bus Control Register H (BCRH)
- 7.2.5 Bus Control Register L (BCRL)
- 7.2.6 Pin Function Control Register (PFCR)
- 7.2.7 Memory Control Register (MCR)
- 7.2.8 DRAM Control Register (DRAMCR)
- 7.2.9 Refresh Timer Counter (RTCNT)
- 7.2.10 Refresh Time Constant Register (RTCOR)
- 7.3 Overview of Bus Control
- 7.3.1 Area Partitioning
- 7.3.2 Bus Specifications
- 7.3.3 Memory Interfaces
- 7.3.4 Interface Specifications for Each Area
- 7.3.5 Chip Select Signals
- 7.4 Basic Bus Interface
- 7.4.1 Overview
- 7.4.2 Data Size and Data Alignment
- 7.4.3 Valid Strobes
- 7.4.4 Basic Timing
- 7.4.5 Wait Control
- 7.5 DRAM Interface (This function is not available in the H8S/2695 )
- 7.5.1 Overview
- 7.5.2 Setting up DRAM Space
- 7.5.3 Address Multiplexing
- 7.5.4 Data Bus
- 7.5.5 DRAM Interface Pins
- 7.5.6 Basic Timing
- 7.5.7 Precharge State Control
- 7.5.8 Wait Control
- 7.5.9 Byte Access Control
- 7.5.10 Burst Operation
- 7.5.11 Refresh Control
- 7.6 DMAC Single Address Mode and DRAM Interface (This function is not available in the H8S/2695 )
- 7.7 Burst ROM Interface
- 7.7.1 Overview
- 7.7.2 Basic Timing
- 7.7.3 Wait Control
- 7.8 Idle Cycle
- 7.8.1 Operation
- 7.8.2 Pin States in Idle Cycle
- 7.9 Write Data Buffer Function
- 7.10 Bus Release
- 7.10.1 Overview
- 7.10.2 Operation
- 7.10.3 Pin States in External Bus Released State
- 7.10.4 Transition Timing
- 7.10.5 Notes
- 7.11 Bus Arbitration (DMAC and DTC functions are not available in the H8S/2695 )
- 7.11.1 Overview
- 7.11.2 Operation
- 7.11.3 Bus Transfer Timing
- 7.12 Resets and the Bus Controller
- Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695 )
- 8.1 Overview
- 8.1.1 Features
- 8.1.2 Block Diagram
- 8.1.3 Overview of Functions
- 8.1.4 Pin Configuration
- 8.1.5 Register Configuration
- 8.2 Register Descriptions (1)(Short Address Mode)
- 8.2.1 Memory Address Registers (MAR)
- 8.2.2 I/O Address Register (IOAR)
- 8.2.3 Execute Transfer Count Register (ETCR)
- 8.2.4 DMA Control Register (DMACR)
- 8.2.5 DMA Band Control Register (DMABCR)
- 8.3 Register Descriptions (2)(Full Address Mode)
- 8.3.1 Memory Address Register (MAR)
- 8.3.2 I/O Address Register (IOAR)
- 8.3.3 Execute Transfer Count Register (ETCR)
- 8.3.4 DMA Control Register (DMACR)
- 8.3.5 DMA Band Control Register (DMABCR)
- 8.4 Register Descriptions (3)
- 8.4.1 DMA Write Enable Register (DMAWER)
- 8.4.2 DMA Terminal Control Register (DMATCR)
- 8.4.3 Module Stop Control Register (MSTPCR)
- 8.5 Operation
- 8.5.1 Transfer Modes
- 8.5.2 Sequential Mode
- 8.5.3 Idle Mode
- 8.5.4 Repeat Mode
- 8.5.5 Single Address Mode
- 8.5.6 Normal Mode
- 8.5.7 Block Transfer Mode
- 8.5.8 DMAC Activation Sources
- 8.5.9 Basic DMAC Bus Cycles
- 8.5.10 DMAC Bus Cycles (Dual Address Mode)
- 8.5.11 DMAC Bus Cycles (Single Address Mode)
- 8.5.12 Write Data Buffer Function
- 8.5.13 DMAC Multi-Channel Operation
- 8.5.14 Relation between External Bus Requests,Refresh Cycles,the DTC,and the DMAC
- 8.5.15 NMI Interrupts and DMAC
- 8.5.16 Forced Termination of DMAC Operation
- 8.5.17 Clearing Full Address Mode
- 8.6 Interrupts
- 8.7 Usage Notes
- Section 9 Data Transfer Controller (DTC) (This function is not available in the H8S/2695 )
- 9.1 Overview
- 9.1.1 Features
- 9.1.2 Block Diagram
- 9.1.3 Register Configuration
- 9.2 Register Descriptions
- 9.2.1 DTC Mode Register A (MRA)
- 9.2.2 DTC Mode Register B (MRB)
- 9.2.3 DTC Source Address Register (SAR)
- 9.2.4 DTC Destination Address Register (DAR)
- 9.2.5 DTC Transfer Count Register A (CRA)
- 9.2.6 DTC Transfer Count Register B (CRB)
- 9.2.7 DTC Enable Registers (DTCER)
- 9.2.8 DTC Vector Register (DTVECR)
- 9.2.9 Module Stop Control Register A (MSTPCRA)
- 9.3 Operation
- 9.3.1 Overview
- 9.3.2 Activation Sources
- 9.3.3 DTC Vector Table
- 9.3.4 Location of Register Information in Address Space
- 9.3.5 Normal Mode
- 9.3.6 Repeat Mode
- 9.3.7 Block Transfer Mode
- 9.3.8 Chain Transfer
- 9.3.9 Operation Timing
- 9.3.10 Number of DTC Execution States
- 9.3.11 Procedures for Using DTC
- 9.3.12 Examples of Use of the DTC
- 9.4 Interrupts
- 9.5 Usage Notes
- Section 10A I/O Ports (H8S/2633,H8S/2632,H8S/2631,H8S/2633R)
- 10A.1 Overview
- 10A.2 Port 1
- 10A.2.1 Overview
- 10A.2.2 Register Configuration
- 10A.2.3 Pin Functions
- 10A.3 Port 3
- 10A.3.1 Overview
- 10A.3.2 Register Configuration
- 10A.3.3 Pin Functions
- 10A.4 Port 4
- 10A.4.1 Overview
- 10A.4.2 Register Configuration
- 10A.4.3 Pin Functions
- 10A.5 Port 7
- 10A.5.1 Overview
- 10A.5.2 Register Configuration
- 10A.5.3 Pin Functions
- 10A.6 Port 9
- 10A.6.1 Overview
- 10A.6.2 Register Configuration
- 10A.6.3 Pin Functions
- 10A.7 Port A
- 10A.7.1 Overview
- 10A.7.2 Register Configuration
- 10A.7.3 Pin Functions
- 10A.7.4 MOS Input Pull-Up Function
- 10A.8 Port B
- 10A.8.1 Overview
- 10A.8.2 Register Configuration
- 10A.8.3 Pin Functions
- 10A.8.4 MOS Input Pull-Up Function
- 10A.9 Port C
- 10A.9.1 Overview
- 10A.9.2 Register Configuration
- 10A.9.3 Pin Functions for Each Mode
- 10A.9.4 MOS Input Pull-Up Function
- 10A.10 Port D
- 10A.10.1 Overview
- 10A.10.2 Register Configuration
- 10A.10.3 Pin Functions
- 10A.10.4 MOS Input Pull-Up Function
- 10A.11 Port E
- 10A.11.1 Overview
- 10A.11.2 Register Configuration
- 10A.11.3 Pin Functions
- 10A.11.4 MOS Input Pull-Up Function
- 10A.12 Port F
- 10A.12.1 Overview
- 10A.12.2 Register Configuration
- 10A.12.3 Pin Functions
- 10A.13 Port G
- 10A.13.1 Overview
- 10A.13.2 Register Configuration
- 10A.13.3 Pin Functions
- Section 10B I/O Ports (H8S/2695)
- 10B.1 Overview
- 10B.2 Port 1
- 10B.2.1 Overview
- 10B.2.2 Register Configuration
- 10B.2.3 Pin Functions
- 10B.3 Port 3
- 10B.3.1 Overview
- 10B.3.2 Register Configuration
- 10B.3.3 Pin Functions
- 10B.4 Port 4
- 10B.4.1 Overview
- 10B.4.2 Register Configuration
- 10B.4.3 Pin Functions
- 10B.5 Port 7
- 10B.5.1 Overview
- 10B.5.2 Register Configuration
- 10B.5.3 Pin Functions
- 10B.6 Port 9
- 10B.6.1 Overview
- 10B.6.2 Register Configuration
- 10B.6.3 Pin Functions
- 10B.7 Port A
- 10B.7.1 Overview
- 10B.7.2 Register Configuration
- 10B.7.3 Pin Functions
- 10B.7.4 MOS Input Pull-Up Function
- 10B.8 Port B
- 10B.8.1 Overview
- 10B.8.2 Register Configuration
- 10B.8.3 Pin Functions
- 10B.8.4 MOS Input Pull-Up Function
- 10B.9 Port C
- 10B.9.1 Overview
- 10B.9.2 Register Configuration
- 10B.9.3 Pin Functions for Each Mode
- 10B.9.4 MOS Input Pull-Up Function
- 10B.10 Port D
- 10B.10.1 Overview
- 10B.10.2 Register Configuration
- 10B.10.3 Pin Functions
- 10B.10.4 MOS Input Pull-Up Function
- 10B.11 Port E
- 10B.11.1 Overview
- 10B.11.2 Register Configuration
- 10B.11.3 Pin Functions
- 10B.11.4 MOS Input Pull-Up Function
- 10B.12 Port F
- 10B.12.1 Overview
- 10B.12.2 Register Configuration
- 10B.12.3 Pin Functions
- 10B.13 Port G
- 10B.13.1 Overview
- 10B.13.2 Register Configuration
- 10B.13.3 Pin Functions
- Section 11 16-Bit Timer Pulse Unit (TPU)
- 11.1 Overview
- 11.1.1 Features
- 11.1.2 Block Diagram
- 11.1.3 Pin Configuration
- 11.1.4 Register Configuration
- 11.2 Register Descriptions
- 11.2.1 Timer Control Register (TCR)
- 11.2.2 Timer Mode Register (TMDR)
- 11.2.3 Timer I/O Control Register (TIOR)
- 11.2.4 Timer Interrupt Enable Register (TIER)
- 11.2.5 Timer Status Register (TSR)
- 11.2.6 Timer Counter (TCNT)
- 11.2.7 Timer General Register (TGR)
- 11.2.8 Timer Start Register (TSTR)
- 11.2.9 Timer Synchro Register (TSYR)
- 11.2.10 Module Stop Control Register A (MSTPCRA)
- 11.3 Interface to Bus Master
- 11.3.1 16-Bit Registers
- 11.3.2 8-Bit Registers
- 11.4 Operation
- 11.4.1 Overview
- 11.4.2 Basic Functions
- 11.4.3 Synchronous Operation
- 11.4.4 Buffer Operation
- 11.4.5 Cascaded Operation
- 11.4.6 PWM Modes
- 11.4.7 Phase Counting Mode
- 11.5 Interrupts
- 11.5.1 Interrupt Sources and Priorities
- 11.5.2 DTC/DMAC Activation (This function is not available in the H8S/2695)
- 11.5.3 A/D Converter Activation
- 11.6 Operation Timing
- 11.6.1 Input/Output Timing
- 11.6.2 Interrupt Signal Timing
- 11.7 Usage Notes
- Section 12 Programmable Pulse Generator (PPG) (This function is not available in the H8S/2695)
- 12.1 Overview
- 12.1.1 Features
- 12.1.2 Block Diagram
- 12.1.3 Pin Configuration
- 12.1.4 Registers
- 12.2 Register Descriptions
- 12.2.1 Next Data Enable Registers H and L (NDERH,NDERL)
- 12.2.2 Output Data Registers H and L (PODRH,PODRL)
- 12.2.3 Next Data Registers H and L (NDRH,NDRL)
- 12.2.4 Notes on NDR Access
- 12.2.5 PPG Output Control Register (PCR)
- 12.2.6 PPG Output Mode Register (PMR)
- 12.2.7 Port 1 Data Direction Register (P1DDR)
- 12.2.8 Module Stop Control Register A (MSTPCRA)
- 12.3 Operation
- 12.3.1 Overview
- 12.3.2 Output Timing
- 12.3.3 Normal Pulse Output
- 12.3.4 Non-Overlapping Pulse Output
- 12.3.5 Inverted Pulse Output
- 12.3.6 Pulse Output Triggered by Input Capture
- 12.4 Usage Notes
- Section 13 8-Bit Timers (TMR) (This function is not available in the H8S/2695)
- 13.1 Overview
- 13.1.1 Features
- 13.1.2 Block Diagram
- 13.1.3 Pin Configuration
- 13.1.4 Register Configuration
- 13.2 Register Descriptions
- 13.2.1 Timer Counters 0 to 3 (TCNT0 to TCNT3)
- 13.2.2 Time Constant Registers A0 to A3 (TCORA0 to TCORA3)
- 13.2.3 Time Constant Registers B0 to B3 (TCORB0 to TCORB3)
- 13.2.4 Timer Control Registers 0 to 3 (TCR0 to TCR3)
- 13.2.5 Timer Control/Status Registers 0 to 3 (TCSR0 to TCSR3)
- 13.2.6 Module Stop Control Register A (MSTPCRA)
- 13.3 Operation
- 13.3.1 TCNT Incrementation Timing
- 13.3.2 Compare Match Timing
- 13.3.3 Timing of External RESET on TCNT
- 13.3.4 Timing of Overflow Flag (OVF)Setting
- 13.3.5 Operation with Cascaded Connection
- 13.4 Interrupts
- 13.4.1 Interrupt Sources and DTC Activation (The H8S/2695 does not have a DTC function or an 8-bit timer)
- 13.4.2 A/D Converter Activation
- 13.5 Sample Application
- 13.6 Usage Notes
- 13.6.1 Contention between TCNT Write and Clear
- 13.6.2 Contention between TCNT Write and Increment
- 13.6.3 Contention between TCOR Write and Compare Match
- 13.6.4 Contention between Compare Matches A and B
- 13.6.5 Switching of Internal Clocks and TCNT Operation
- 13.6.6 Interrupts and Module Stop Mode
- Section 14 14-Bit PWM D/A (This function is not available in the H8S/2695)
- 14.1 Overview
- 14.1.1 Features
- 14.1.2 Block Diagram
- 14.1.3 Pin Configuration
- 14.1.4 Register Configuration
- 14.2 Register Descriptions
- 14.2.1 PWM D/A Counter (DACNT)
- 14.2.2 PWM D/A Data Registers A and B (DADRA and DADRB)
- 14.2.3 PWM D/A Control Register (DACR)
- 14.2.4 Module Stop Control Register B (MSTPCRB)
- 14.3 Bus Master Interface
- 14.4 Operation
- Section 15 Watchdog Timer (WDT1 is not available in the H8S/2695)
- 15.1 Overview
- 15.1.1 Features
- 15.1.2 Block Diagram
- 15.1.3 Pin Configuration
- 15.1.4 Register Configuration
- 15.2 Register Descriptions
- 15.2.1 Timer Counter (TCNT)
- 15.2.2 Timer Control/Status Register (TCSR)
- 15.2.3 Reset Control/Status Register (RSTCSR)
- 15.2.4 Pin Function Control Register (PFCR)
- 15.2.5 Notes on Register Access
- 15.3 Operation
- 15.3.1 Watchdog Timer Operation
- 15.3.2 Interval Timer Operation
- 15.3.3 Timing of Setting Overflow Flag (OVF)
- 15.3.4 Timing of Setting of Watchdog Timer Overflow Flag (WOVF)
- 15.4 Interrupts
- 15.5 Usage Notes
- 15.5.1 Contention between Timer Counter (TCNT)Write and Increment
- 15.5.2 Changing Value of PSS and CKS2 to CKS0
- 15.5.3 Switching between Watchdog Timer Mode and Interval Timer Mode
- 15.5.4 System Reset by WDTOVF Signal
- 15.5.5 Internal Reset in Watchdog Timer Mode
- 15.5.6 OVF Flag Clearing in Interval Timer Mode
- Section 16 Serial Communication Interface (SCI,IrDA) (The H8S/2695 is not equipped with an IrDA function)
- 16.1 Overview
- 16.1.1 Features
- 16.1.2 Block Diagram
- 16.1.3 Pin Configuration
- 16.1.4 Register Configuration
- 16.2 Register Descriptions
- 16.2.1 Receive Shift Register (RSR)
- 16.2.2 Receive Data Register (RDR)
- 16.2.3 Transmit Shift Register (TSR)
- 16.2.4 Transmit Data Register (TDR)
- 16.2.5 Serial Mode Register (SMR)
- 16.2.6 Serial Control Register (SCR)
- 16.2.7 Serial Status Register (SSR)
- 16.2.8 Bit Rate Register (BRR)
- 16.2.9 Smart Card Mode Register (SCMR)
- 16.2.10 IrDA Control Register (IrCR)
- 16.2.11 Module Stop Control Registers B and C (MSTPCRB,MSTPCRC)
- 16.3 Operation
- 16.3.1 Overview
- 16.3.2 Operation in Asynchronous Mode
- 16.3.3 Multiprocessor Communication Function
- 16.3.4 Operation in Clocked Synchronous Mode
- 16.3.5 IrDA Operation
- 16.4 SCI Interrupts
- 16.5 Usage Notes
- Section 17 Smart Card Interface
- 17.1 Overview
- 17.1.1 Features
- 17.1.2 Block Diagram
- 17.1.3 Pin Configuration
- 17.1.4 Register Configuration
- 17.2 Register Descriptions
- 17.2.1 Smart Card Mode Register (SCMR)
- 17.2.2 Serial Status Register (SSR)
- 17.2.3 Serial Mode Register (SMR)
- 17.2.4 Serial Control Register (SCR)
- 17.3Operation
- 17.3.1 Overview
- 17.3.2 Pin Connections
- 17.3.3 Data Format
- 17.3.4 Register Settings
- 17.3.5 Clock
- 17.3.6 Data Transfer Operations
- 17.3.7 Operation in GSM Mode
- 17.3.8 Operation in Block Transfer Mode
- 17.4 Usage Notes
- Section 18 I2C Bus Interface [Option ] (This function is not available in the H8S/2695)
- 18.1 Overview
- 18.1.1 Features
- 18.1.2 Block Diagram
- 18.1.3 Input/Output Pins
- 18.1.4 Register Configuration
- 18.2 Register Descriptions
- 18.2.1 I2C Bus Data Register (ICDR)
- 18.2.2 Slave Address Register (SAR)
- 18.2.3 Second Slave Address Register (SARX)
- 18.2.4 I2C Bus Mode Register (ICMR)
- 18.2.5 I2C Bus Control Register (ICCR)
- 18.2.6 I2C Bus Status Register (ICSR)
- 18.2.7 Serial Control Register X (SCRX)
- 18.2.8 DDC Switch Register (DDCSWR)
- 18.2.9 Module Stop Control Register B (MSTPCRB)
- 18.3 Operation
- 18.3.1 I2C Bus Data Format
- 18.3.2 Initial Setting
- 18.3.3 Master Transmit Operation
- 18.3.4 Master Receive Operation
- 18.3.5 Slave Receive Operation
- 18.3.6 Slave Transmit Operation
- 18.3.7 IRIC Setting Timing and SCL Control
- 18.3.8 Operation Using the DTC
- 18.3.9 Noise Canceler
- 18.3.10 Sample Flowcharts
- 18.3.11 Initialization of Internal State
- 18.4 Usage Notes
- Section 19 A/D Converter
- 19.1 Overview
- 19.1.1 Features
- 19.1.2 Block Diagram
- 19.1.3 Pin Configuration
- 19.1.4 Register Configuration
- 19.2 Register Descriptions
- 19.2.1 A/D Data Registers A to D (ADDRA to ADDRD)
- 19.2.2 A/D Control/Status Register (ADCSR)
- 19.2.3 A/D Control Register (ADCR)
- 19.2.4 Module Stop Control Register A (MSTPCRA)
- 19.3 Interface to Bus Master
- 19.4 Operation
- 19.4.1 Single Mode (SCAN =0)
- 19.4.2 Scan Mode (SCAN =1)
- 19.4.3 Input Sampling and A/D Conversion Time
- 19.4.4 External Trigger Input Timing
- 19.5 Interrupts
- 19.6 Usage Notes
- Section 20 D/A Converter (This function is not available in the H8S/2695)
- 20.1 Overview
- 20.1.1 Features
- 20.1.2 Block Diagram
- 20.1.3 Input and Output Pins
- 20.1.4 Register Configuration
- 20.2 Register Descriptions
- 20.2.1 D/A Data Registers 0 to 3 (DADR0 to DADR3)
- 20.2.2 D/A Control Register 01 and 23 (DACR01 and DACR23)
- 20.2.3 Module Stop Control Register A and C (MSTPCRA and MSTPCRC)
- 20.3 Operation
- Section 21 RAM
- 21.1 Overview
- 21.1.1 Block Diagram
- 21.1.2 Register Configuration
- 21.2 Register Descriptions
- 21.2.1 System Control Register (SYSCR)
- 21.3 Operation
- 21.4 Usage Notes
- Section 22 ROM
- 22.1 Overview
- 22.1.1 Block Diagram
- 22.1.2 Register Configuration
- 22.2 Register Descriptions
- 22.2.1 Mode Control Register (MDCR)
- 22.3 Operation
- 22.4 Flash Memory Overview
- 22.4.1 Features
- 22.4.2 Overview
- 22.4.3 Flash Memory Operating Modes
- 22.4.4 On-Board Programming Modes
- 22.4.5 Flash Memory Emulation in RAM
- 22.4.6 Differences between Boot Mode and User Program Mode
- 22.4.7 Block Configuration
- 22.4.8 Pin Configuration
- 22.4.9 Register Configuration
- 22.5 Register Descriptions
- 22.5.1 Flash Memory Control Register 1 (FLMCR1)
- 22.5.2 Flash Memory Control Register 2 (FLMCR2)
- 22.5.3 Erase Block Register 1 (EBR1)
- 22.5.4 Erase Block Register 2 (EBR2)
- 22.5.5 RAM Emulation Register (RAMER)
- 22.5.6 Flash Memory Power Control Register (FLPWCR)
- 22.5.7 Serial Control Register X (SCRX)
- 22.6 On-Board Programming Modes
- 22.6.1 Boot Mode
- 22.6.2 User Program Mode
- 22.7 Programming/Erasing Flash Memory
- 22.7.1 Program Mode
- 22.7.2 Program-Verify Mode
- 22.7.3 Erase Mode
- 22.7.4 Erase-Verify Mode
- 22.8 Protection
- 22.8.1 Hardware Protection
- 22.8.2 Software Protection
- 22.8.3 Error Protection
- 22.9 Flash Memory Emulation in RAM
- 22.10 Interrupt Handling when Programming/Erasing Flash Memory
- 22.11 Flash Memory Programmer Mode
- 22.11.1 Socket Adapter Pin Correspondence Diagram
- 22.11.2 Programmer Mode Operation
- 22.11.3 Memory Read Mode
- 22.11.4 Auto-Program Mode
- 22.11.5 Auto-Erase Mode
- 22.11.6 Status Read Mode
- 22.11.7 Status Polling
- 22.11.8 Programmer Mode Transition Time
- 22.11.9 Notes on Memory Programming
- 22.12 Flash Memory and Power-Down States
- 22.12.1 Note on Power-Down States
- 22.13 Flash Memory Programming and Erasing Precautions
- 22.14 Note on Switching from F-ZTAT Version to Mask ROM Version
- Section 23A Clock Pulse Generator (H8S/2633,H8S/2632,H8S/2631,H8S/2633F)
- 23A.1 Overview
- 23A.1.1 Block Diagram
- 23A.1.2 Register Configuration
- 23A.2 Register Descriptions
- 23A.2.1 System Clock Control Register (SCKCR)
- 23A.2.2 Low-Power Control Register (LPWRCR)
- 23A.3 Oscillator
- 23A.3.1 Connecting a Crystal Resonator
- 23A.3.2 External Clock Input
- 23A.4 PLL Circuit
- 23A.5 Medium-Speed Clock Divider
- 23A.6 Bus Master Clock Selection Circuit
- 23A.7 Subclock Oscillator
- 23A.8 Subclock Waveform Shaping Circuit
- 23A.9 Note on Crystal Resonator
- Section 23B Clock Pulse Generator (H8S/2633R,H8S/2695)
- 23B.1 Overview
- 23B.1.1 Block Diagram
- 23B.1.2 Register Configuration
- 23B.2 Register Descriptions
- 23B.2.1 System Clock Control Register (SCKCR)
- 23B.2.2 Low-Power Control Register (LPWRCR)
- 23B.3 Oscillator
- 23B.3.1 Connecting a Crystal Resonator
- 23B.3.2 External Clock Input
- 23B.4 PLL Circuit
- 23B.5 Medium-Speed Clock Divider
- 23B.6 Bus Master Clock Selection Circuit
- 23B.7 Subclock Oscillator (This function is not available in the H8S/2695)
- 23B.8 Subclock Waveform Shaping Circuit
- 23B.9 Note on Crystal Resonator
- Section 24 Power-Down Modes
- 24.1 Overview
- 24.1.1 Register Configuration
- 24.2 Register Descriptions
- 24.2.1 Standby Control Register (SBYCR)
- 24.2.2 System Clock Control Register (SCKCR)
- 24.2.3 Low-Power Control Register (LPWRCR)
- 24.2.4 Timer Control/Status Register (TCSR)
- 24.2.5 Module Stop Control Register (MSTPCR)
- 24.3 Medium-Speed Mode
- 24.4 Sleep Mode
- 24.4.1 Sleep Mode
- 24.4.2 Exiting Sleep Mode
- 24.5 Module Stop Mode
- 24.5.1 Module Stop Mode
- 24.5.2 Usage Notes
- 24.6 Software Standby Mode
- 24.6.1 Software Standby Mode
- 24.6.2 Exiting Software Standby Mode
- 24.6.3 Setting Oscillation Stabilization Time after Clearing Software Standby Mode
- 24.6.4 Software Standby Mode Application Example
- 24.6.5 Usage Notes
- 24.7 Hardware Standby Mode
- 24.7.1 Hardware Standby Mode
- 24.7.2 Hardware Standby Mode Timing
- 24.8 Watch Mode (This function is not available in the H8S/2695)
- 24.8.1 Watch Mode
- 24.8.2 Exiting Watch Mode
- 24.8.3 Notes
- 24.9 Sub-Sleep Mode (This function is not available in the H8S/2695)
- 24.9.1 Sub-Sleep Mode
- 24.9.2 Exiting Sub-Sleep Mode
- 24.10 Sub-Active Mode (This function is not available in the H8S/2695)
- 24.10.1 Sub-Active Mode
- 24.10.2 Exiting Sub-Active Mode
- 24.10.3 Usage Notes
- 24.11 Direct Transitions (This function is not available in the H8S/2695)
- 24.11.1 Overview of Direct Transitions
- 24.12 Clock Output Disabling Function
- Section 25 Electrical Characteristics (H8S/2633,H8S/2632,H8S/2631,H8S/2633F)
- 25.1 Absolute Maximum Ratings
- 25.2 DC Characteristics
- 25.3 AC Characteristics
- 25.3.1 Clock Timing
- 25.3.2 Control Signal Timing
- 25.3.3 Bus Timing
- 25.3.4 DMAC Timing
- 25.3.5 Timing of On-Chip Supporting Modules
- 25.4 A/D Conversion Characteristics
- 25.5 D/A Conversion Characteristics
- 25.6 Flash Memory Characteristics
- 25.7 Usage Note
- Section 26 Electrical Characteristics (H8S/2633R)
- 26.1 Absolute Maximum Ratings
- 26.2 DC Characteristics
- 26.3 AC Characteristics
- 26.3.1 Clock Timing
- 26.3.2 Control Signal Timing
- 26.3.3 Bus Timing
- 26.3.4 DMAC Timing
- 26.3.5 Timing of On-Chip Supporting Modules
- 26.4 A/D Conversion Characteristics
- 26.5 D/A Conversion Characteristics
- 26.6 Flash Memory Characteristics
- 26.7 Usage Note
- Section 27 Electrical Characteristics (H8S/2695)
- 27.1 Absolute Maximum Ratings
- 27.2 DC Characteristics
- 27.3 AC Characteristics
- 27.3.1 Clock Timing
- 27.3.2 Control Signal Timing
- 27.3.3 Bus Timing
- 27.3.4 Timing of On-Chip Supporting Modules
- 27.4 A/D Conversion Characteristics
- 27.5 Usage Note
- Appendix A Instruction Set
- A.1 Instruction List
- A.2Instruction Codes
- A.3 Operation Code Map
- A.4 Number of States Required for Instruction Execution
- A.5 Bus States During Instruction Execution
- A.6 Condition Code Modification
- Appendix B Internal I/O Register
- B.1A Addresses (H8S/2633 Series,H8S/2633F,H8S/2633R)
- B.1B Addresses (H8S/2695)
- B.2 Functions
- Appendix C I/O Port Block Diagrams
- C.1 Port 1 Block Diagram
- C.2 Port 3 Block Diagram
- C.3 Port 4 Block Diagram
- C.4 Port 7 Block Diagram
- C.5Port 9 Block Diagram
- C.6 Port A Block Diagram
- C.7 Port B Block Diagram
- C.8 Port C Block Diagram
- C.9 Port D Block Diagram
- C.10 Port E Block Diagram
- C.11 Port F Block Diagram
- C.12 Port G Block Diagram
- C.13 Port 1 Block Diagram
- C.14 Port 3 Block Diagram
- C.15Port 4 Block Diagram
- C.16 Port 7 Block Diagram
- C.17 Port 9 Block Diagram
- C.18 Port A Block Diagram
- C.19 Port B Block Diagram
- C.20 Port C Block Diagram
- C.21 Port D Block Diagram
- C.22 Port E Block Diagram
- C.23 Port F Block Diagram
- C.24 Port G Block Diagram
- Appendix D Pin States
- D.1 Port States in Each Mode
- Appendix E Timing of Transition to and Recovery from Hardware Standby Mode
- Appendix F Product Code Lineup
- Appendix G Package Dimensions
- Colophon
Regarding the change of names mentioned in the document, such as Hitachi
Electric and Hitachi XX, to Renesas Technology Corp.
The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas
Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog
and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)
Accordingly, although Hitachi, Hitachi, Ltd., Hitachi Semiconductors, and other Hitachi brand
names are mentioned in the document, these names have in fact all been changed to Renesas
Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and
corporate statement, no changes whatsoever have been made to the contents of the document, and
these changes do not constitute any alteration to the contents of the document itself.
Renesas Technology Home Page: http://www.renesas.com
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
To all our customers
Cautions
Keep safety first in your circuit designs!
1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better
and more reliable, but there is always the possibility that trouble may occur with them. Trouble with
semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate
measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or
(iii) prevention against any malfunction or mishap.
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H8S/2633 Series
H8S/2633
HD6432633
H8S/2632
HD6432632
H8S/2631
HD6432631
H8S/2633 F-ZTATTM
HD64F2633
H8S/2633R F-ZTATTM
HD64F2633R
H8S/2695
HD6432695
Hardware Manual
ADE-602-165C
Rev. 4.0
8/29/02
Hitachi, Ltd.
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi's or any third party's
patent, copyright, trademark, or other intellectual property rights for information contained in
this document. Hitachi bears no responsibility for problems that may arise with third party's
rights, including intellectual property rights, in connection with use of the information
contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you
have received the latest product standards or specifications before final design, purchase or
use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability.
However, contact Hitachi's sales office before using the product in an application that
demands especially high quality and reliability or where its failure or malfunction may directly
threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear
power, combustion control, transportation, traffic, safety equipment or medical equipment for
life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi
particularly for maximum rating, operating supply voltage range, heat radiation characteristics,
installation conditions and other characteristics. Hitachi bears no responsibility for failure or
damage when used beyond the guaranteed ranges. Even within the guaranteed ranges,
consider normally foreseeable failure rates or failure modes in semiconductor devices and
employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi
product does not cause bodily injury, fire or other consequential damage due to operation of
the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document
without written approval from Hitachi.
7. Contact Hitachi's sales office for any questions regarding this document or Hitachi
semiconductor products.
General Precautions on the Handling of Products
1. Treatment of NC Pins
Note:
Do not connect anything to the NC pins.
The NC (not connected) pins are either not connected to any of the internal circuitry; or
are used as test pins or to reduce noise. If something is connected to the NC pins, the
operation of the LSI is not guaranteed.
2. Treatment of Unused Input Pins
Note:
Fix all unused input pins to high or low level.
Generally, the input pins of CMOS products are high-impedance input pins. If unused pins
are in their open states, intermediate levels are induced by noise in the vicinity, a pass-
through current flows internally, and a malfunction may occur.
3. Processing before Initialization
Note:
When power is first supplied, the product's state is undefined. The states of internal
circuits are undefined until full power is supplied throughout the chip and a low level is
input on the reset pin. During the period where the states are undefined, the register
settings and the output state of each pin are also undefined. Design your system so that it
does not malfunction because of processing while it is in this undefined state. For those
products which have a reset function, reset the LSI immediately after the power supply has
been turned on.
4. Prohibition of Access to Undefined or Reserved Address
Note:
Access to undefined or reserved addresses is prohibited.
The undefined or reserved addresses may be used to expand functions, or test registers
may have been be allocated to these address. Do not access these registers: the system's
operation is not guaranteed if they are accessed.
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