Электронный компонент: HD64F7017

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Hitachi SuperHTM RISC engine

SH7014, SH7016,

SH7017F-ZTATTM

Hardware Manual

ADE-602-128C
Rev. 4.0
3/13/03
Hitachi, Ltd.

Cautions

1. Hitachi neither warrants nor grants licenses of any rights of Hitachi's or any third party's

patent, copyright, trademark, or other intellectual property rights for information contained in
this document. Hitachi bears no responsibility for problems that may arise with third party's
rights, including intellectual property rights, in connection with use of the information
contained in this document.

2. Products and product specifications may be subject to change without notice. Confirm that you

have received the latest product standards or specifications before final design, purchase or
use.

3. Hitachi makes every attempt to ensure that its products are of high quality and reliability.

However, contact Hitachi's sales office before using the product in an application that
demands especially high quality and reliability or where its failure or malfunction may directly
threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear
power, combustion control, transportation, traffic, safety equipment or medical equipment for
life support.

4. Design your application so that the product is used within the ranges guaranteed by Hitachi

particularly for maximum rating, operating supply voltage range, heat radiation characteristics,
installation conditions and other characteristics. Hitachi bears no responsibility for failure or
damage when used beyond the guaranteed ranges. Even within the guaranteed ranges,
consider normally foreseeable failure rates or failure modes in semiconductor devices and
employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi
product does not cause bodily injury, fire or other consequential damage due to operation of
the Hitachi product.

5. This product is not designed to be radiation resistant.

6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document

without written approval from Hitachi.

7. Contact Hitachi's sales office for any questions regarding this document or Hitachi

semiconductor products.

Preface

The SH7014/16/17 CMOS single-chip microprocessors integrate a Hitachi-original architecture,
high-speed CPU with peripheral functions required for system configuration.

The CPU has a RISC-type instruction set

.

Most instructions can be executed in one clock cycle,

which greatly improves instruction execution speed

.

In addition, the 32-bit internal-bus

architecture enhances data processing power. With this CPU, it has become possible to assemble
low cost, high performance/high-functioning systems, even for applications that were previously
impossible with microprocessors, such as real-time control, which demands high speeds. In
particular, this LSI has a 1-kbyte on-chip cache, which allows an improvement in CPU
performance during external memory access.

In addition, this LSI includes on-chip peripheral functions necessary for system configuration,
such as large-capacity ROM (except the SH7014, which is ROMless) and RAM, timers, a serial
communication interface (SCI), an A/D converter, an interrupt controller, and I/O ports. Memory
or peripheral LSIs can be connected efficiently with an external memory access support function.
This greatly reduces system cost.

This LSI has an F-ZTAT

TM

version with on-chip flash memory and a mask ROM version. These

versions enable users to respond quickly and flexibly to changing application specifications,
growing production volumes, and other conditions.

This hardware manual covers the SH7014/16/17/. For a detailed description of instructions, refer
to the programming manual.

Related Manuals
SH7014/16/17 instruction execution: SH-1/SH-2/SH-DSP Programming Manual

For information on development systems, please contact a Hitachi sales representative.

Document Outline

• Cover
• Cautions
• Preface
• Contents
• Section 1 SH7014/16/17 Overview
  • 1.1 SH7014/16/17 Overview
    • 1.1.1 SH7014/16/17 Series Features
  • 1.2 Block Diagram
  • 1.3 Pin Arrangement and Pin Functions
    • 1.3.1 Pin Arrangment
    • 1.3.2 Pin Arrangement by Mode
    • 1.3.3 Pin Functions
• Section 2 CPU
  • 2.1 Register Configuration
    • 2.1.1 General Registers (Rn)
    • 2.1.2 Control Registers
    • 2.1.3 System Registers
    • 2.1.4 Initial Values of Registers
  • 2.2 Data Formats
    • 2.2.1 Data Format in Registers
    • 2.2.2 Data Format in Memory
    • 2.2.3 Immediate Data Format
  • 2.3 Instruction Features
    • 2.3.1 RISC-Type Instruction Set
    • 2.3.2 Addressing Modes
    • 2.3.3 Instruction Format
  • 2.4 Instruction Set by Classification
  • 2.5 Processing States
    • 2.5.1 State Transitions
    • 2.5.2 Power-Down State
• Section 3 Operating Modes
  • 3.1 Operating Modes, Types, and Selection
  • 3.2 Explanation of Operating Modes
  • 3.3 Pin Configuration
• Section 4 Clock Pulse Generator (CPG)
  • 4.1 Overview
    • 4.1.1 Block Diagram
  • 4.2 Oscillator
    • 4.2.1 Connecting a Crystal Oscillator
    • 4.2.2 External Clock Input Method
    • 4.2.3 Prescaler
• Section 5 Exception Processing
  • 5.1 Overview
    • 5.1.1 Types of Exception Processing and Priority
    • 5.1.2 Exception Processing Operations
    • 5.1.3 Exception Processing Vector Table
  • 5.2 Resets
    • 5.2.1 Power-on Reset
  • 5.3 Address Errors
    • 5.3.1 Address Error Exception Processing
  • 5.4 Interrupts
    • 5.4.1 Interrupt Priority Level
    • 5.4.2 Interrupt Exception Processing
  • 5.5 Exceptions Triggered by Instructions
    • 5.5.1 Trap Instructions
    • 5.5.2 Illegal Slot Instructions
    • 5.5.3 General Illegal Instructions
  • 5.6 When Exception Sources Are Not Accepted
    • 5.6.1 Immediately after a Delayed Branch Instruction
    • 5.6.2 Immediately after an Interrupt-Disabled Instruction
  • 5.7 Stack Status after Exception Processing Ends
  • 5.8 Notes on Use
    • 5.8.1 Value of Stack Pointer (SP)
    • 5.8.2 Value of Vector Base Register (VBR)
    • 5.8.3 Address Errors Caused by Stacking of Address Error Exception Processing
• Section 6 Interrupt Controller (INTC)
  • 6.1 Overview
    • 6.1.1 Features
    • 6.1.2 Block Diagram
    • 6.1.3 Pin Configuration
    • 6.1.4 Register Configuration
  • 6.2 Interrupt Sources
    • 6.2.1 NMI Interrupts
    • 6.2.2 IRQ Interrupts
    • 6.2.3 On-Chip Peripheral Module Interrupts
    • 6.2.4 Interrupt Exception Vectors and Priority Rankings
  • 6.3 Description of Registers
    • 6.3.1 Interrupt Priority Registers A�H (IPRA�IPRH)
    • 6.3.2 Interrupt Control Register (ICR)
    • 6.3.3 IRQ Status Register (ISR)
  • 6.4 Interrupt Operation
    • 6.4.1 Interrupt Sequence
    • 6.4.2 Stack after Interrupt Exception Processing
  • 6.5 Interrupt Response Time
  • 6.6 Data Transfer with Interrupt Request Signals
    • 6.6.1 Handling DMAC Activating Sources but Not CPU Interrupt Sources
    • 6.6.2 Treating CPU Interrupt Sources but Not DMAC Activating Sources
• Section 7 Cache Memory (CAC)
  • 7.1 Overview
    • 7.1.1 Features
    • 7.1.2 Block Diagram
    • 7.1.3 Register Configuration
  • 7.2 Register Explanation
    • 7.2.1 Cache Control Register (CCR)
  • 7.3 Address Array and Data Array
    • 7.3.1 Cache Address Array Read/Write Space
    • 7.3.2 Cache Data Array Read/Write Space
  • 7.4 Cautions on Use
    • 7.4.1 Cache Initialization
    • 7.4.2 Forced Access to Address Array and Data Array
    • 7.4.3 Cache Miss Penalty and Cache Fill Timing
    • 7.4.4 Cache Hit after Cache Miss
• Section 8 Bus State Controller (BSC)
  • 8.1 Overview
    • 8.1.1 Features
    • 8.1.2 Block Diagram
    • 8.1.3 Pin Configuration
    • 8.1.4 Register Configuration
    • 8.1.5 Address Map
  • 8.2 Description of Registers
    • 8.2.1 Bus Control Register 1 (BCR1)
    • 8.2.2 Bus Control Register 2 (BCR2)
    • 8.2.3 Wait Control Register 1 (WCR1)
    • 8.2.4 Wait Control Register 2 (WCR2)
    • 8.2.5 DRAM Area Control Register (DCR)
    • 8.2.6 Refresh Timer Control/Status Register (RTCSR)
    • 8.2.7 Refresh Timer Counter (RTCNT)
    • 8.2.8 Refresh Time Constant Register (RTCOR)
  • 8.3 Accessing Ordinary Space
    • 8.3.1 Basic Timing
    • 8.3.2 Wait State Control
    • 8.3.3 CS Assert Period Extension
  • 8.4 DRAM Access
    • 8.4.1 DRAM Direct Connection
    • 8.4.2 Basic Timing
    • 8.4.3 Wait State Control
    • 8.4.4 Burst Operation
    • 8.4.5 Refresh Timing
  • 8.5 Address/Data Multiplex I/O Space Access
    • 8.5.1 Basic Timing
    • 8.5.2 Wait State Control
    • 8.5.3 CS Assertion Extension
  • 8.6 Waits between Access Cycles
    • 8.6.1 Prevention of Data Bus Conflicts
    • 8.6.2 Simplification of Bus Cycle Start Detection
  • 8.7 Bus Arbitration
  • 8.8 Memory Connection Examples
  • 8.9 On-chip Peripheral I/O Register Access
  • 8.10 CPU Operation when Program Is in External Memory
• Section 9 Direct Memory Access Controller (DMAC)
  • 9.1 Overview
    • 9.1.1 Features
    • 9.1.2 Block Diagram
    • 9.1.3 Pin Configuration
    • 9.1.4 Register Configuration
  • 9.2 Register Descriptions
    • 9.2.1 DMA Source Address Registers 0, 1 (SAR0, SAR1)
    • 9.2.2 DMA Destination Address Registers 0, 1 (DAR0, DAR1)
    • 9.2.3 DMA Transfer Count Registers 0, 1 (DMATCR0, DMATCR1)
    • 9.2.4 DMA Channel Control Registers 0, 1 (CHCR0, CHCR1)
    • 9.2.5 DMAC Operation Register (DMAOR)
  • 9.3 Operation
    • 9.3.1 DMA Transfer Flow
    • 9.3.2 DMA Transfer Requests
    • 9.3.3 Channel Priority
    • 9.3.4 DMA Transfer Types
    • 9.3.5 Address Modes
    • 9.3.6 Dual Address Mode
    • 9.3.7 Bus Modes
    • 9.3.8 Relationship between Request Modes and Bus Modes by DMA Transfer Category
    • 9.3.9 Bus Mode and Channel Priority Order
    • 9.3.10 Number of Bus Cycle States and DREQ Pin Sample Timing
    • 9.3.11 DMA Transfer Ending Conditions
    • 9.3.12 DMAC Access from CPU
  • 9.4 Examples of Use
    • 9.4.1 Example of DMA Transfer between On-Chip SCI and External Memory
    • 9.4.2 Example of DMA Transfer between External RAM and External Device with DACK
  • 9.5 Cautions on Use
• Section 10 Multifunction Timer Pulse Unit (MTU)
  • 10.1 Overview
    • 10.1.1 Features
    • 10.1.2 Block Diagram
    • 10.1.3 Pin Configuration
    • 10.1.4 Register Configuration
  • 10.2 MTU Register Descriptions
    • 10.2.1 Timer Control Register (TCR)
    • 10.2.2 Timer Mode Register (TMDR)
    • 10.2.3 Timer I/O Control Register (TIOR)
    • 10.2.4 Timer Interrupt Enable Register (TIER)
    • 10.2.5 Timer Status Register (TSR)
    • 10.2.6 Timer Counters (TCNT)
    • 10.2.7 Timer General Register (TGR)
    • 10.2.8 Timer Start Register (TSTR)
    • 10.2.9 Timer Synchro Register (TSYR)
  • 10.3 Bus Master Interface
    • 10.3.1 16-Bit Registers
    • 10.3.2 8-Bit Registers
  • 10.4 Operation
    • 10.4.1 Overview
    • 10.4.2 Basic Functions
    • 10.4.3 Synchronous Operation
    • 10.4.4 Buffer Operation
    • 10.4.5 Cascade Connection Mode
    • 10.4.6 PWM Mode
    • 10.4.7 Phase Counting Mode
  • 10.5 Interrupts
    • 10.5.1 Interrupt Sources and Priority Ranking
    • 10.5.2 DMAC Activation
    • 10.5.3 A/D Converter Activation
  • 10.6 Operation Timing
    • 10.6.1 Input/Output Timing
    • 10.6.2 Interrupt Signal Timing
  • 10.7 Notes and Precautions
    • 10.7.1 Input Clock Limitations
    • 10.7.2 Note on Cycle Setting
    • 10.7.3 Contention between TCNT Write and Clear
    • 10.7.4 Contention between TCNT Write and Increment
    • 10.7.5 Contention between Buffer Register Write and Compare Match
    • 10.7.6 Contention between TGR Read and Input Capture
    • 10.7.7 Contention between TGR Write and Input Capture
    • 10.7.8 Contention between Buffer Register Write and Input Capture
    • 10.7.9 Contention between TGR Write and Compare Match
    • 10.7.10 TCNT2 Write and Overflow/Underflow Contention in Cascade Connection
    • 10.7.11 Contention between Overflow/Underflow and Counter Clearing
    • 10.7.12 Contention between TCNT Write and Overflow/Underflow
    • 10.7.13 Cautions on Carrying Out Buffer Operation of Channel 0 in PWM Mode
  • 10.8 MTU Output Pin Initialization
    • 10.8.1 Operating Modes
    • 10.8.2 Reset Start Operation
    • 10.8.3 Operation in Case of Re-Setting Due to Error during Operation, Etc.
    • 10.8.4 Overview of Initialization Procedures and Mode Transitions in Case of Error during Operation, etc.
• Section 11 Watchdog Timer (WDT)
  • 11.1 Overview
    • 11.1.1 Features
    • 11.1.2 Block Diagram
    • 11.1.3 Pin Configuration
    • 11.1.4 Register Configuration
  • 11.2 Register Descriptions
    • 11.2.1 Timer Counter (TCNT)
    • 11.2.2 Timer Control/Status Register (TCSR)
    • 11.2.3 Reset Control/Status Register (RSTCSR)
    • 11.2.4 Register Access
  • 11.3 Operation
    • 11.3.1 Watchdog Timer Mode
    • 11.3.2 Interval Timer Mode
    • 11.3.3 Clearing the Standby Mode
    • 11.3.4 Timing of Setting the Overflow Flag (OVF)
    • 11.3.5 Timing of Setting the Watchdog Timer Overflow Flag (WOVF)
  • 11.4 Notes on Use
    • 11.4.1 TCNT Write and Increment Contention
    • 11.4.2 Changing CKS2 to CKS0 Bit Values
    • 11.4.3 Changing between Watchdog Timer/Interval Timer Modes
    • 11.4.4 System Reset with WDTOVF
    • 11.4.5 Internal Reset with the Watchdog Timer
• Section 12 Serial Communication Interface (SCI)
  • 12.1 Overview
    • 12.1.1 Features
    • 12.1.2 Block Diagram
    • 12.1.3 Pin Configuration
    • 12.1.4 Register Configuration
  • 12.2 Register Descriptions
    • 12.2.1 Receive Shift Register (RSR)
    • 12.2.2 Receive Data Register (RDR)
    • 12.2.3 Transmit Shift Register (TSR)
    • 12.2.4 Transmit Data Register (TDR)
    • 12.2.5 Serial Mode Register (SMR)
    • 12.2.6 Serial Control Register (SCR)
    • 12.2.7 Serial Status Register (SSR)
    • 12.2.8 Bit Rate Register (BRR)
  • 12.3 Operation
    • 12.3.1 Overview
    • 12.3.2 Operation in Asynchronous Mode
    • 12.3.3 Multiprocessor Communication
    • 12.3.4 Clock Synchronous Operation
  • 12.4 SCI Interrupt Sources and the DMAC
  • 12.5 Notes on Use
    • 12.5.1 TDR Write and TDRE Flags
    • 12.5.2 Simultaneous Multiple Receive Errors
    • 12.5.3 Break Detection and Processing
    • 12.5.4 Sending a Break Signal
    • 12.5.5 Receive Error Flags and Transmitter Operation (Clock Synchronous Mode Only)
    • 12.5.6 Receive Data Sampling Timing and Receive Margin in the Asynchronous Mode
    • 12.5.7 Constraints on DMAC Use
    • 12.5.8 Cautions for Clock Synchronous External Clock Mode
    • 12.5.9 Caution for Clock Synchronous Internal Clock Mode
• Section 13 High Speed A/D Converter -SH7014-
  • 13.1 Overview
    • 13.1.1 Features
    • 13.1.2 Block Diagram
    • 13.1.3 Pin Configuration
    • 13.1.4 Register Configuration
  • 13.2 Register Descriptions
    • 13.2.1 A/D Data Registers A�H (ADDRA�ADDRH)
    • 13.2.2 A/D Control/Status Register (ADCSR)
    • 13.2.3 A/D Control Register (ADCR)
  • 13.3 Bus Master Interface
  • 13.4 Operation
    • 13.4.1 Select-Single Mode
    • 13.4.2 Select-Scan Mode
    • 13.4.3 Group-Single Mode
    • 13.4.4 Group-Scan Mode
    • 13.4.5 Buffer Operation
    • 13.4.6 Simultaneous Sampling Operation
    • 13.4.7 Conversion Start Modes
    • 13.4.8 A/D Conversion Time
  • 13.5 Interrupts
  • 13.6 Notes on Use
    • 13.6.1 Analog Input Voltage Range
    • 13.6.2 AVCC , AVSS Input Voltages
    • 13.6.3 Input Ports
    • 13.6.4 Conversion Start Modes
    • 13.6.5 A/D Conversion Termination
    • 13.6.6 Handling of Analog Input Pins
• Section 14 Mid-Speed A/D Converter -SH7016, SH7017-
  • 14.1 Overview
    • 14.1.1 Features
    • 14.1.2 Block Diagram
    • 14.1.3 Pin Configuration
    • 14.1.4 Register Configuration
  • 14.2 Register Descriptions
    • 14.2.1 A/D Data Register A to D (ADDRA to ADDRD)
    • 14.2.2 A/D Control/Status Register (ADCSR)
    • 14.2.3 A/D Control Register (ADCR)
  • 14.3 Interface with CPU
  • 14.4 Operation
    • 14.4.1 Single Mode (SCAN=0)
    • 14.4.2 Scan Mode (SCAN=1)
    • 14.4.3 Input Sampling and A/D Conversion Time
    • 14.4.4 MTU Trigger Input Timing
  • 14.5 Interrupt
  • 14.6 A/D Conversion Precision Definitions
  • 14.7 Usage Notes
    • 14.7.1 Analog Voltage Settings
    • 14.7.2 Handling of Analog Input Pins
• Section 15 Compare Match Timer (CMT)
  • 15.1 Overview
    • 15.1.1 Features
    • 15.1.2 Block Diagram
    • 15.1.3 Register Configuration
  • 15.2 Register Descriptions
    • 15.2.1 Compare Match Timer Start Register (CMSTR)
    • 15.2.2 Compare Match Timer Control/Status Register (CMCSR)
    • 15.2.3 Compare Match Timer Counter (CMCNT)
    • 15.2.4 Compare Match Timer Constant Register (CMCOR)
  • 15.3 Operation
    • 15.3.1 Period Count Operation
    • 15.3.2 CMCNT Count Timing
  • 15.4 Interrupts
    • 15.4.1 Interrupt Sources and DTC Activation
    • 15.4.2 Compare Match Flag Set Timing
    • 15.4.3 Compare Match Flag Clear Timing
  • 15.5 Notes on Use
    • 15.5.1 Contention between CMCNT Write and Compare Match
    • 15.5.2 Contention between CMCNT Word Write and Incrementation
    • 15.5.3 Contention between CMCNT Byte Write and Incrementation
• Section 16 Pin Function Controller
  • 16.1 Overview
  • 16.2 Register Configuration
  • 16.3 Register Descriptions
    • 16.3.1 Port A I/O Register L (PAIORL)
    • 16.3.2 Port A Control Registers L1, L2 (PACRL1 and PACRL2)
    • 16.3.3 Port B I/O Register (PBIOR)
    • 16.3.4 Port B Control Registers (PBCR1 and PBCR2)
    • 16.3.5 Port C I/O Register (PCIOR) �SH7016, SH7017�
    • 16.3.6 Port C Control Register (PCCR) �SH7016, SH7017�
    • 16.3.7 Port D I/O Register L (PDIORL) �SH7016, SH7017�
    • 16.3.8 Port D Control Register L (PDCRL) �SH7016, SH7017�
    • 16.3.9 Port E I/O Register (PEIOR)
    • 16.3.10 Port E Control Registers 1, 2 (PECR1 and PECR2)
• Section 17 I/O Ports (I/O)
  • 17.1 Overview
  • 17.2 Port A
    • 17.2.1 Register Configuration
    • 17.2.2 Port A Data Register L (PADRL)
  • 17.3 Port B
    • 17.3.1 Register Configuration
    • 17.3.2 Port B Data Register (PBDR)
  • 17.4 Port C �SH7016, SH7017�
    • 17.4.1 Register Configuration
    • 17.4.2 Port C Data Register (PCDR)
  • 17.5 Port D �SH7016, SH7017�
    • 17.5.1 Register Configuration
    • 17.5.2 Port D Data Register L (PDDRL)
  • 17.6 Port E
    • 17.6.1 Register Configuration
    • 17.6.2 Port E Data Register (PEDR)
  • 17.7 Port F
    • 17.7.1 Register Configuration
    • 17.7.2 Port F Data Register (PFDR)
• Section 18 128 kB Flash Memory (F-ZTAT)
  • 18.1 Features
  • 18.2 Overview
    • 18.2.1 Block Diagram
    • 18.2.2 Mode Transitions
    • 18.2.3 On-Board Programming Modes
    • 18.2.4 Flash Memory Emulation in RAM
    • 18.2.5 Differences between Boot Mode and User Program Mode
    • 18.2.6 Block Configuration
  • 18.3 Pin Configuration
  • 18.4 Register Configuration
  • 18.5 Register Descriptions
    • 18.5.1 Flash Memory Control Register 1 (FLMCR1)
    • 18.5.2 Flash Memory Control Register 2 (FLMCR2)
    • 18.5.3 Erase Block Register 1 (EBR1)
    • 18.5.4 RAM Emulation Register (RAMER)
  • 18.6 On-Board Programming Modes
    • 18.6.1 Boot Mode
    • 18.6.2 User Program Mode
  • 18.7 Programming/Erasing Flash Memory
    • 18.7.1 Program Mode
    • 18.7.2 Program-Verify Mode
    • 18.7.3 Erase Mode
    • 18.7.4 Erase-Verify Mode
  • 18.8 Protection
    • 18.8.1 Hardware Protection
    • 18.8.2 Software Protection
    • 18.8.3 Error Protection
  • 18.9 Flash Memory Emulation in RAM
  • 18.10 Note on Flash Memory Programming/Erasing
  • 18.11 Flash Memory Programmer Mode
    • 18.11.1 Socket Adapter Pin Correspondence Diagram
    • 18.11.2 Programmer Mode Operation
    • 18.11.3 Memory Read Mode
    • 18.11.4 Auto-Program Mode
    • 18.11.5 Auto-Erase Mode
    • 18.11.6 Status Read Mode
    • 18.11.7 Status Polling
    • 18.11.8 Programmer Mode Transition Time
    • 18.11.9 Notes on Memory Programming
• Section 19 Mask ROM
  • 19.1 Overview
• Section 20 RAM
  • 20.1 Overview
• Section 21 Power-Down State
  • 21.1 Overview
    • 21.1.1 Power-Down States
    • 21.1.2 Related Register
  • 21.2 Standby Control Register (SBYCR)
  • 21.3 Sleep Mode
    • 21.3.1 Transition to Sleep Mode
    • 21.3.2 Canceling Sleep Mode
  • 21.4 Standby Mode
    • 21.4.1 Transition to Standby Mode
    • 21.4.2 Canceling the Standby Mode
    • 21.4.3 Standby Mode Application Example
• Section 22 Electrical Characteristics (5 V 28.7 MHz)
  • 22.1 Absolute Maximum Ratings
  • 22.2 DC Characteristics
  • 22.3 AC Characteristics
    • 22.3.1 Clock Timing
    • 22.3.2 Control Signal Timing
    • 22.3.3 Bus Timing
    • 22.3.4 Direct Memory Access Controller Timing
    • 22.3.5 Multifunction Timer Pulse Unit Timing
    • 22.3.6 I/O Port Timing
    • 22.3.7 Watchdog Timer Timing
    • 22.3.8 Serial Communication Interface Timing
    • 22.3.9 High Speed A/D Converter Timing � SH7014�
    • 22.3.10 Mid-speed Converter Timing �SH7016, SH7017�
    • 22.3.11 Measuring Conditions for AC Characteristics
  • 22.4 A/D Converter Characteristics
• Appendix A On-Chip Supporting Module Registers
  • A.1 Addresses
• Appendix B I/O Port Block Diagrams
• Appendix C Pin States
• Appendix D Notes when Converting the F-ZTAT Application Software to the Mask-ROM Versions
• Appendix E Product Code Lineup
• Appendix F Package Dimensions
• Colophon