DESCRIPTION
The 4518 Group is a 4-bit single-chip microcomputer designed with
CMOS technology. Its CPU is that of the 4500 series using a
simple, high-speed instruction set. The computer is equipped with
serial I/O, four 8-bit timers (each timer has one or two reload regis-
ter), a 10-bit A-D converter, interrupts, and oscillation circuit switch
function.
The various microcomputers in the 4518 Group include variations
of the built-in memory size as shown in the table below.
FEATURES
q
Minimum instruction execution time .................................. 0.5
s
(at 6 MHz oscillation frequency, in X
IN
through-mode)
q
Supply voltage
Mask ROM version ...................................................... 1.8 to 5.5 V
One Time PROM version ............................................. 2.5 to 5.5 V
(It depends on operation source clock, oscillation frequency and op-
eration mode)
q
Timers
Timer 1 ...................................... 8-bit timer with a reload register
Timer 2 ...................................... 8-bit timer with a reload register
Timer 3 ...................................... 8-bit timer with a reload register
Timer 3 ................................. 8-bit timer with two reload registers
Product
M34518M2-XXXFP
M34518M2-XXXSP
M34518M4-XXXFP
M34518M4-XXXSP
M34518M6-XXXFP
M34518M8-XXXFP
M34518E8FP (Note)
M34518E8SP (Note)
ROM type
Mask ROM
Mask ROM
Mask ROM
Mask ROM
Mask ROM
Mask ROM
One Time PROM
One Time PROM
Package
32P6U-A
32P4B
32P6U-A
32P4B
32P6U-A
32P6U-A
32P6U-A
32P4B
RAM size
(
4 bits)
256 words
256 words
256 words
256 words
384 words
384 words
384 words
384 words
ROM (PROM) size
(
10 bits)
2048 words
2048 words
4096 words
4096 words
6144 words
8192 words
8192 words
8192 words
q
Interrupt ........................................................................ 8 sources
q
Key-on wakeup function pins ................................................... 10
q
Serial I/O ....................................................................... 8 bits
1
q
A-D converter ...... 10-bit successive approximation method, 4ch
q
Voltage drop detection circuit
Reset occurrence .................................... Typ. 3.5 V (Ta = 25 C)
Reset release .......................................... Typ. 3.7 V (Ta = 25 C)
q
Watchdog timer
q
Clock generating circuit
(ceramic resonator/RC oscillation/quartz-crystal oscillation/inter-
nal ring oscillator)
q
LED drive directly enabled (port D)
APPLICATION
Electrical household appliance, consumer electronic products, of-
fice automation equipment, etc.
Note: Shipped in blank.
Rev.2.00 2003.04.15 page 1 of 156
4518 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
REJ03B0008-0200Z
Rev.2.00
2003.04.15
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Rev.2.00 2003.04.15 page 2 of 156
4518 Group
PIN CONFIGURATION
Pin configuration (top view) (4518 Group)
OUTLINE 32P6U-A
2
1
3
4
5
6
7
8
23
24
22
21
20
19
18
17
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
D
3
D
4
D
5
D
6
/CNTR0
D
7
/CNTR1
P2
0
/S
CK
P2
1
/S
OUT
P2
2
/S
IN
P0
2
P0
1
P0
0
P6
3
/A
IN3
P6
2
/A
IN2
P6
1
/A
IN1
P6
0
/A
IN0
P3
1
/INT1
P3
0
/INT0
VDCE
V
DD
V
SS
X
IN
X
OUT
CNV
SS
RESET
P0
3
P1
0
P1
1
P1
2
P1
3
D
0
D
1
D
2
M34518Mx-XXXFP
M34518E8FP
8
7
10
9
12
11
14
15
16
13
6
5
4
3
2
M34518Mx-XXXSP
M34518E8SP
1
25
26
23
24
21
22
19
18
17
20
27
28
29
30
31
32
D
0
D
1
D
2
D
3
D
4
D
5
D
6
/CNTR0
D
7
/CNTR1
P2
0
/S
CK
P2
1
/S
OUT
P2
2
/S
IN
RESET
CNV
SS
X
OUT
X
IN
V
SS
P1
3
P1
2
P1
1
P1
0
P0
3
P0
2
P0
1
P0
0
P6
3
/A
IN3
P6
2
/A
IN2
P6
1
/A
IN1
P6
0
/A
IN0
P3
1
/INT1
P3
0
/INT0
VDCE
V
DD
Pin configuration (top view) (4518 Group)
OUTLINE 32P4B
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Rev.2.00 2003.04.15 page 3 of 156
4518 Group
Block diagram (4518 Group)
4
4
3
2
4
8
R
A
M
R
O
M
M
e
m
o
r
y
I
/
O
p
o
r
t
I
n
t
e
r
n
a
l
p
e
r
i
p
h
e
r
a
l
f
u
n
c
t
i
o
n
s
T
i
m
e
r
T
i
m
e
r
1
(
8
b
i
t
s
)
S
y
s
t
e
m
c
l
o
c
k
g
e
n
e
r
a
t
i
o
n
c
i
r
c
u
i
t
T
i
m
e
r
2
(
8
b
i
t
s
)
2
5
6
,
3
8
4
w
o
r
d
s
4
b
i
t
s
2
0
4
8
,
4
0
9
6
,
6
1
4
4
,
8
1
9
2
w
o
r
d
s
1
0
b
i
t
s
4
5
0
0
s
e
r
i
e
s
C
P
U
c
o
r
e
R
e
g
i
s
t
e
r
B
(
4
b
i
t
s
)
R
e
g
i
s
t
e
r
A
(
4
b
i
t
s
)
R
e
g
i
s
t
e
r
D
(
3
b
i
t
s
)
R
e
g
i
s
t
e
r
E
(
8
b
i
t
s
)
S
t
a
c
k
r
e
g
i
s
t
e
r
S
K
(
8
l
e
v
e
l
s
)
I
n
t
e
r
r
u
p
t
s
t
a
c
k
r
e
g
i
s
t
e
r
S
D
P
(
1
l
e
v
e
l
)
A
L
U
(
4
b
i
t
s
)
W
a
t
c
h
d
o
g
t
i
m
e
r
(
1
6
b
i
t
s
)
P
o
r
t
P
0
P
o
r
t
P
1
P
o
r
t
P
2
V
o
l
t
a
g
e
d
r
o
p
d
e
t
e
c
t
i
o
n
c
i
r
c
u
i
t
T
i
m
e
r
3
(
8
b
i
t
s
)
T
i
m
e
r
4
(
8
b
i
t
s
)
X
I
N
-
X
O
U
T
(
C
e
r
a
m
i
c
/
Q
u
a
r
t
z
-
c
r
y
s
t
a
l
/
R
C
)
B
u
i
l
t
-
i
n
r
i
n
g
o
s
c
i
l
l
a
t
o
r
P
o
r
t
P
3
P
o
r
t
D
P
o
r
t
P
6
S
e
r
i
a
l
I
/
O
(
8
b
i
t
s
1
)
A
-
D
c
o
n
v
e
r
t
e
r
(
1
0
b
i
t
s
4
c
h
)
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Rev.2.00 2003.04.15 page 4 of 156
4518 Group
PERFORMANCE OVERVIEW
Function
148
0.5
s (at 6.0 MHz oscillation frequency, in X
IN
through-mode)
2048 words
10 bits
4096 words
10 bits
6144 words
10 bits
8192 words
10 bits
256 words
4 bits
384 words
4 bits
Eight independent I/O ports;
Ports D
6
and D
7
are also used as CNTR0 and CNTR1, respectively.
The output structure is switched by software.
4-bit I/O port; a pull-up function, a key-on wakeup function and output structure can be switched
by software.
4-bit I/O port; a pull-up function, a key-on wakeup function and output structure can be switched
by software.
3-bit I/O port; ports P2
0
, P2
1
and P2
2
are also used as S
CK
, S
OUT
and S
IN
, respectively.
2-bit I/O port ; ports P3
0
and P3
1
are also used as INT0 and INT1, respectively.
4-bit I/O port ; ports P6
0
P6
3
are also used as A
IN0
A
IN3
, respectively.
8-bit timer with a reload register is also used as an event counter.
Also, this is equipped with a period/pulse width measurement function.
8-bit timer with a reload register.
8-bit timer with a reload register is also used as an event counter.
8-bit timer with two reload registers and PWM output function.
10-bit wide
4 ch, This is equipped with an 8-bit comparator function.
8-bit
1
8 (two for external, four for timer, one for A-D, and one for serial I/O)
1 level
8 levels
CMOS silicon gate
32-pin plastic molded LQFP (32P6U-A)/SDIP (32P4B)
20 C to 85 C
1.8 V to 5.5 V (It depends on operation source clock, oscillation frequency and operating mode.)
2.5 V to 5.5 V (It depends on operation source clock, oscillation frequency and operating mode.)
2.8 mA (V
DD
=5V, f(X
IN
)=6 MHz, f(STCK)=f(X
IN
), ring oscillator stop)
70
A (V
DD
=5V, f(X
IN
)=32 kHz, f(STCK)=f(X
IN
), ring oscillator stop)
150
A (V
DD
=5V, ring oscillator is used, f(STCK)=f(RING), f(X
IN
) stop)
0.1
A (at room temperature, V
DD
= 5 V, output transistors in the cut-off state)
Parameter
Number of basic instructions
Minimum instruction execution time
Memory sizes
Input/Output
ports
Timers
A-D converter
Serial I/O
Interrupt
Subroutine nesting
Device structure
Package
Operating temperature range
Supply voltage
Power
dissipation
(typical value)
ROM
RAM
D
0
D
7
P0
0
P0
3
P1
0
P1
3
P2
0
P2
2
P3
0
, P3
1
P6
0
P6
3
Timer 1
Timer 2
Timer 3
Timer 4
Sources
Nesting
Mask ROM version
One Time PROM version
Active mode
RAM back-up mode
I/O (Input is
examined by
skip decision)
I/O
I/O
I/O
I/O
I/O
M34518M2
M34518M4
M34518M6
M34518M8/E8
M34518M2/M4
M34518M6/M8/E8
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Rev.2.00 2003.04.15 page 5 of 156
4518 Group
PIN DESCRIPTION
Name
Power supply
Ground
CNV
SS
Voltage drop
detection circuit
enable
Reset input/output
Main clock input
Pin
V
DD
V
SS
CNV
SS
VDCE
RESET
X
IN
Input/Output
--
--
--
Input
I/O
Input
Function
Connected to a plus power supply.
Connected to a 0 V power supply.
Connect CNV
SS
to V
SS
and apply "L" (0V) to CNV
SS
certainly.
This pin is used to operate/stop the voltage drop detection circuit. When "H" level is
input to this pin, the circuit starts operating. When "L" level is input to this pin, the
circuit stops operating.
An N-channel open-drain I/O pin for a system reset. When the SRST instruction,
watchdog timer or the voltage drop detection circuit cause the system to be reset,
the
RESET
pin outputs "L" level.
I/O pins of the main clock generating circuit. When using a ceramic resonator, connect
it between pins X
IN
and X
OUT
. When using a 32 kHz quartz-crystal oscillator, connect it
between pins X
IN
and X
OUT
. A feedback resistor is built-in between them. When using
the RC oscillation, connect a resistor and a capacitor to X
IN
, and leave X
OUT
pin open.
X
OUT
Main clock output
Output
D
0
D
7
P0
0
P0
3
P1
0
P1
3
P2
0
P2
3
P3
0
P3
3
P6
0
P6
3
CNTR0,
CNTR1
INT0, INT1
A
IN0
A
IN3
S
CK
S
OUT
S
IN
I/O port D
Input is examined by
skip decision.
I/O port P0
I/O port P1
I/O port P2
I/O port P3
I/O port P6
Timer input/output
Interrupt input
Analog input
Serial I/O data I/O
Serial I/O data output
Serial I/O clock input
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Input
Input
I/O
Output
Input
Each pin of port D has an independent 1-bit wide I/O function. The output structure
can be switched to N-channel open-drain or CMOS by software. For input use, set
the latch of the specified bit to "1" and select the N-channel open-drain. Ports D
6
, D
7
is also used as CNTR0 pin and CNTR1 pin, respectively.
Port P0 serves as a 4-bit I/O port. The output structure can be switched to N-channel
open-drain or CMOS by software. For input use, set the latch of the specified bit to
"1" and select the N-channel open-drain. Port P0 has a key-on wakeup function and
a pull-up function. Both functions can be switched by software.
Port P1 serves as a 4-bit I/O port. The output structure can be switched to N-channel
open-drain or CMOS by software. For input use, set the latch of the specified bit to
"1" and select the N-channel open-drain. Port P1 has a key-on wakeup function and
a pull-up function. Both functions can be switched by software.
Port P2 serves as a 3-bit I/O port. The output structure is N-channel open-drain. For
input use, set the latch of the specified bit to "1".
Ports P2
0
P2
2
are also used as S
CK
, S
OUT
, S
IN
, respectively.
Port P3 serves as a 2-bit I/O port. The output structure is N-channel open-drain. For
input use, set the latch of the specified bit to "1".
Ports P3
0
and P3
1
are also used as INT0 pin and INT1 pin, respectively.
Port P6 serves as a 4-bit I/O port. The output structure can be switched to N-channel
open-drain. For input use, set the latch of the specified bit to "1". Ports P6
0
P6
3
are
also used as A
IN0
A
IN3
, respectively.
CNTR0 pin has the function to input the clock for the timer 1 event counter, and to
output the timer 1 or timer 2 underflow signal divided by 2.
CNTR1 pin has the function to input the clock for the timer 3 event counter, and to
output the PWM signal generated by timer 4.CNTR0 pin and CNTR1 pin are also
used as Ports D
6
and D
7
, respectively.
INT0 pin and INT1 pin accept external interrupts. They have the key-on wakeup func-
tion which can be switched by software. INT0 pin and INT1 pin are also used as
Ports P3
0
and P3
1
, respectively.
A-D converter analog input pins. A
IN0
A
IN3
are also used as ports P6
0
P6
3
, respec-
tively.
Serial I/O data transfer synchronous clock I/O pin. S
CK
pin is also used as port P2
0.
.
Serial I/O data output pin. S
OUT
pin is also used as port P2
1
.
Serial I/O data input pin. S
IN
pin is also used as port P2
2
.
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