Rev.0.01, Jan.11.2005, page 1 of 14
R1LV0416CBG-I Series
Wide Temperature Range Version
4M SRAM (256-kword
16-bit)
REJ03C0259-0001
Preliminary
Rev.0.01
Jan.11.2005
Description
The R1LV0416CBG-I is a 4-Mbit static RAM organized 256-kword
16-bit. The R1LV0416C-I Series has realized
higher density, higher performance and low power consumption by employing CMOS process technology (6-transistor
memory cell). The R1LV0416CBG-I Series offers low power standby power dissipation; therefore, it is suitable for
battery backup systems. It has packaged in 48-pin CSP (0.75 mm ball pitch).
Features
Single 2.5 V and 3.0 V supply: 2.2 V to 3.6 V
Fast access time: 55/70 ns (max)
Power dissipation:
Active: 5.0 mW/MHz (typ)(V
CC
= 2.5 V)
: 6.0 mW/MHz (typ) (V
CC
= 3.0 V)
Standby: 1.25 W (typ) (V
CC
= 2.5 V)
: 1.5
W (typ) (V
CC
= 3.0 V)
Completely static memory.
No clock or timing strobe required
Access and cycle times are equal.
Common data input and output.
Three state output
Battery backup operation.
2 chip selection for battery backup
Temperature range: -40 to +85C
Ordering Information
Type No.
Access time
Package
R1LV0416CBG-5SI
55 ns
48-ball CSP with 0.75 mm ball pitch (48FHH)
R1LV0416CBG-7LI 70
ns
Preliminary: The specifications of this device are subject to change without notice. Please contact your nearest
Renesas Technology's Sales Dept. regarding specifications.
R1LV0416CBG-I Series
Rev.0.01, Jan.11.2005, page 2 of 14
Pin Arrangement
(Top view)
48-ball CSP
A
B
C
D
E
F
G
H
1 2 3 4 5 6
LB#
I/O8
I/O9
VSS
VCC
I/O14
I/O15
NC
OE#
UB#
I/O10
I/O11
I/O12
I/O13
NC
A8
A3
A5
A17
NC
A14
A0
A12
A9
A1
A4
A6
A7
A16
A15
A13
A10
A2
CS1#
I/O1
I/O3
I/O4
I/O5
WE#
A11
CS2
I/O0
I/O2
VCC
VSS
I/O6
I/O7
NC
Pin Description
Pin name
Function
A0 to A17
Address input
I/O0 to I/O15
Data input/output
CS1# (
CS1
)
Chip select 1
CS2
Chip select 2
WE# (
WE
) Write
enable
OE# (
OE
) Output
enable
LB# (
LB
)
Lower byte select
UB# (
UB
)
Upper byte select
V
CC
Power
supply
V
SS
Ground
NC No
connection
R1LV0416CBG-I Series
Rev.0.01, Jan.11.2005, page 3 of 14
Block Diagram
I/O0
I/O15
CS2
WE#
OE#
A4 A3 A2
A5
A0
V
V
CC
SS
Row
decoder
Memory matrix
2,048 x 2,048
Column I/O
Column decoder
Input
data
control
Control logic
A6
A12
A11
A10
A9
A8
A13
A14
A15
A16
A17
A7
CS1#
LB#
UB#
A1
LSB
MSB
LSB
MSB
R1LV0416CBG-I Series
Rev.0.01, Jan.11.2005, page 4 of 14
Operation Table
CS1#
CS2
WE#
OE#
UB#
LB#
I/O0 to I/O7
I/O8 to I/O15
Operation
H
High-Z
High-Z
Standby
L
High-Z
High-Z
Standby
H H
High-Z
High-Z
Standby
L H H L L
L
Dout Dout
Read
L H H L H L
Dout
High-Z
Lower
byte
read
L H H L L H
High-Z
Dout
Upper
byte
read
L H L
L L
Din
Din
Write
L H L
H
L
Din
High-Z
Lower byte write
L H L
L
H
High-Z
Din
Upper byte write
L H H H
High-Z
High-Z
Output
disable
Note: H: V
IH
, L: V
IL
,
: V
IH
or V
IL
Absolute Maximum Ratings
Parameter Symbol
Value
Unit
Power supply voltage relative to V
SS
V
CC
-
0.5 to +4.6
V
Terminal voltage on any pin relative to V
SS
V
T
-
0.5
*
1
to V
CC
+ 0.3
*
2
V
Power dissipation
P
T
0.7
W
Operating temperature
Topr
-
40 to +85
C
Storage temperature range
Tstg
-
65 to +150
C
Storage temperature range under bias
Tbias
-
40 to +85
C
Notes: 1. V
T
min:
-
3.0 V for pulse half-width
30 ns.
2. Maximum voltage is +4.6 V.
DC Operating Conditions
(Ta =
-40 to +85C)
Parameter Symbol
Min
Typ
Max
Unit
Note
Supply voltage
V
CC
2.2
2.5/3.0
3.6 V
V
SS
0 0 0 V
Input high voltage
V
CC
= 2.2 V to 2.7 V
V
IH
2.0
V
CC
+ 0.3
V
V
CC
= 2.7 V to 3.6 V
V
IH
2.2
V
CC
+ 0.3
V
Input low voltage
V
CC
= 2.2 V to 2.7 V
V
IL
-
0.2
0.4 V 1
V
CC
= 2.7 V to 3.6 V
V
IL
-
0.3
0.6 V 1
Note: 1. V
IL
min:
-
3.0 V for pulse half-width
30 ns.
R1LV0416CBG-I Series
Rev.0.01, Jan.11.2005, page 5 of 14
DC Characteristics
Parameter Symbol
Min
Typ
Max Unit
Test
conditions
Input leakage current
|I
LI
|
1
A Vin = V
SS
to V
CC
Output leakage current
|I
LO
|
1
A CS1# = V
IH
or CS2 = V
IL
or
OE# = V
IH
or WE# = V
IL
or
LB# = UB# = V
IH
,
V
I/O
= V
SS
to V
CC
Operating current
I
CC
5
*
1
20
mA CS1# = V
IL
, CS2 = V
IH
,
Others = V
IH
/V
IL
, I
I/O
= 0 mA
Average operating current
I
CC1
8
*
1
25
mA Min. cycle, duty = 100%,
I
I/O
= 0 mA, CS1# = V
IL
,
CS2 = V
IH
,
Others = V
IH
/V
IL
I
CC2
2
*
1
5
mA Cycle time = 1
s,
duty = 100%,
I
I/O
= 0 mA, CS1#
0.2 V,
CS2
V
CC
-
0.2 V
V
IH
V
CC
-
0.2 V, V
IL
0.2 V
Standby current
I
SB
0.1
*
1
0.3
mA CS2 = V
IL
to +85
C I
SB1
10
A Vin
0 V
to +70
C I
SB1
8
A (1) 0 V
CS2
0.2 V or
to +40
C
I
SB1
0.7
*
2
3
A (2)
CS1#
V
CC
-
0.2 V,
-
5SI
to +25
C I
SB1
0.5
*
1
2.5
A CS2
V
CC
-
0.2 V or
to +85
C I
SB1
20
A (3) LB# = UB#
V
CC
-
0.2 V,
to +70
C I
SB1
16
A CS2
V
CC
-
0.2 V,
to +40
C
I
SB1
0.7
*
2
10
A CS1#
0.2 V
Standby current
-
7LI
to +25
C I
SB1
0.5
*
1
10
A
Output high voltage V
CC
=2.2 V to 2.7 V
V
OH
2.0 --
--
V I
OH
=
-
0.5 mA
V
CC
=2.7 V to 3.6 V
V
OH
2.4 --
--
V I
OH
=
-
1 mA
V
CC
=2.2 V to 3.6 V
V
OH2
V
CC
-
0.2
--
--
V I
OH
=
-
100
A
Output low voltage
V
CC
=2.2 V to 2.7 V
V
OL
-- --
0.4
V I
OL
= 0.5 mA
V
CC
=2.7 V to 3.6 V
V
OL
--
--
0.4 V I
OL
= 2 mA
V
CC
=2.2 V to 3.6 V
V
OL2
--
--
0.2 V I
OL
= 100
A
Notes: 1. Typical values are at V
CC
= 3.0 V, Ta = +25
C and specified loading, and not guaranteed.
2. Typical values are at V
CC
= 3.0 V, Ta = +40
C and specified loading, and not guaranteed.
Capacitance
(Ta = +25
C, f = 1.0 MHz)
Parameter Symbol
Min
Typ
Max
Unit
Test
conditions
Note
Input capacitance
Cin
8
pF
Vin = 0 V
1
Input/output capacitance
C
I/O
10 pF
V
I/O
= 0 V
1
Note: 1. This parameter is sampled and not 100% tested.
R1LV0416CBG-I Series
Rev.0.01, Jan.11.2005, page 6 of 14
AC Characteristics
(Ta =
-40 to +85C, V
CC
= 2.2 V to 3.6 V, unless otherwise noted.)
Test Conditions
Input pulse levels: V
IL
= 0.4 V, V
IH
= 2.2 V (V
CC
= 2.2 V to 2.7 V)
:
V
IL
= 0.4 V, V
IH
= 2.4 V (V
CC
= 2.7 V to 3.6 V)
Input rise and fall time: 5 ns
Input/output timing reference levels: 1.1 V (V
CC
= 2.2 V to 2.7 V)
: 1.4 V (V
CC
= 2.7 V to 3.6 V)
Output load: See figures (Including scope and jig)
Dout
30pF
R1
V
TM
V
TM
= 2.3 V
R2
R1 = 3070
R2 = 3150
50pF
Dout
RL=500
1.4 V
Output load (A)
(V
CC
= 2.2 V to 2.7 V)
Output load (B)
(V
CC
= 2.7 V to 3.6 V)
Read Cycle
R1LV0416CBG-I
-5SI
-7LI
Parameter
Symbol Min Max Min Max Unit Notes
Read cycle time
t
RC
55
70
ns
Address access time
t
AA
55
70 ns
Chip select access time
t
ACS1
55
70 ns
t
ACS2
55
70 ns
Output enable to output valid
t
OE
35
40 ns
Output hold from address change
t
OH
10
10
ns
LB#, UB# access time
t
BA
55
70 ns
Chip select to output in low-Z
t
CLZ1
10
10
ns 2,
3
t
CLZ2
10
10
ns 2,
3
LB#, UB# disable to low-Z
t
BLZ
5
5
ns 2,
3
Output enable to output in low-Z
t
OLZ
5
5
ns 2,
3
Chip deselect to output in high-Z
t
CHZ1
0 20 0 25 ns 1,
2,
3
t
CHZ2
0 20 0 25 ns 1,
2,
3
LB#, UB# disable to high-Z
t
BHZ
0 20 0 25 ns 1,
2,
3
Output disable to output in high-Z
t
OHZ
0 20 0 25 ns 1,
2,
3
R1LV0416CBG-I Series
Rev.0.01, Jan.11.2005, page 7 of 14
Write Cycle
R1LV0416CBG-I
-5SI
-7LI
Parameter
Symbol Min Max Min Max Unit Notes
Write cycle time
t
WC
55
70
ns
Address valid to end of write
t
AW
50
60
ns
Chip selection to end of write
t
CW
50
60
ns 5
Write pulse width
t
WP
40
50
ns 4
LB#, UB# valid to end of write
t
BW
50
55
ns
Address setup time
t
AS
0
0
ns 6
Write recovery time
t
WR
0
0
ns 7
Data to write time overlap
t
DW
25
30
ns
Data hold from write time
t
DH
0
0
ns
Output active from end of write
t
OW
5
5
ns 2
Output disable to output in high-Z
t
OHZ
0 20 0 25 ns 1,
2,
3
Write to output in high-Z
t
WHZ
0 20 0 25 ns 1,
2
Notes: 1. t
CHZ
, t
OHZ
, t
WHZ
and t
BHZ
are defined as the time at which the outputs achieve the open circuit conditions and
are not referred to output voltage levels.
2. This parameter is sampled and not 100% tested.
3. At any given temperature and voltage condition, t
HZ
max is less than t
LZ
min both for a given device and from
device to device.
4. A write occures during the overlap of a low CS1#, a high CS2, a low WE# and a low LB# or a low UB#. A
write begins at the latest transition among CS1# going low, CS2 going high, WE# going low and LB# going
low or UB# going low. A write ends at the earliest transition among CS1# going high, CS2 going low, WE#
going high and LB# going high or UB# going high. t
WP
is measured from the beginning of write to the end of
write.
5.
t
CW
is measured from the later of CS1# going low or CS2 going high to the end of write.
6.
t
AS
is measured from the address valid to the beginning of write.
7.
t
WR
is measured from the earliest of CS1# or WE# going high or CS2 going low to the end of write cycle.
R1LV0416CBG-I Series
Rev.0.01, Jan.11.2005, page 8 of 14
Timing Waveform
Read Timing Waveform (WE# = V
IH
)
t
AA
t
ACS1
t
ACS2
t
CLZ2
t
CLZ1
t
BLZ
t
BA
t
OH
t
RC
Valid data
Address
Dout
Valid address
High impedance
CS1#
CS2
LB#, UB#
OE#
*
1, 2, 3
*
1, 2, 3
*
2, 3
*
2, 3
*
2, 3
*
1, 2, 3
t
OLZ
*
2, 3
*
1, 2, 3
t
OE
t
CHZ1
t
CHZ2
t
BHZ
t
OHZ
R1LV0416CBG-I Series
Rev.0.01, Jan.11.2005, page 9 of 14
Write Timing Waveform (1) (WE# Clock)
Address
WE#
t
WC
t
AW
t
WP
*
4
t
WR
*
7
t
CW
*
5
t
CW
*
5
t
BW
t
AS
*
6
t
OW
*
2
t
WHZ*
1, 2
t
DW
t
DH
Valid address
Valid data
CS1#
LB#, UB#
Dout
Din
High impedance
CS2
R1LV0416CBG-I Series
Rev.0.01, Jan.11.2005, page 10 of 14
Write Timing Waveform (2) (CS# Clock, OE# = V
IH
)
Address
WE#
t
WC
t
AW
t
WP
*
4
t
WR
*
7
t
CW
*
5
t
CW
*
5
t
BW
t
AS
*
6
t
DW
t
DH
Valid address
Valid data
LB#, UB#
Dout
Din
High impedance
CS2
CS1#
R1LV0416CBG-I Series
Rev.0.01, Jan.11.2005, page 11 of 14
Write Timing Waveform (3) (LB#, UB# Clock, OE# = V
IH
)
Address
WE#
t
WC
t
AW
t
WP
*
4
t
CW
*
5
t
CW
*
5
t
BW
t
WR
*
7
t
DW
t
DH
Valid address
Valid data
LB#, UB#
Dout
Din
High impedance
CS2
CS1#
t
AS
*
6
R1LV0416CBG-I Series
Rev.0.01, Jan.11.2005, page 12 of 14
Low V
CC
Data Retention Characteristics
(Ta =
-40 to +85C)
Parameter Symbol
Min
Typ
Max Unit
Test
conditions
*
3
V
CC
for data retention
V
DR
2.0
V
Vin
0V
(1) 0 V
CS2
0.2 V or
(2) CS2
V
CC
-
0.2 V,
CS1#
V
CC
-
0.2 V or
(3) LB# = UB#
V
CC
-
0.2 V,
CS2
V
CC
-
0.2 V,
CS1#
0.2 V
to +85
C I
CCDR
10
A
to +70
C I
CCDR
8
A
to +40
C
I
CCDR
0.7
*
2
3
A
-
5SI
to +25
C I
CCDR
0.5
*
1
2.5
A
to +85
C I
CCDR
20
A
to +70
C I
CCDR
16
A
to +40
C I
CCDR
0.7
*
2
10
A
Data
retention
current
-
7LI
to +25
C I
CCDR
0.5
*
1
10
A
V
CC
= 3.0 V, Vin
0V
(1) 0 V
CS2
0.2 V or
(2) CS2
V
CC
-
0.2 V,
CS1#
V
CC
-
0.2 V or
(3) LB# = UB#
V
CC
-
0.2 V,
CS2
V
CC
-
0.2 V,
CS1#
0.2 V
Chip deselect to data retention time
t
CDR
0
ns See retention waveform
Operation recovery time
t
R
t
RC
*
4
ns
Notes: 1. Typical values are at V
CC
= 3.0 V, Ta = +25
C and specified loading, and not guaranteed.
2. Typical values are at V
CC
= 3.0 V, Ta = +40
C and specified loading, and not guaranteed.
3. CS2 controls address buffer, WE# buffer, CS1# buffer, OE# buffer, LB#, UB# buffer and Din buffer. If CS2
controls data retention mode, Vin levels (address, WE#, OE#, CS1#, LB#, UB#, I/O) can be in the high
impedance state. If CS1# controls data retention mode, CS2 must be CS2
V
CC
-
0.2 V or 0 V
CS2
0.2
V. The other input levels (address, WE#, OE#, LB#, UB#, I/O) can be in the high impedance state.
4.
t
RC
= read cycle time.
R1LV0416CBG-I Series
Rev.0.01, Jan.11.2005, page 13 of 14
Low V
CC
Data Retention Timing Waveform (1) (CS1# Controlled) (V
CC
= 2.2 V to 2.7 V)
CC
V
2.2 V
2.0 V
0 V
CS1#
t
CDR
t
R
CS1# V 0.2 V
CC
DR
V
Data retention mode
Low V
CC
Data Retention Timing Waveform (2) (CS1# Controlled) (V
CC
= 2.7 V to 3.6 V)
CC
V
2.2 V
2.7 V
0 V
CS1#
t
CDR
t
R
CS1# V 0.2 V
CC
DR
V
Data retention mode
Low V
CC
Data Retention Timing Waveform (3) (CS2 Controlled) (V
CC
= 2.2 V to 2.7 V)
CC
V
2.2 V
0.4 V
0 V
CS2
CDR
t
R
0 V CS2 0.2 V
DR
V
Data retention mode
t
<
<
Low V
CC
Data Retention Timing Waveform (4) (CS2 Controlled) (V
CC
= 2.7 V to 3.6 V)
CC
V
2.7 V
0.6 V
0 V
CS2
CDR
t
R
0 V CS2 0.2 V
DR
V
Data retention mode
t
<
<
R1LV0416CBG-I Series
Rev.0.01, Jan.11.2005, page 14 of 14
Low V
CC
Data Retention Timing Waveform (5) (LB#, UB# Controlled) (V
CC
= 2.2 V to 2.7 V)
CC
V
2.2 V
2.0 V
0 V
LB#, UB#
t
CDR
t
R
LB#, UB# V 0.2 V
CC
DR
V
Data retention mode
Low V
CC
Data Retention Timing Waveform (6) (LB#, UB# Controlled) (V
CC
= 2.7 V to 3.6 V)
CC
V
2.2 V
2.7 V
0 V
LB#, UB#
t
CDR
t
R
LB#, UB# V 0.2 V
CC
DR
V
Data retention mode
Revision History
R1LV0416CBG-I Series
Contents of Modification
Rev. Date
Page Description
0.01 Jan.11.2005
Initial
issue
Keep safety first in your circuit designs!
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