Rev.1.00, Mar.12.2004, page 1 of 11
R1RW0404D Series
4M High Speed SRAM (1-Mword
4-bit)
REJ03C0115-0100Z
Rev. 1.00
Mar.12.2004
Description
The R1RW0404D is a 4-Mbit high speed static RAM organized 1-Mword
4-bit. It has realized high
speed access time by employing CMOS process (6-transistor memory cell) and high speed circuit
designing technology. It is most appropriate for the application which requires high speed and high density
memory, such as cache and buffer memory in system. The R1RW0404D is packaged in 400-mil 32-pin
SOJ for high density surface mounting.
Features
Single supply: 3.3 V
0.3 V
Access time: 12 ns (max)
Completely static memory
No clock or timing strobe required
Equal access and cycle times
Directly TTL compatible
All inputs and outputs
Operating current: 100 mA (max)
TTL standby current: 40 mA (max)
CMOS standby current : 5 mA (max)
: 0.8 mA (max) (L-version)
Data retention current: 0.4 mA (max) (L-version)
Data retention voltage: 2 V (min) (L-version)
Center V
CC
and V
SS
type pin out
R1RW0404D Series
Rev.1.00, Mar.12.2004, page 2 of 11
Ordering Information
Type No.
Access time
Package
R1RW0404DGE-2PR
12 ns
400-mil 32-pin plastic SOJ (32P0K)
R1RW0404DGE-2LR 12
ns
Pin Arrangement
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A0
A1
A2
A3
A4
CS#
I/O1
V
CC
V
SS
I/O2
WE#
A5
A6
A7
A8
A9
A19
A18
A17
A16
A15
OE#
I/O4
V
SS
V
CC
I/O3
A14
A13
A12
A11
A10
NC
(Top view)
32-pin SOJ
Pin Description
Pin name
Function
A0 to A19
Address input
I/O1 to I/O4
Data input/output
CS# Chip
select
OE# Output
enable
WE# Write
enable
V
CC
Power
supply
V
SS
Ground
NC No
connection
R1RW0404D Series
Rev.1.00, Mar.12.2004, page 3 of 11
Block Diagram
I/O1
.
.
.
I/O4
WE#
Input
data
control
Column I/O
Column decoder
1024-row
64-column
16-block
4-bit
(4,194,304 bits)
Row
decoder
OE#
CS#
CS
CS
V
CC
V
SS
CS
A14
A13
A12
A5
A6
A7
A11
A10
A3
A1
A8 A9 A19 A17 A18 A15 A0 A2 A4 A16
(LSB)
(MSB)
(LSB)
(MSB)
R1RW0404D Series
Rev.1.00, Mar.12.2004, page 4 of 11
Operation Table
CS# OE# WE# Mode
V
CC
current
I/O
Ref. cycle
H
Standby I
SB
, I
SB1
High-Z
L H H Output
disable
I
CC
High-Z
L L H Read
I
CC
D
OUT
Read cycle (1) to (3)
L H L Write
I
CC
D
IN
Write cycle (1)
L L L Write
I
CC
D
IN
Write cycle (2)
Note: H: V
IH
, L: V
IL
,
: V
IH
or V
IL
Absolute Maximum Ratings
Parameter Symbol
Value
Unit
Supply voltage relative to V
SS
V
CC
-
0.5 to +4.6
V
Voltage on any pin relative to V
SS
V
T
-
0.5
*
1
to V
CC
+ 0.5
*
2
V
Power dissipation
P
T
1.0
W
Operating temperature
Topr
0 to +70
C
Storage temperature
Tstg
-
55 to +125
C
Storage temperature under bias
Tbias
-
10 to +85
C
Notes: 1. V
T
(min) =
-
2.0 V for pulse width (under shoot)
6 ns.
2.
V
T
(max) = V
CC
+ 2.0 V for pulse width (over shoot)
6 ns.
Recommended DC Operating Conditions
(Ta = 0 to +70
C)
Parameter Symbol
Min
Typ
Max
Unit
Supply voltage
V
CC
*
3
3.0 3.3 3.6 V
V
SS
*
4
0 0 0 V
Input voltage
V
IH
2.0
V
CC
+ 0.5
*
2
V
V
IL
-
0.5
*
1
0.8 V
Notes: 1. V
IL
(min) =
-
2.0 V for pulse width (under shoot)
6 ns.
2.
V
IH
(max) = V
CC
+ 2.0 V for pulse width (over shoot)
6 ns.
3. The supply voltage with all V
CC
pins must be on the same level.
4. The supply voltage with all V
SS
pins must be on the same level.
R1RW0404D Series
Rev.1.00, Mar.12.2004, page 5 of 11
DC Characteristics
(Ta = 0 to +70
C, V
CC
= 3.3 V
0.3 V, V
SS
= 0 V)
Parameter Symbol
Min
Max
Unit
Test
conditions
Input leakage current
II
LI
I
2
A V
IN
= V
SS
to V
CC
Output leakage current
II
LO
I
2
A V
IN
= V
SS
to V
CC
Operation power supply current
I
CC
100
mA
Min
cycle
CS# = V
IL
, l
OUT
= 0 mA
Other inputs = V
IH
/V
IL
Standby power supply current
I
SB
40
mA
Min cycle, CS# = V
IH
,
Other inputs = V
IH
/V
IL
I
SB1
5
mA
f = 0 MHz
V
CC
CS#
V
CC
-
0.2 V,
(1) 0 V
V
IN
0.2 V or
(2) V
CC
V
IN
V
CC
-
0.2 V
*
1
0.8
*
1
Output voltage
V
OL
0.4 V I
OL
= 8 mA
V
OH
2.4
V I
OH
=
-
4 mA
Note: 1. This characteristics is guaranteed only for L-version.
Capacitance
(Ta = +25
C, f = 1.0 MHz)
Parameter Symbol
Min
Max
Unit
Test
conditions
Input capacitance
*
1
C
IN
6 pF V
IN
= 0 V
Input/output capacitance
*
1
C
I/O
8 pF V
I/O
= 0 V
Note: 1. This parameter is sampled and not 100% tested.
R1RW0404D Series
Rev.1.00, Mar.12.2004, page 6 of 11
AC Characteristics
(Ta = 0 to +70
C, V
CC
= 3.3 V
0.3 V, unless otherwise noted.)
Test Conditions
Input pulse levels: 3.0 V/0.0 V
Input rise and fall time: 3 ns
Input and output timing reference levels: 1.5 V
Output load: See figures (Including scope and jig)
D
OUT
353
319
3.3 V
5 pF
Output load (B)
(for t
CLZ
, t
OLZ
, t
CHZ
, t
OHZ
, t
WHZ
, and t
OW
)
Output load (A)
1.5 V
30 pF
D
OUT
RL=50
Zo=50
Read Cycle
R1RW0404D
-2
Parameter Symbol
Min
Max
Unit
Notes
Read cycle time
t
RC
12
ns
Address access time
t
AA
12 ns
Chip select access time
t
ACS
12 ns
Output enable to output valid
t
OE
6 ns
Output hold from address change
t
OH
3
ns
Chip select to output in low-Z
t
CLZ
3
ns
1
Output enable to output in low-Z
t
OLZ
0
ns
1
Chip deselect to output in high-Z
t
CHZ
6 ns
1
Output disable to output in high-Z
t
OHZ
6 ns
1
R1RW0404D Series
Rev.1.00, Mar.12.2004, page 7 of 11
Write Cycle
R1RW0404D
-2
Parameter Symbol
Min
Max
Unit
Notes
Write cycle time
t
WC
12
ns
Address valid to end of write
t
AW
8
ns
Chip select to end of write
t
CW
8
ns
9
Write pulse width
t
WP
8
ns
8
Address setup time
t
AS
0
ns
6
Write recovery time
t
WR
0
ns
7
Data to write time overlap
t
DW
6
ns
Data hold from write time
t
DH
0
ns
Write disable to output in low-Z
t
OW
3
ns
1
Output disable to output in high-Z
t
OHZ
6 ns
1
Write enable to output in high-Z
t
WHZ
6 ns
1
Notes: 1. Transition is measured
200 mV from steady voltage with output load (B). This parameter is
sampled and not 100% tested.
2. Address should be valid prior to or coincident with CS# transition low.
3. WE# and/or CS# must be high during address transition time.
4. If CS# and OE# are low during this period, I/O pins are in the output state. Then, the data input
signals of opposite phase to the outputs must not be applied to them.
5. If the CS# low transition occurs simultaneously with the WE# low transition or after the WE#
transition, output remains a high impedance state.
6.
t
AS
is measured from the latest address transition to the later of CS# or WE# going low.
7.
t
WR
is measured from the earlier of CS# or WE# going high to the first address transition.
8. A write occurs during the overlap of a low CS# and a low WE#. A write begins at the latest
transition among CS# going low and WE# going low. A write ends at the earliest transition
among CS# going high and WE# going high. t
WP
is measured from the beginning of write to the
end of write.
9.
t
CW
is measured from the later of CS# going low to the end of write.
R1RW0404D Series
Rev.1.00, Mar.12.2004, page 8 of 11
Timing Waveforms
Read Timing Waveform (1) (WE# = V
IH
)
t
AA
t
ACS
t
RC
t
OE
t
CLZ
Valid data
Address
CS#
D
OUT
Valid address
High impedance
t
OHZ
OE#
t
OH
t
CHZ
t
OLZ
Read Timing Waveform (2) (WE# = V
IH
, CS# = V
IL
, OE# = V
IL
)
t
AA
t
RC
Valid data
Address
D
OUT
Valid address
t
OH
t
OH
R1RW0404D Series
Rev.1.00, Mar.12.2004, page 9 of 11
Read Timing Waveform (3) (WE# = V
IH
, CS# = V
IL
, OE# = V
IL
)*
2
Valid data
CS#
D
OUT
High
impedance
High
impedance
t
CLZ
t
ACS
t
RC
t
CHZ
Write Timing Waveform (1) (WE# Controlled)
Address
WE#*
3
D
OUT
D
IN
t
WC
t
WP
t
WR
t
CW
t
DW
t
DH
Valid address
t
AW
Valid data
t
AS
CS#*
3
t
OHZ
*
4
*
4
OE#
High impedance*
5
R1RW0404D Series
Rev.1.00, Mar.12.2004, page 10 of 11
Write Timing Waveform (2) (CS# Controlled)
Address
WE# *
3
D
OUT
D
IN
t
WC
t
WP
t
WR
t
CW
t
DW
t
DH
Valid address
t
AW
Valid data
t
AS
CS# *
3
t
WHZ
t
OW
*
4
*
4
High impedance*
5
R1RW0404D Series
Rev.1.00, Mar.12.2004, page 11 of 11
Low V
CC
Data Retention Characteristics
(Ta = 0 to +70
C)
This characteristics is guaranteed only for L-version.
Parameter Symbol
Min
Max
Unit
Test
conditions
V
CC
for data retention
V
DR
2.0
V
V
CC
CS#
V
CC
-
0.2 V
(1) 0 V
V
IN
0.2 V or
(2) V
CC
V
IN
V
CC
-
0.2 V
Data retention current
I
CCDR
400
A V
CC
= 3 V, V
CC
CS#
V
CC
-
0.2 V
(1) 0 V
V
IN
0.2 V or
(2) V
CC
V
IN
V
CC
-
0.2 V
Chip deselect to data
retention time
t
CDR
0
ns
See retention waveform
Operation recovery time
t
R
5
ms
Low V
CC
Data Retention Timing Waveform
CC
V
3.0 V
0 V
CS#
t
CDR
t
R
V
CC
CS#
V
CC
-
0.2 V
2.0 V
DR
V
Data retention mode
Revision History
R1RW0404D Series Data Sheet
Contents of Modification
Rev. Date
Page Description
0.01 Oct. 01, 2003
Initial
issue
1.00 Mar.12.2004
Deletion of Preliminary
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