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Электронный компонент: R5F21113DFP

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R8C/11 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
REJ03B0034-0140Z
Rev.1.40
Sep 30, 2004
Rev.1.40 Sep 30, 2004 page 1 of 26
REJ03B0034-0140Z
1. Overview
This MCU is built using the high-performance silicon gate CMOS process using a R8C/Tiny Series CPU
core and is packaged in a 32-pin plastic molded LQFP. This MCU operates using sophisticated instructions
featuring a high level of instruction efficiency. With 1M bytes of address space, it is capable of executing
instructions at high speed.
1.1 Applications
Electric household appliance, office equipment, housing equipment (sensor, security), general industrial
equipment, audio, etc.
Rev.1.40 Sep 30, 2004 page 2 of 26
REJ03B0034-0140Z
R8C/11 Group
1. Overview
Table 1.1 Performance outline
1.2 Performance Outline
Table 1.1. lists the performance outline of this MCU.
Item
Performance
CPU
Number of basic instructions 89 instructions
Shortest instruction execution time
50 ns (f(X
IN
) = 20 MH
Z
, V
CC
= 3.0 to 5.5 V)
100 ns (f(X
IN
) = 10 MH
Z
, V
CC
= 2.7 to 5.5 V)
Operating mode
Single-chip
Address space
1M bytes
Memory capacity
See Table 1.2.
Peripheral
Interrupt
Internal: 11 factors, External: 5 factors,
function
Software: 4 factors, Priority level: 7 levels
Watchdog timer
15 bits x 1 (with prescaler)
Timer
Timer X: 8 bits x 1 channel, Timer Y: 8 bits x 1 channel,
Timer Z: 8 bits x 1 channel
(Each timer equipped with 8-bit prescaler)
Timer C: 16 bits x 1 channel
Circuits of input capture and output compare.
Serial Interface
1 channel
Clock synchronous, UART
1 channel
UART
A/D converter
10-bit A/D converter: 1 circuit, 12 channels
Clock generation circuit
2 circuits
Main clock generation circuit (Equipped with a built-in
feedback resistor)
On-chip oscillator (high speed, low speed)
On high-speed on-chip oscillator the frequency adjust-
ment function is usable.
Oscillation stop detection function Stop detection of main clock oscillation
Voltage detection circuit
Included
Power on reset circuit
Included
Port
Input/Output: 22 (including LED drive port), Input: 2
(LED drive I/O port: 8)
Electrical
Power supply voltage
V
CC
= 3.0 to 5.5 V (f(X
IN
) = 20 MH
Z
)
characteristics
V
CC
= 2.7 to 5.5 V (f(X
IN
) = 10 MH
Z
)
Power consumption
Typ. 9 mA (V
CC
= 5.0 V, (f(X
IN
) = 20 MH
Z
, High-speed mode)
Typ. 5 mA (V
CC
= 3.0 V, (f(X
IN
) = 10 MH
Z
, High-speed mode)
Typ. 35
A (V
CC
= 3.0 V, Wait mode, Peripheral clock stops)
Typ. 0.7
A (V
CC
= 3.0 V, Stop mode)
Flash memory Program/erase voltage
V
CC
= 2.7 to 5.5 V
Number of program/erase
100 times
Operating ambient temperature
-20 to 85 C
-40 to 85 C (D-version)
Package
32-pin plastic mold LQFP
Rev.1.40 Sep 30, 2004 page 3 of 26
REJ03B0034-0140Z
R8C/11 Group
1. Overview
1.3 Block Diagram
Figure 1.1 shows this MCU block diagram.
Figure 1.1 Block Diagram
Timer X (8 bits)
Timer Y (8 bits)
Timer Z (8 bits)
Timer C (16 bits)
Watchdog timer
(15 bits)
Memory
ROM
(Note 1)
R
8
C
S
e
r
i
e
s
C
P
U
c
o
r
e
I
/
O
p
o
r
t
P
o
r
t
P
0
8
P
o
r
t
P
1
8
Port P3
5
Multiplier
S
y
s
t
e
m
c
l
o
c
k
g
e
n
e
r
a
t
o
r
X
IN
-X
OUT
High-speed on-chip oscillator
Low-speed on-chip oscillator
U
A
R
T
(
8
b
i
t
s
1
c
h
a
n
n
e
l
)
P
o
r
t
P
4
1
2
Pe
r
i
p
h
e
r
a
l
f
u
n
c
t
i
o
n
s
U
A
R
T
o
r
C
l
o
c
k
s
y
n
c
h
r
o
n
o
u
s
s
e
r
i
a
l
I
/
O
(
8
b
i
t
s
1
c
h
a
n
n
e
l
)
A
/
D
c
o
n
v
e
r
t
e
r
(
1
0
b
i
t
s
1
2
c
h
a
n
n
e
l
s
)
RAM
(Note 2)
N
o
t
e
1
:
R
O
M
s
i
z
e
d
e
p
e
n
d
s
o
n
M
C
U
t
y
p
e
.
N
o
t
e
2
:
R
A
M
s
i
z
e
d
e
p
e
n
d
s
o
n
M
C
U
t
y
p
e
.
R0L
R0H
R1H
R1L
R2
R3
A0
A1
FB
S
B
ISP
USP
INTB
PC
F
L
G
T
i
m
e
r
Rev.1.40 Sep 30, 2004 page 4 of 26
REJ03B0034-0140Z
R8C/11 Group
1. Overview
1.4 Product List
Table 1.2 lists the products.
Table 1.2 Product List
RAM capacity
ROM capacity
Package type
Remarks
Type No.
As of Sep. 2004
Flash memory version
R5F21112FP
32P6U-A
8K bytes
512 bytes
32P6U-A
12K bytes
768 bytes
32P6U-A
16K bytes
1K bytes
R5F21113FP
R5F21114FP
R5F21112DFP
32P6U-A
8K bytes
512 bytes
32P6U-A
12K bytes
768 bytes
32P6U-A
16K bytes
1K bytes
R5F21113DFP
R5F21114DFP
D version
Figure 1.2 Type No., Memory Size, and Package
Package type:
FP : 32P6U
ROM capacity:
2 : 8 KBytes.
3 : 12 KBytes.
4 : 16 KBytes.
Memory type:
F: Flash memory version
Type No. R 5 F
21 11
4
D FP
R8C/11 group
R8C/Tiny series
Shows characteristics and others.
D: Operating ambient temperature 40 C to 85 C
No symbol: Operating ambient temperature 20 C to 85 C
Renesas MCU
Renesas semiconductors
Rev.1.40 Sep 30, 2004 page 5 of 26
REJ03B0034-0140Z
R8C/11 Group
1. Overview
Package: 32P6U-A
Figure 1.3 Pin Configuration (Top View)
PIN CONFIGURATION (top view)
1 2 3 4 5 6 7 8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
2
9
2
8
2
7
2
6
2
5
2
4 2
3 2
2 2
1 2
0 1
9 1
8 1
7
3
2
3
1
3
0
R
8
C
/
1
1
G
r
o
u
p
X
I
N
/
P
4
6
X
O
U
T
/
P
4
7
(N
o
t
e
1
)
V
S
S
R
E
S
E
T
V
C
C
C
N
V
S
S
P
1
7
/
I
N
T
1
/
C
N
T
R
0
P
1
6
/
C
L
K
0
P
1
5
/
R
x
D
0
P
1
4
/
T
x
D
0
P
3
7
/
T
x
D
1
0
/
R
x
D
1
P
3
0
/
C
N
T
R
0
/
C
M
P
1
0
P
3
3
/
I
N
T
3
/
P
3
1
/
T
Z
O
U
T
/
C
M
P
1
1
P
3
2
/
I
N
T
2
/
C
N
T
R
1
/
C
M
P
1
2
I
V
C
C
3
A
V
S
S
A
V
C
C
/
V
R
E
F
P
0
3
/
A
N
4
P0
2
/AN
5
P
0
1
/
A
N
6
P
0
0
/
A
N
7
/T
x
D
1
1
P
0
6
/
A
N
1
P
0
5
/
A
N
2
P
0
4
/
A
N
3
P
4
5
/
I
N
T
0
P
1
0
/
K
I
0
/
A
N
8
/
C
M
P
0
0
P1
1
/KI
1
/AN
9
/CMP0
1
P1
2
/KI
2
/AN
10
/CMP0
2
P1
3
/KI
3
/AN
11
P
0
7
/
A
N
0
MODE
T
C
I
N
Notes:
1. P4
7
functions only as an input port.
2. When using On-chip debugger, do not use pins P0
0
/AN
7
/TxD
11
and P3
7
/TxD
10
/RxD
1
.
3. Do not connect IVcc to Vcc.
1.5 Pin Configuration
Figure 1.3 shows the pin configuration (top view).
Rev.1.40 Sep 30, 2004 page 6 of 26
REJ03B0034-0140Z
R8C/11 Group
1. Overview
Signal name
Pin name
I/O type
Power supply
Vcc,
I
input
Vss
IVcc
IVcc
O
Analog power
AVcc, AVss
I
supply input
Reset input
___________
RESET
I
CNVss
CNVss
I
MODE
MODE
I
Main clock input
X
IN
I
Main clock output X
OUT
O
_____
INT interrupt input
_______
_______
INT
0
to INT
3
I
Key input interrupt
_____
_____
KI
0
to KI
3
I
Timer X
CNTR
0
I/O
____________
CNTR
0
O
Timer Y
CNTR
1
I/O
Timer Z
TZ
OUT
O
Timer C
TC
IN
I
CMP0
0
to CMP0
3
, O
CMP1
0
to CMP1
3
Serial interface
CLK
0
I/O
RxD
0
, RxD
1
I
TxD
0
, TxD
10
,
O
TxD
11
Reference voltage V
REF
I
input
A/D converter
AN
0
to AN
11
I
I/O port
P0
0
to P0
7
,
I/O
P1
0
to P1
7
,
P3
0
to P3
3
, P3
7
,
P4
5
Input port
P4
6
, P4
7
I
Function
Apply 2.7 V to 5.5 V to the Vcc pin. Apply 0 V to the
Vss pin.
This pin is to stabilize internal power supply.
Connect this pin to Vss via a capacitor (0.1
F).
Do not connect to Vcc.
These are power supply input pins for A/D converter.
Connect the AVss pin to Vss. Connect a capacitor
between pins AVcc and AVss.
"L" on this input resets the MCU.
Connect this pin to Vss via a resistor.
Connect this pin to Vcc via a resistor.
These pins are provided for the main clock generat-
ing circuit I/O. Connect a ceramic resonator or a crys-
tal oscillator between the X
IN
and X
OUT
pins. To use
an externally derived clock, input it to the X
IN
pin and
leave the X
OUT
pin open.
______
These are INT interrupt input pins.
These are key input interrupt pins.
This is the timer X I/O pin.
This is the timer X output pin.
This is the timer Y I/O pin.
This is the timer Z output pin.
This is the timer C input pin.
These are the timer C output pins.
This is a transfer clock I/O pin.
These are serial data input pins.
These are serial data output pins.
This is a reference voltage input pin for A/D con-
verter.
These are analog input pins for A/D converter.
These are 8-bit CMOS I/O ports. Each port has an
input/output select direction register, allowing each
pin in that port to be directed for input or output indi-
vidually.
Any port set to input can select whether to use a pull-
up resistor or not by program.
P1
0
to P1
7
also function as LED drive ports.
These are input only pins.
1.6 Pin Description
Table 1.3 shows the pin description
Table 1.3 Pin description
Rev.1.40 Sep 30, 2004 page 7 of 26
REJ03B0034-0140Z
R8C/11 Group
2. Central Processing Unit (CPU)
2. Central Processing Unit (CPU)
Figure 2.1 shows the CPU registers. The CPU has 13 registers. Of these, R0, R1, R2, R3, A0, A1 and FB
comprise a register bank. There are two register banks.
2.1 Data Registers (R0, R1, R2 and R3)
The R0 register consists of 16 bits, and is used mainly for transfers and arithmetic/logic operations. R1 to
R3 are the same as R0.
The R0 register can be separated between high (R0H) and low (R0L) for use as two 8-bit data registers.
R1H and R1L are the same as R0H and R0L. Conversely, R2 and R0 can be combined for use as a 32-
bit data register (R2R0). R3R1 is the same as R2R0.
Data registers (Note 1)
Address registers (Note 1)
Frame base registers (Note 1)
Program counter
Interrupt table register
User stack pointer
Interrupt stack pointer
Static base register
Flag register
Note 1: These registers comprise a register bank. There are two register banks.
R0H(R0's high bits)
b15
b8
b7
b0
R3
INTBH
USP
ISP
SB
C
D
Z
S
B
O
I
U
IPL
R0L(R0's low bits)
R1H(R1's high bits)R1L(R1's low bits)
R2
b31
R3
R2
A1
A0
FB
b19
INTBL
b15
b0
PC
b19
b0
b15
b0
FLG
b15
b0
b15
b0
b7
b8
Reserved area
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved area
Processor interrupt priority level
The upper 4 bits of INTB are INTBH and
the lower 16 bits of INTB are INTBL.
Figure 2.1. Central Processing Unit Register
Rev.1.40 Sep 30, 2004 page 8 of 26
REJ03B0034-0140Z
R8C/11 Group
2. Central Processing Unit (CPU)
2.2 Address Registers (A0 and A1)
The register A0 consists of 16 bits, and is used for address register indirect addressing and address
register relative addressing. They also are used for transfers and logic/logic operations. A1 is the same as A0.
In some instructions, registers A1 and A0 can be combined for use as a 32-bit address register (A1A0).
2.3 Frame Base Register (FB)
FB is configured with 16 bits, and is used for FB relative addressing.
2.4 Interrupt Table Register (INTB)
INTB is configured with 20 bits, indicating the start address of an interrupt vector table.
2.5 Program Counter (PC)
PC is configured with 20 bits, indicating the address of an instruction to be executed.
2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
Stack pointer (SP) comes in two types: USP and ISP, each configured with 16 bits.
Your desired type of stack pointer (USP or ISP) can be selected by the U flag of FLG.
2.7 Static Base Register (SB)
SB is configured with 16 bits, and is used for SB relative addressing.
2.8 Flag Register (FLG)
FLG consists of 11 bits, indicating the CPU status.
2.8.1 Carry Flag (C Flag)
This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit.
2.8.2 Debug Flag (D Flag)
The D flag is used exclusively for debugging purpose. During normal use, it must be set to "0".
2.8.3 Zero Flag (Z Flag)
This flag is set to "1" when an arithmetic operation resulted in 0; otherwise, it is "0".
2.8.4 Sign Flag (S Flag)
This flag is set to "1" when an arithmetic operation resulted in a negative value; otherwise, it is "0".
2.8.5 Register Bank Select Flag (B Flag)
Register bank 0 is selected when this flag is "0" ; register bank 1 is selected when this flag is "1".
2.8.6 Overflow Flag (O Flag)
This flag is set to "1" when the operation resulted in an overflow; otherwise, it is "0".
2.8.7 Interrupt Enable Flag (I Flag)
This flag enables a maskable interrupt.
Maskable interrupts are disabled when the I flag is "0", and are enabled when the I flag is "1". The I
flag is cleared to "0" when the interrupt request is accepted.
2.8.8 Stack Pointer Select Flag (U Flag)
ISP is selected when the U flag is "0"; USP is selected when the U flag is "1".
The U flag is cleared to "0" when a hardware interrupt request is accepted or an INT instruction for
software interrupt Nos. 0 to 31 is executed.
2.8.9 Processor Interrupt Priority Level (IPL)
IPL is configured with three bits, for specification of up to eight processor interrupt priority levels from
level 0 to level 7.
If a requested interrupt has priority greater than IPL, the interrupt is enabled.
2.8.10 Reserved Area
When write to this bit, write "0". When read, its content is indeterminate.
Rev.1.40 Sep 30, 2004 page 9 of 26
REJ03B0034-0140Z
R8C/11 Group
3. Memory
3. Memory
Figure 3.1 is a memory map of this MCU. The address space extends the 1M bytes from address 00000
16
to FFFFF
16
.
The internal ROM is allocated in a lower address direction beginning with address 0FFFF
16
. For example,
a 16-Kbyte internal ROM is allocated to the addresses from 0C000
16
to 0FFFF
16
.
The fixed interrupt vector table is allocated to the addresses from 0FFDC
16
to 0FFFF
16
. Therefore, store
the start address of each interrupt routine here.
The internal RAM is allocated in an upper address direction beginning with address 00400
16
. For example,
a 1-Kbyte internal RAM is allocated to the addresses from 00400
16
to 007FF
16
. In addition to storing data,
the internal RAM also stores the stack used when calling subroutines and when interrupts are generated.
Special function registers (SFR) are allocated to the addresses from 00000
16
to 002FF
16
. Peripheral func-
tion control registers are located here. Of the SFR, any space which has no functions allocated is reserved
for future use and cannot be used by users.
Figure 3.1 Memory Map
00000
16










































































0YYYY
16






















































































0FFFF
16































































002FF
16









































































00400
16




































































Internal ROM
SFR
(See Chapter 4 for details.)
0FFDC
16
0FFFF
16
Undefined instruction
Overflow
BRK instruction
Address match
Single step
Watchdog timer,Oscillation stop detection,Voltage detection
Reset
(Reserved)
Type name
0XXXX
16




































































Internal RAM
FFFFF
16































































Address 0XXXX
16
005FF
16
Internal RAM
Size
007FF
16
512 bytes
1K bytes
006FF
16
768 bytes
Address 0YYYY
16
0E000
16
Internal ROM
Size
0C000
16
8K bytes
16K bytes
0D000
16
12K bytes
Expanding area
(Reserved)
R5F21114FP, R5F21114DFP
R5F21113FP, R5F21113DFP
R5F21112FP, R5F21112DFP
NOTES :
1. Blank spaces are reserved. No access is allowed.
Rev.1.40 Sep 30, 2004 page 10 of 26
REJ03B0034-0140Z
R8C/11 Group
4. Special Function Register (SFR)
W
a
t
c
h
d
o
g
t
i
m
e
r
s
t
a
r
t
r
e
g
i
s
t
e
r
W
D
T
S
X
X
1
6
W
a
t
c
h
d
o
g
t
i
m
e
r
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
W
D
C
0
0
0
X
X
X
X
X
2
P
r
o
c
e
s
s
o
r
m
o
d
e
r
e
g
i
s
t
e
r
0
P
M
0
0
0
1
6
S
y
s
t
e
m
c
l
o
c
k
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
0
C
M
0
0
1
1
0
1
0
0
0
2
S
y
s
t
e
m
c
l
o
c
k
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
1
C
M
1
0
0
1
0
0
0
0
0
2
A
d
d
r
e
s
s
m
a
t
c
h
i
n
t
e
r
r
u
p
t
e
n
a
b
l
e
r
e
g
i
s
t
e
r
A
I
E
R
X
X
X
X
X
X
0
0
2
P
r
o
t
e
c
t
r
e
g
i
s
t
e
r
P
R
C
R
0
0
X
X
X
0
0
0
2
P
r
o
c
e
s
s
o
r
m
o
d
e
r
e
g
i
s
t
e
r
1
P
M
1
0
0
1
6
O
s
c
i
l
l
a
t
i
o
n
s
t
o
p
d
e
t
e
c
t
i
o
n
r
e
g
i
s
t
e
r
O
C
D
0
0
0
0
0
1
0
0
2
I
N
T
0
i
n
p
u
t
f
i
l
t
e
r
s
e
l
e
c
t
r
e
g
i
s
t
e
r
I
N
T
0
F
X
X
X
X
X
0
0
0
2
0000
16
0001
16
0002
16
0003
16
0004
16
0005
16
0006
16
0007
16
0008
16
0009
16
000A
16
000B
16
000C
16
000D
16
000E
16
000F
16
0010
16
0011
16
0012
16
0013
16
0014
16
0015
16
0016
16
0017
16
0018
16
0019
16
001A
16
001B
16
001C
16
001D
16
001E
16
001F
16
0020
16
0021
16
0022
16
0023
16
0024
16
0025
16
0026
16
0027
16
0028
16
0029
16
002A
16
002B
16
002C
16
002D
16
002E
16
002F
16
0030
16
0031
16
0032
16
0033
16
0034
16
0035
16
0036
16
0037
16
0038
16
0039
16
003A
16
003B
16
003C
16
003D
16
003E
16
003F
16
A
d
d
r
e
s
s
R
e
g
i
s
t
e
r
S
y
m
b
o
l
After
reset
A
d
d
r
e
s
s
m
a
t
c
h
i
n
t
e
r
r
u
p
t
r
e
g
i
s
t
e
r
0
R
M
A
D
0
0
0
1
6
0
0
1
6
X
0
1
6
A
d
d
r
e
s
s
m
a
t
c
h
i
n
t
e
r
r
u
p
t
r
e
g
i
s
t
e
r
1
R
M
A
D
1
0
0
1
6
0
0
1
6
X
0
1
6
W
a
t
c
h
d
o
g
t
i
m
e
r
r
e
s
e
t
r
e
g
i
s
t
e
r
W
D
T
R
X
X
1
6
High-speed on-chip control register 0
HR0
00
16
H
i
g
h
-
s
p
e
e
d
o
n
-
c
h
i
p
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
1
H
R
1
4
0
1
6
Voltage detection register 1
VCR1
00
16
V
o
l
t
a
g
e
d
e
t
e
c
t
i
o
n
r
e
g
i
s
t
e
r
2
V
C
R
2
X
X
X
0
0
0
0
0
1
6
V
o
l
t
a
g
e
d
e
t
e
c
t
i
o
n
i
n
t
e
r
r
u
p
t
r
e
g
i
s
t
e
r
D
4
I
N
T
0
0
1
6
1
2
2
2
01000001
2
3
4
X
:
U
n
d
e
f
i
n
e
d
N
O
T
E
S
:
1
.
B
l
a
n
k
c
o
l
u
m
n
s
a
r
e
a
l
l
r
e
s
e
r
v
e
d
s
p
a
c
e
.
N
o
a
c
c
e
s
s
i
s
a
l
l
o
w
e
d
.
2
.
S
o
f
t
w
a
r
e
r
e
s
e
t
o
r
t
h
e
w
a
t
c
h
d
o
g
t
i
m
e
r
r
e
s
e
t
d
o
e
s
n
o
t
a
f
f
e
c
t
t
h
i
s
r
e
g
i
s
t
e
r
.
3
.
O
w
i
n
g
t
o
R
e
s
e
t
i
n
p
u
t
.
4
.
I
n
t
h
e
c
a
s
e
o
f
R
E
S
E
T
p
i
n
=
H
r
e
t
a
i
n
i
n
g
.
4. Special Function Register (SFR)
SFR(Special Function Register) is the control register of peripheral functions. Tables 4.1 to 4.4 list the SFR
information
Table 4.1 SFR Information(1)
(1)
Rev.1.40 Sep 30, 2004 page 11 of 26
REJ03B0034-0140Z
R8C/11 Group
4. Special Function Register (SFR)
UART0 transmit interrupt control register
S0TIC
XXXXX000
2
UART0 receive interrupt control register
S0RIC
XXXXX000
2
UART1 transmit interrupt control register
S1TIC
XXXXX000
2
UART1 receive interrupt control register
S1RIC
XXXXX000
2
Key input interrupt control register
KUPIC
XXXXX000
2
A/D conversion interrupt control register
ADIC
XXXXX000
2
INT1 interrupt control register
INT1IC
XXXXX000
2
INT2 interrupt control register
INT2IC
XXXXX000
2
INT0 interrupt control register
INT0IC
XX00X000
2
INT3 interrupt control register
INT3IC
XXXXX000
2
0040
16
0041
16
0042
16
0043
16
0044
16
0045
16
0046
16
0047
16
0048
16
0049
16
004A
16
004B
16
004C
16
004D
16
004E
16
004F
16
0050
16
0051
16
0052
16
0053
16
0054
16
0055
16
0056
16
0057
16
0058
16
0059
16
005A
16
005B
16
005C
16
005D
16
005E
16
005F
16
0060
16
0061
16
0062
16
0063
16
0064
16
0065
16
0066
16
0067
16
0068
16
0069
16
006A
16
006B
16
006C
16
006D
16
006E
16
006F
16
0070
16
0071
16
0072
16
0073
16
0074
16
0075
16
0076
16
0077
16
0078
16
0079
16
007A
16
007B
16
007C
16
007D
16
007E
16
007F
16
Address
Register
Symbol After
reset
Timer X interrupt control register
TXIC
XXXXX000
2
Timer Y interrupt control register
TYIC
XXXXX000
2
Timer Z interrupt control register
TZIC
XXXXX000
2
Timer C interrupt control register
TCIC
XXXXX000
2
Compare 1 interrupt control register
CMP1IC
XXXXX000
2
Compare 0 interrupt control register
CMP0IC
XXXXX000
2
X : Undefined
NOTES :
1. Blank columns are all reserved space. No access is allowed.
Table 4.2 SFR Information(2)
(1)
Rev.1.40 Sep 30, 2004 page 12 of 26
REJ03B0034-0140Z
R8C/11 Group
4. Special Function Register (SFR)
0080
16
0081
16
0082
16
0083
16
0084
16
0085
16
0086
16
0087
16
0088
16
0089
16
008A
16
008B
16
008C
16
008D
16
008E
16
008F
16
0090
16
0091
16
0092
16
0093
16
0094
16
0095
16
0096
16
0097
16
0098
16
0099
16
009A
16
009B
16
009C
16
009D
16
009E
16
009F
16
00A0
16
00A1
16
00A2
16
00A3
16
00A4
16
00A5
16
00A6
16
00A7
16
00A8
16
00A9
16
00AA
16
00AB
16
00AC
16
00AD
16
00AE
16
00AF
16
00B0
16
00B1
16
00B2
16
00B3
16
00B4
16
00B5
16
00B6
16
00B7
16
00B8
16
00B9
16
00BA
16
00BB
16
00BC
16
00BD
16
00BE
16
00BF
16
Timer X register
TX
FF
16
Timer Y secondary
TYSC
FF
16
External input enable register
INTEN
00
16
Prescaler Y
PREY
FF
16
UART0 transmit/receive mode register
U0MR
00
16
UART0 transmit buffer register
U0TB
XX
16
XX
16
UART0 receive buffer register
U0RB
XX
16
XX
16
UART1 transmit/receive mode register
U1MR
00
16
UART1 transmit buffer register
U1TB
XX
16
XX
16
UART1 receive buffer register
U1RB
XX
16
XX
16
UART0 bit rate register
U0BRG
XX
16
UART0 transmit/receive control register 0
U0C0
00001000
2
UART0 transmit/receive control register 1
U0C1
00000010
2
UART1 bit rate register
U1BRG
XX
16
UART1 transmit/receive control register 0
U1C0
00001000
2
UART1 transmit/receive control register 1
U1C1
00000010
2
UART transmit/receive control register 2
UCON
00
16
Address
Register
Symbol After
reset
Timer Y, Z mode register
TYZMR
00
16
Timer Y primary
TYPR
FF
16
Timer Y, Z waveform output control register
PUM
00
16
Prescaler Z
PREZ
FF
16
Timer Z secondary
TZSC
FF
16
Timer Y, Z output control register
TYZOC
00
16
Timer X mode register
TXMR
00
16
Prescaler X
PREX
FF
16
Timer count source setting register
TCSS
00
16
Timer C register
TC
00
16
00
16
Key input enable register
KIEN
00
16
Timer C control register 0
TCC0
00
16
Timer C control register 1
TCC1
00
16
Capture, compare 0 register
TM0
FF
16
FF
16
Compare 1 register
TM1
FF
16
FF
16
X : Undefined
NOTES :
1. Blank columns are all reserved space. No access is allowed.
Timer Z primary
TZPR
FF
16
Table 4.3 SFR Information(3)
(1)
Rev.1.40 Sep 30, 2004 page 13 of 26
REJ03B0034-0140Z
R8C/11 Group
4. Special Function Register (SFR)
00C0
16
00C1
16
00C2
16
00C3
16
00C4
16
00C5
16
00C6
16
00C7
16
00C8
16
00C9
16
00CA
16
00CB
16
00CC
16
00CD
16
00CE
16
00CF
16
00D0
16
00D1
16
00D2
16
00D3
16
00D4
16
00D5
16
00D6
16
00D7
16
00D8
16
00D9
16
00DA
16
00DB
16
00DC
16
00DD
16
00DE
16
00DF
16
00E0
16
00E1
16
00E2
16
00E3
16
00E4
16
00E5
16
00E6
16
00E7
16
00E8
16
00E9
16
00EA
16
00EB
16
00EC
16
00ED
16
00EE
16
00EF
16
00F0
16
00F1
16
00F2
16
00F3
16
00F4
16
00F5
16
00F6
16
00F7
16
00F8
16
00F9
16
03FA
16
00FB
16
00FC
16
00FD
16
00FE
16
00FF
16
01B3
16
01B4
16
01B5
16
01B6
16
01B7
16
A/D register
AD
XX
16
XX
16
A/D control register 0
ADCON0
00000XXX
2
A/D control register 2
ADCON2
00
16
A/D control register 1
ADCON1
00
16
Port P0 register
P0
XX
16
Port P0 direction register
PD0
00
16
Port P1 register
P1
XX
16
Port P1 direction register
PD1
00
16
Port P3 register
P3
XX
16
Port P3 direction register
PD3
00
16
Port P4 register
P4
XX
16
Port P4 direction register
PD4
00
16
Pull-up control register 0
PUR0
00XX0000
2
Port P1 drive capacity control register
DRR
00
16
Register
Symbol After
reset
Address
Pull-up control register 1
PUR1
XXXXXX0X
2
Flash memory control register 1
FMR1
0100XX0X
2
Flash memory control register 0
FMR0
00000001
2
Timer C output control register
TCOUT
00
16
Flash memory control register 4
FMR4
01000000
2
X : Undefined
NOTES :
1. The blank areas, 0100
16
to 01B2
16
and 01B8
16
to 02FF
16
are reserved and cannot be used by users.
Table 4.4 SFR Information(4)
(1)
Rev.1.40 Sep 30, 2004 page 14 of 26
REJ09B0034-0140Z
R8C/11 Group
5. Electrical Characteristics
5. Electrical Characteristics
Operating ambient temperature
Parameter
Unit
Supply voltage
Output voltage
V
O
P
d
Power dissipation
Storage temperature
Rated value
V
V
Condition
V
CC
T
stg
T
opr
Symbol
mW
V
CC
=AV
CC
V
AV
CC
V
-0.3 to 6.5
-65 to 150
300
-20 to 85 / -40 to 85 (D version)
C
Topr=25 C
Analog supply voltage
V
CC
=AV
CC
-0.3 to 6.5
V
I
Input voltage
-0.3 to V
CC
+0.3
-0.3 to V
CC
+0.3
C
Table 5.1 Absolute Maximum Ratings
Table 5.2 Recommended Operating Conditions
2
.
7
5
.
5
Typ.
M
a
x
.
Unit
P
a
r
a
m
e
t
e
r
V
C
C
S
u
p
p
l
y
v
o
l
t
a
g
e
S
y
m
b
o
l
M
i
n
.
S
t
a
n
d
a
r
d
A
n
a
l
o
g
s
u
p
p
l
y
v
o
l
t
a
g
e
V
C
C3
A
V
c
c
V
V
0
0
A
n
a
l
o
g
s
u
p
p
l
y
v
o
l
t
a
g
e
S
u
p
p
l
y
v
o
l
t
a
g
e
V
I
H
V
s
s
A
V
s
s
0
.
8
V
C
C
V
V
V
CC
0.2V
CC
"
L
"
i
n
p
u
t
v
o
l
t
a
g
e
"
H
"
i
n
p
u
t
v
o
l
t
a
g
e
V
f
(X
IN
)
Main clock input oscillation frequency
V
V
I
L
10
3
.
0V
V
c
c
5
.
5
V
2
.
7
V
V
c
c
<
3
.
0
V
M
H
z
M
H
z
Note
1: Referenced to V
CC
= AV
CC
= 2.7 to 5.5V at Topr = -20 to 85
C / -40 to 85
C unless otherwise specified.
2: The mean output current is the mean value within 100ms.
3: Hold Vcc=AVcc.
0
I
OH (sum)
"H" peak all
output currents
C
o
n
d
i
t
i
o
n
s
Sum of all pins' IOH
(peak)
-60.0
mA
I
O
H
(
p
e
a
k
)
"
H
"
p
e
a
k
o
u
t
p
u
t
c
u
r
r
e
n
t
-10.0
mA
I
OH (avg)
"
H
"
a
v
e
r
a
g
e
o
u
t
p
u
t
c
u
r
r
e
n
t
-
5
.
0
m
A
I
OL (sum)
"
L
"
p
e
a
k
a
l
l
o
u
t
p
u
t
c
u
r
r
e
n
t
s
Sum of all pins' IOL
(peak)
60
m
A
I
OL (peak)
"L" peak output
current
Except P1
0
to P1
7
P1
0
to P1
7
10
m
A
Drive capacity HIGH
Drive capacity LOW
30
10
mA
m
A
I
O
L
(
a
v
g
)
"L" average
output current
Except P1
0
to P1
7
P1
0
to P1
7
Drive capacity HIGH
Drive capacity LOW
5
1
5
5
m
A
m
A
m
A
0
0
20
Rev.1.00 Sep 17, 2004 page 15 of 26
REJ09B0062-0100Z
R8C/11 Group
5. Electrical Characteristics
Table 5.3 A/D Conversion Characteristics
Standard
Min.
Typ. Max.
Resolution
Bit
V
ref
=V
CC
10
Symbol Parameter
Measuring
condition
Unit
LSB
3
R
LADDER
t
CONV
Ladder resistance
Conversion time
Reference voltage
Analog input voltage
V
V
IA
V
REF
0
V
ref
Note
1: Referenced to V
CC
=AV
CC
=2.7 to 5.5V at Topr = -20 to 85 C / -40 to 85 C unless otherwise specified.
2: When f
AD
is 10 MHz more, divide the f
AD
and make A/D operation clock frequency (
AD)
lower than
10 MHz.
3: When the Vcc is less than 4.2V, divide the f
AD
and make A/D operation clock frequency (
AD)
lower than f
AD
/2.
4: Hold Vcc=Vref.
f(XIN)=AD=10 MHz, Vref=Vcc=5.0V
V
REF
=V
CC
Absolute
accuracy
10 bit mode
8 bit mode
f(XIN)=AD=10 MHz, Vref=Vcc=5.0V
2
LSB
10 bit mode
8 bit mode
f(XIN)=AD=10 MHz, Vref=Vcc=3.3V
5
LSB
f(XIN)=AD=10 MHz, Vref=Vcc=3.3V
2
LSB
10
40
k
10 bit mode
8 bit mode
f(XIN)=AD=10 MHz, Vref=Vcc=5.0V
f(XIN)=AD=10 MHz, Vref=Vcc=5.0V
3.3
2.8
s
s
V
A/D operation
clock frequency
2
Without sample & hold
With sample & hold
0.25
10
MHz
1.0
10
MHz
V
CC
4
P0
P1
P2
P3
P4
30pF
Figure 5.1 Port P0 to P4 measurement circuit
Rev.1.40 Sep 30, 2004 page 16 of 26
REJ09B0034-0140Z
R8C/11 Group
5. Electrical Characteristics
Byte program time
Block erase time
Program, Erase voltage
Read voltage
50
0.4
s
Parameter
Standard
Min.
Typ.
Max
Unit
Note
1: Referenced to V
CC1
=AVcc=2.7 to 5.5V at Topr = 0 to 60 C unless otherwise specified.
Measuring condition
Symbol
Program, Erase temperature
2.7
2.7
0
400
9
5.5
5.5
60
s
V
V
C
Time delay from suspend request until erase
suspend
td(SR-ES)
Program/erase cycle
8
ms
100
cycle
Vcc=5.0V, Topr=25 C
Vcc=5.0V, Topr=25 C
Data-retention duration
Topr=55 C
20
year
Table 5.4 Flash Memory Version Electrical Characteristics
Table 5.5 Voltage Detection Circuit Electrical Characteristics
Symbol
Standard
Typ.
Unit
Measuring condition
Min.
Max.
Parameter
Vdet
Voltage detection level
V
3.8
4.3
NOTES:
1. The measuring condition is Vcc=AVcc=2.7V to 5.5V and Topr= -40C to 85 C.
2. This shows the time until the voltage detection interrupt request is generated since the voltage passes Vdet.
3. This shows the required time until the voltage detection circuit operates when setting to "1" again after setting the VC27 bit in the VCR2
register to "0"
Voltage detection interrupt request generating time
2
40
nA
Voltage detection circuit self consumption current
Waiting time till voltage detection circuit operation starts
3
td(E-A)
VC27=1, VCC=5.0V
3.3
20
600
s
s
Vccmin
Minimum value of microcomputer operation voltage
2.7
V
FMR46
Erase-suspend request
(interrupt request)
t
d(SR-ES)
Figure 5.2 Time delay from Suspend Request until Erase Suspend
Rev.1.00 Sep 17, 2004 page 17 of 26
REJ09B0062-0100Z
R8C/11 Group
5. Electrical Characteristics
Symbol
Standard
Typ.
Unit
Measuring condition
Min.
Max.
Parameter
Power-on reset valid voltage
NOTES:
1. The voltage detection circuit which is embedded in a microcomputer is a factor to generate the hardware reset 2. Refer to 5.1.2 Hardware
Reset 2 of Hardware Manual.
2. This condition is not applicable when using with Vcc
1.0V.
3. When turning power on after the time to hold the external power below effective voltage exceeds 10s, refer to Table 16.8 Reset Circuit
Electrical Characteristics (When Not Using Voltage Moitor 1 Reset).
s
Supply voltage rising time when power-on reset is canceled
2
V
ms
Vpor2
t
w(Vpor2-
Vdet)
Vdet
0
t
w(por2)
Time to hold external power below valid voltage
100
Figure 5.3 Reset Circuit Electrical Characteristics
V
por1
V
cc min
V
det3
V
det3
t
w(por1)
t
w(Vpor1Vdet)
Sampling time1,2
Internal reset signal
("L" effective)
f
RING-S
1
X 32
f
RING-S
1
X 32
V
por2
NOTES:
1. Hold the voltage of the microcomputer operation voltage range (Vccmin or above) within sampling time.
2. A sampling clock is selectable. Refer to "5.4 Voltage Detection Circuit" of Hardware Manual for details.
3. V
det
shows the voltage detection level of the voltage detection circuit. Refer to "5.4 Voltage Detection Circuit"
of Hardware Manual for details.
t
w(por2)
t
w(Vpor2 Vdet)
Symbol
Standard
Typ.
Unit
Measuring condition
Min.
Max.
Parameter
Power-on reset valid voltage
NOTES:
1. When not the sing hardware reset 2, use with Vcc
2.7V.
Time to hold external power on below valid voltage
s
Supply voltage rising time when power-on reset is canceled
100
-20C
Topr
0C
V
ms
Vpor1
t
w(Vpor1-
Vdet)
t
w(por1)
Time to hold external power on below valid voltage
Time to hold external power on below valid voltage
0.1
0.5
1
t
w(Vpor1-
Vdet)
t
w(por1)
t
w(Vpor1-
Vdet)
t
w(por1)
t
w(Vpor1-
Vdet)
t
w(por1)
Supply voltage rising time when power-on reset is canceled
Supply voltage rising time when power-on reset is canceled
Time to hold external power on below valid voltage
Supply voltage rising time when power-on reset is canceled
0C
Topr
85C
0C
Topr
85C
-20C
Topr
0C
-20C
Topr
0C
-20C
Topr
0C
0C
Topr
85C
0C
Topr
85C
10
30
10
1
100
ms
ms
ms
s
s
s
Table 5.6 Reset Circuit Electrical Characteristics (When Using Hardware Reset 2)
Table 5.7 Reset Circuit Electrical Characteristics (When Not Using Hardware Reset 2)
Rev.1.40 Sep 30, 2004 page 18 of 26
REJ09B0034-0140Z
R8C/11 Group
5. Electrical Characteristics
Table 5.10 Electrical Characteristics (1) [Vcc=5V]
Symbol
V
OH
V
OL
"L" output voltage
"H" output voltage
Standard
Typ.
Unit
Measuring condition
V
V
V
Min.
Max.
V
CC
-
2.0
Parameter
I
OH
=
-
5mA
V
Hysteresis
"H" input current
I
IH
"L" input current
I
IL
V
RAM
RAM retention voltage
V
T+-
V
T-
0.2
V
A
At stop mode
2.0
V
I
=5V
V
I
=0V
R
fXIN
Feedback resistance
X
IN
M
R
PULLUP
Pull-up resistance
167
k
30
125
Note
1 : Referenced to V
CC
=AV
CC
=4.2 to 5.5V at Topr = -20 to 85 C / -40 to 85 C, f(BCLK)=20MHz unless otherwise specified.
V
CC
Except X
OUT
X
OUT
I
OH
=
-
200A
Drive ability HIGH
Drive ability LOW
V
CC
-
0.3
V
CC
V
I
OH
=
-
1 mA
V
CC
-
2.0
V
CC
-
2.0
I
OH
=
-
500A
V
V
V
CC
V
CC
P1
0
to P1
7
Except X
OUT
P1
0
to P1
7
X
OUT
Drive capacity HIGH
Drive capacity LOW
I
OH
= 5 mA
I
OH
= 200 A
I
OL
= 15 mA
I
OL
=
5 mA
2.0
0.45
V
2.0
2.0
V
Drive capacity HIGH
Drive capacity LOW
I
OL
=
1 mA
I
OL
=500 A
2.0
2.0
V
RESET
0.2
1.0
2.2
V
5.0
-
5.0
A
V
I
=0V
50
1.0
f
RING-S
Low-speed on-chip oscillator frequency
40
250
kHz
INT
0
, INT
1
, INT
2
, INT
3
, KI
0
, KI
1
,
KI
2
, KI
3
, CNTRo, CNTR
1
, TC
IN
,
RxD
0
, RxD
1
Drive capacity LOW
I
OL
= 200 A
0.45
V
V
Symbol
Standard
Typ.
Unit
Measuring condition
Min.
Max.
Parameter
High-speed on-chip oscillator frequency 1 / {td(HRoffset)+td(HR)} when the
reset is released
NOTES:
1. The measuring condition is Vcc=AVcc=5.0 V and Topr=25 C.
High-speed on-chip oscillator period adjusted unit
MHz
ns
VCC=5.0V, Topr=25 C
Set "00
16
" in the HR1 register
8
61
Differences when setting "01
16
" and "00
16
"
in the HR register
Settable high-speed on-chip oscillator minimum period
High-speed on-chip oscillator temperature dependence(1)
td(HRoffset)
td(HR)
VCC=5.0V, Topr=25 C
Set "40
16
" in the HR1 register
1
ns
Frequency fluctuation in temperature range
of -10 C to 50 C
5
%
%
High-speed on-chip oscillator temperature dependence(2)
Frequency fluctuation in temperature range
of -40 C to 85 C
10
6
10
Table 5.8 High-speed On-Chip Oscillator Circuit Electrical Characteristics
Symbol
Standard
Typ.
Unit
Measuring condition
Min.
Max.
Parameter
2
Note
1: The measuring condition is Vcc=AVcc=2.7 to 5.5 V and Topr=25 C.
2: This shows the wait time until the internal power supply generating circuit is stabilized during power-on.
3: This shows the time until BCLK starts from the interrupt acknowledgement to cancel stop mode.
150
td(R-S)
STOP release time
3
ms
td(P-R)
Time for internal power supply stabilization during powering-on
2
s
Table 5.9 Power Circuit Timing Characteristics
Rev.1.00 Sep 17, 2004 page 19 of 26
REJ09B0062-0100Z
R8C/11 Group
5. Electrical Characteristics
Symbol
Standard
Typ.
Unit
Measuring condition
Min. Max.
Parameter
No division
mA
In single-chip mode, the output
pins are open and other pins
are V
SS
9
15
X
IN
=20 MHz (square wave)
mA
High-speed
mode
I
CC
Power supply current
(V
CC
=3.3 to 5.5V)
470
NOTES
1: The power supply current measuring is executed using the measuring program on frash memory.
2: Timer Y is operated with timer mode.
mA
Medium-speed
mode
High-speed
on-chip oscillator
mode
Low-speed
on-chip oscillator
mode
High-speed on-chip oscillator off
Low-speed on-chip oscillator on=125 kHz
X
IN
=16 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on=125 kHz
No division
8
X
IN
=20 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on=125 kHz
Division by 8
4
X
IN
=16 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on=125 kHz
Division by 8
3
mA
Main clock off
High-speed on-chip oscillator on=8 MHz
Low-speed on-chip oscillator on=125 kHz
No division
4
8
mA
Main clock off
Low-speed on-chip oscillator on=125 kHz
Division by 8
mA
1.5
Main clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on=125 kHz
High-speed on-chip oscillator on=8 MHz
mA
X
IN
=10 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on=125 kHz
No division
5
X
IN
=10 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on=125 kHz
Division by 8
2
mA
14
900
Wait mode
A
Division by 8
Main clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on=125 kHz
When a WAIT instruction is executed
2
Peripheral clock operation
40
A
Wait mode
Main clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on=125 kHz
When a WAIT instruction is executed
2
Peripheral clock off
38
76
80
A
Stop mode
Main clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10="1"
Peripheral clock off
0.8
3.0
VC27="0"
VC27="0"
VC27="0"
A
Table 5.11 Electrical Characteristics (2) [Vcc=5V]
Rev.1.40 Sep 30, 2004 page 20 of 26
REJ09B0034-0140Z
R8C/11 Group
5. Electrical Characteristics
Timing requirements (Unless otherwise noted: V
CC
= 5V, V
SS
= 0V at Ta = 25 C) [V
CC
=5V]
Table 5.12 X
IN
input
________
Table 5.13 CNTR0 input, CNTR1 input, INT2 input
________
Table 5.14 TCIN input, INT3 input
Table 5.15 Serial Interface
________
Table 5.16 External interrupt INT0 input
Symbol
t
C
(X
IN
)
t
WH
(X
IN
)
t
WL
(X
IN
)
Parameter
X
IN
input cycle time
X
IN
input HIGH pulse width
X
IN
input LOW pulse width
Min.
50
25
25
Max.
Unit
ns
ns
ns
Standard
Symbol
t
C
(
CNTR0
)
t
WH
(
CNTR0
)
t
WL
(
CNTR0
)
Parameter
CNTR0 input cycle time
CNTR0 input HIGH pulse width
CNTR0 input LOW pulse width
Min.
100
40
40
Max.
Unit
ns
ns
ns
Standard
Symbol
t
C
(
TCIN
)
t
WH
(
TCIN
)
t
WL
(
TCIN
)
Parameter
TCIN input cycle time
TCIN input HIGH pulse width
TCIN input LOW pulse width
Min.
400
(1)
200
(2)
200
(2)
Max.
Unit
ns
ns
ns
Standard
NOTES
1 :When using the Timer C input capture mode, adjust the cycle time above ( 1/ Timer C count source
frequency x 3).
2 : When using the Timer C input capture mode, adjust the pulse width above ( 1/ Timer C count source
frequency x 1.5).
NOTES
________
________
1 : When selecting the digital filter by the INT0 input filter select bit, use the INT0 input HIGH pulse width
to the greater value,either ( 1/ digital filter clock frequency x 3) or the minimum value of standard.
________
________
2 : When selecting the digital filter by the INT0 input filter select bit, use the INT0 input LOW pusle width
to the greater value,either ( 1/ digital filter clock frequency x 3) or the minimum value of standard.
Symbol
t
C
(
CK
)
t
W
(
CKH
)
t
W
(
CKL
)
t
d
(
C-Q
)
t
h
(
C-Q
)
t
su
(
D-C
)
t
h
(
C-D
)
Parameter
CLKi input cycle time
CLKi input HIGH pulse width
CLKi input LOW pulse width
TxDi output delay time
TxDi hold time
RxDi input setup time
RxDi input hold time
Min.
200
100
100
0
35
90
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
Standard
80
Symbol
t
W
(
INH
)
t
W
(
INL
)
Parameter
________
INT0 input HIGH pulse width
________
INT0 input LOW pulse width
Min.
250
(1)
250
(2)
Max.
Unit
ns
ns
Standard
Rev.1.00 Sep 17, 2004 page 21 of 26
REJ09B0062-0100Z
R8C/11 Group
5. Electrical Characteristics
Figure 5.4 Vcc=5V timing diagram
CLK
i
TxD
i
RxD
i
INT
i
t
W(CKH)
t
c(CK)
t
W(CKL)
t
h(C-Q)
t
h(C-D)
t
su(D-C)
t
d(C-Q)
t
W(INL)
t
W(INH)
X
IN
input
t
WH(XIN)
t
c(XIN)
t
WL(XIN)
TCIN input
t
WH(TCIN)
t
c(TCIN)
t
WL(TCIN)
CNTR0 input
t
WH(CNTR0)
t
c(CNTR0)
t
WL(CNTR0)
V
CC
= 5V
Rev.1.40 Sep 30, 2004 page 22 of 26
REJ09B0034-0140Z
R8C/11 Group
5. Electrical Characteristics
Symbol
V
OH
V
OL
"L" output voltage
"H" output voltage
Standard
Typ.
Unit
Measuring condition
V
V
V
Min.
Max.
V
CC
-
0.5
Parameter
I
OH
=
-
1mA
V
Hysteresis
"H" input current
I
IH
"L" input current
I
IL
V
RAM
RAM retention voltage
V
T+-
V
T-
0.2
V
A
At stop mode
2.0
V
I
=3V
R
fXIN
Feedback resistance
X
IN
M
R
PULLUP
Pull-up resistance
k
66
125
Note
1 : Referenced to V
CC
=AV
CC
=2.7 to 3.3V at Topr = -20 to 85 C / -40 to 85 C, f(BCLK)=10MHz unless otherwise specified.
V
CC
Except X
OUT
X
OUT
Drive capacity HIGH
Drive capacity LOW
I
OH
=
-
0.1 mA
V
CC
-
0.5
V
CC
-
0.5
I
OH
=
-
50 A
V
V
V
CC
V
CC
P1
0
to P1
7
Except X
OUT
P1
0
to P1
7
X
OUT
Drive capacity HIGH
Drive capacity LOW
I
OH
= 1 mA
I
OL
= 2 mA
I
OL
=
1 mA
0.5
V
0.5
0.5
V
Drive capacity HIGH
Drive capacity LOW
I
OL
=
0.1 mA
I
OL
=50 A
0.5
0.5
V
INT
0
, INT
1
, INT
2
, INT
3
, KI
0
, KI
1
,
KI
2
, KI
3
, CNTRo, CNTR
1
, TC
IN
,
RxD
0
, RxD
1
RESET
0.2
0.8
1.8
V
4.0
-
4.0
A
V
I
=0V
160
3.0
f
RING-S
Low-speed on-chip oscillator frequency
40
250
kHz
V
I
=0V
500
Table 5.17 Electrical Characteristics (3) [Vcc=3V]
Rev.1.00 Sep 17, 2004 page 23 of 26
REJ09B0062-0100Z
R8C/11 Group
5. Electrical Characteristics
Table 5.18 Electrical Characteristics (4) [Vcc=3V]
Symbol
Standard
Typ.
Unit
Measuring condition
Min. Max.
Parameter
No division
mA
In single-chip mode, the output
pins are open and other pins
are V
SS
8
13
X
IN
=20 MHz (square wave)
mA
High-speed
mode
I
CC
Power supply current
(V
CC
=2.7 to 3.3V)
420
Note
1: The power supply current measuring is executed using the measuring program on frash memory.
2: Timer Y is operated with timer mode.
Wait mode
A
A
mA
Medium-speed
mode
High-speed
on-chip oscillator
mode
Low-speed
on-chip oscillator
mode
High-speed on-chip oscillator off
Low-speed on-chip oscillator on=125 kHz
X
IN
=16 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on=125 kHz
No division
7
X
IN
=20 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on=125 kHz
Division by 8
3
X
IN
=16 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on=125 kHz
Division by 8
2.5
mA
Main clock off
High-speed on-chip oscillator on=8 MHz
Low-speed on-chip oscillator on=125 kHz
No division
3.5
7.5
mA
Main clock off
Low-speed on-chip oscillator on=125 kHz
Division by 8
mA
1.5
Main clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on=125 kHz
Division by 8
Main clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on=125 kHz
When a WAIT instruction is executed
2
Peripheral clock operation
37
High-speed on-chip oscillator on=8 MHz
mA
X
IN
=10 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on=125 kHz
No division
5
X
IN
=10 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on=125 kHz
Division by 8
1.6
mA
12
800
A
Wait mode
Main clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on=125 kHz
When a WAIT instruction is executed
2
Peripheral clock off
35
70
74
Stop mode
Main clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10="1"
Peripheral clock off
0.7
3.0
VC27="0"
VC27="0"
VC27="0"
A
Rev.1.40 Sep 30, 2004 page 24 of 26
REJ09B0034-0140Z
R8C/11 Group
5. Electrical Characteristics
Timing requirements (Unless otherwise noted: V
CC
= 3V, V
SS
= 0V at Ta = 25 C) [V
CC
=3V]
Table 5.19 X
IN
input
________
Table 5.20 CNTR0 input, CNTR1 input, INT2 input
________
Table 5.21 TCIN input, INT3 input
Table 5.22 Serial Interface
________
Table 5.23 External interrupt INT0 input
Symbol
t
C
(X
IN
)
t
WH
(X
IN
)
t
WL
(X
IN
)
Parameter
X
IN
input cycle time
X
IN
input HIGH pulse width
X
IN
input LOW pulse width
Min.
100
40
40
Max.
Unit
ns
ns
ns
Standard
Symbol
t
C
(
CNTR0
)
t
WH
(
CNTR0
)
t
WL
(
CNTR0
)
Parameter
CNTR0 input cycle time
CNTR0 input HIGH pulse width
CNTR0 input LOW pulse width
Min.
300
120
120
Max.
Unit
ns
ns
ns
Standard
Symbol
t
C
(
TCIN
)
t
WH
(
TCIN
)
t
WL
(
TCIN
)
Parameter
TCIN input cycle time
TCIN input HIGH pulse width
TCIN input LOW pulse width
Min.
1200
(1)
600
(2)
600
(2)
Max.
Unit
ns
ns
ns
Standard
NOTES
1 :When using the Timer C input capture mode, adjust the cycle time above ( 1/ Timer C count source
frequency x 3).
2 : When using the Timer C input capture mode, adjust the pulse width above ( 1/ Timer C count source
frequency x 1.5).
NOTES
________
________
1 : When selecting the digital filter by the INT0 input filter select bit, use the INT0 input HIGH pulse width
to the greater value,either ( 1/ digital filter clock frequency x 3) or the minimum value of standard.
________
________
2 : When selecting the digital filter by the INT0 input filter select bit, use the INT0 input LOW pusle width
to the greater value,either ( 1/ digital filter clock frequency x 3) or the minimum value of standard.
Symbol
t
C
(
CK
)
t
W
(
CKH
)
t
W
(
CKL
)
t
d
(
C-Q
)
t
h
(
C-Q
)
t
su
(
D-C
)
t
h
(
C-D
)
Parameter
CLKi input cycle time
CLKi input HIGH pulse width
CLKi input LOW pulse width
TxDi output delay time
TxDi hold time
RxDi input setup time
RxDi input hold time
Min.
300
150
150
0
55
90
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
Standard
160
Symbol
t
W
(
INH
)
t
W
(
INL
)
Parameter
________
INT0 input HIGH pulse width
________
INT0 input LOW pulse width
Min.
380
(1)
380
(2)
Max.
Unit
ns
ns
Standard
Rev.1.00 Sep 17, 2004 page 25 of 26
REJ09B0062-0100Z
R8C/11 Group
5. Electrical Characteristics
Figure 5.5 Vcc=3V timing diagram
CLK
i
TxD
i
RxD
i
INT
i
t
W(CKH)
t
c(CK)
t
W(CKL)
t
h(C-Q)
t
h(C-D)
t
su(D-C)
t
d(C-Q)
t
W(INL)
t
W(INH)
X
IN
input
t
WH(XIN)
t
c(XIN)
t
WL(XIN)
TCIN input
t
WH(TCIN)
t
c(TCIN)
t
WL(TCIN)
CNTR0 input
t
WH(CNTR0)
t
c(CNTR0)
t
WL(CNTR0)
V
CC
= 3V
Rev.1.40 Sep 30, 2004 page 26 of 26
REJ03B0034-0140Z
R8C/11 Group
Package Dimensions
Package Dimensions
LQFP32-P-0707-0.80
Weight(g)
--
JEDEC Code
EIAJ Package Code
Lead Material
Cu Alloy
32P6U-A
Plastic 32pin 7
7mm body LQFP
--
0.1
--
--
--
0.2
--
--
--
--
--
--
--
--
--
Symbol
Min
Nom
Max
A
A
2
b
c
D
E
H
E
L
L
1
y
b
2
Dimension in Millimeters
H
D
A
1
--
--
I
2
1.0
--
--
M
D
--
--
M
E
10
0
0.1
1.0
0.7
0.2
0.5
0.3
0.8
6.9
7.0
7.1
6.9
7.0
7.1
8.8
9.0
9.2
8.8
9.0
9.2
0.175
0.125
0.105
0.45
0.37
0.32
1.4
0
1.7
e
Lp
0.45
--
--
0.6
0.5
7.4
7.4
0.25
--
0.75
--
x
A3
Recommended Mount Pad
Detail F
A
E
H
E
H
D
D
1
8
24
17
25
32
16
9
M
D
b
2
M
E
e
F
e
y
b
x
M
A
1
A
2
L
L
1
Lp
A3
c
I
2
REVISION HISTORY
R8C/11 Group Datasheet
Rev.
Date
Description
Page
Summary
A-1
1.00
Jun. 19, 2003
First edition issued
1.10
Sep. 08, 2003
Table 1.1: Shortest instruction execution time and f(X
IN
) changed
____________
Figure 1.3: Pin name changed from TX
OUT
to CNTR
0
____________
Table 1.3: Pin name changed from TX
OUT
to CNTR
0
The value of HR1 register after reset changed
The value of TC register after reset changed
Chapter "5. Electrical Characteristics" added
2
5
6
10
12
14
1.20
Oct. 31, 2003
Table 1.1: Power consumption values added
Table 1.3: Resistor value for CNVss and MODE deleted
Register name of address 0050
16
modified from CMP2IC to CMP1IC, register name
of address 005C
16
modified from CMP1IC to CMP0IC
Table 5.2: Note 3 and Note 4 deleted
t
samp
in Table 5.3 deleted
Figure 5.1 added
Table 5.10: Vcc changed from "4.2 to 5.5V" to "3.3V to 5.5V", low-power ring oscil-
lator changed from "on 100kHz" to "125kHz", X
IN
=5MHz deleted and X
IN
=10MHz
added in high-speed mode and medium-speed mode, VC27="0" added in stop
mode measuring condition, data added and modified
Table 11 to Table 15 added
Figure 5.2 added
Table 5.16: Note 1, f
(BCLK)
=5 MHz changed to 10 MHz
Table 5.17: low-power ring oscillator changed from "on 100kHz" to "125kHz",
X
IN
=5MHz deleted and X
IN
=10MHz added in high-speed mode and medium-speed
mode, VC27="0" added in stop mode measuring condition, data added and modi-
fied
Table 5.18 to Table 5.22 added
Figure 5.3 added
2
6
11
14
15
17
19
20
21
22
23
24
25
1.30
Dec 05, 2003
4
Table 1.2 : ** deleted
15 Table 5.4 revised
1.40
Sep 30, 2004
all pages
Words standardized (on-chip oscillator, serial interface, A/D)
2
Table 1.1 revised
5
Figure 1.3, NOTES 3 added
6
Table 1.3 revised
9
Figure 3.1, NOTES added
10-13
One body sentence in chapter 4 added ; Title of Table 4.1 to 4.4 added
12
Table 4.3 revised ; Table 4.4 revised
14
Table 5.2 revised
15
Table 5.3 revised
16
Table 5.4 revised ; Table 16.5 revised
17
Table 5.6, 5.7 adn 5.8 revised ; Figure 5.3 revised
18
Table 5.9 revised ; Table 5.10 revised
REVISION HISTORY
R8C/11 Group Datasheet
Rev.
Date
Description
Page
Summary
A-2
1.40
Sep 30, 2004
20
Table 5.12 revised ; Table 5.16 revised
22
Table 16.17 revised
24
Table 16.19 revised
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