Rev.0.20
Mar 8, 2005
Page 1 of 22
REJ03B0117-0020
PRELIMINARY
R8C/24, R8C/25 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Notice: This is not a final specification.
Some parametric limits are subject to change.
1.
Overview
This MCU is built using the high-performance silicon gate CMOS process using the R8C/Tiny Series CPU
core and is packaged in a 52-pin plastic molded LQFP. This MCU operates using sophisticated instructions
featuring a high level of instruction efficiency. With 1 Mbyte of address space, it is capable of executing
instructions at high speed.
Furthermore, the data flash ROM (1KB x 2blocks) is embedded in the R8C/25 group.
The difference between R8C/24 and R8C/25 groups is only the existence of the data flash ROM. Their
peripheral functions are the same.
1.1
Applications
Electric household appliance, office equipment, audio, consumer products, etc.
REJ03B0117-0020
Rev.0.20
Mar 8, 2005
Rev.0.20
Mar 8, 2005
Page 2 of 22
REJ03B0117-0020
Under development
R8C/24, R8C/25 Group
1. Overview
Preliminary specification
Specifications in this manual are tentative and subject to change.
1.2
Performance Overview
Table 1.1 lists the R8C/24 Group Performance. Table 1.2 lists the R8C/25 Group Performance.
NOTES:
1. I
2
C bus is a trademark of Koninklijke Philips Electronics N. V.
2. Specify the D version when using it.
Table 1.1
R8C/24 Group Performance
Item
Performance
CPU
Number of Basic Instructions
89 instructions
Minimum Instruction Execution
Time
50ns (f(XIN)=20MHz, VCC=3.0 to 5.5V)
100ns (f(XIN)=10MHz, VCC=2.7 to 5.5V)
TBD(f(XIN)=TBD, VCC=2.2 to 5.5V)
Operating Mode
Single-chip
Memory Space
1 Mbyte
Memory Capacity
See Table 1.3 Product Information of R8C/24 Group
Peripheral
Function
Port
I/O port: 41 pins, Input port: 3 pins
LED Drive Port
I/O port: 8 pins
Timer
Timer RA: 8 bits 1 channel, Timer RB: 8 bits 1
channel (Each timer equipped with 8-bit prescaler)
Timer RD: 16 bits 2 channel
(Circuits of input capture and output compare)
Timer RE:
(With real-time clock and compare match function)
Serial Interface
1 channel
Clock synchronous, UART
1 channel
UART
1 channel
I
2
C Bus Interface (IIC)
(1)
Chip-select clock synchronous (SSU)
LIN Module
Hardware LIN: 1 channel (Timer RA, UART)
A/D Converter
10-bit A/D converter: 1 circuit, 12 channels
Watchdog Timer
15 bits 1 channel (with prescaler)
Reset start selectable
Interrupt
Internal: 11 factors, External: 5 factors, Software: 4 factors,
Priority level: 7 levels
Clock Generation Circuit
3 circuits
XIN clock generation circuit (Equipped with a built-in
feedback resistor)
On-chip oscillator (High speed, low speed)
Equipped with frequency adjustment function on high
speed on-chip oscillator
XCIN clock generation circuit (32 kHz)
Oscillation Stop Detection Function XIN clock oscillation stop detection function
Voltage Detection Circuit
Included
Power-On Reset Circuit
Included
Electric
Characteristics
Supply Voltage
VCC=3.0 to 5.5V (f(XIN)=20MHz)
VCC=2.7 to 5.5V (f(XIN)=10MHz)
VCC=2.2 to 5.5V (f(XIN)=TBD)
Power Consumption
TBD
Flash Memory Program/Erase Supply Voltage VCC=2.7 to 5.5V
Program/Erase Endurance
100 times
Operating Ambient Temperature
-20 to 85
C
-40 to 85
C (D Version)
(2)
Package
52-pin plastic mold LQFP
Rev.0.20
Mar 8, 2005
Page 3 of 22
REJ03B0117-0020
Under development
R8C/24, R8C/25 Group
1. Overview
Preliminary specification
Specifications in this manual are tentative and subject to change.
Table 1.2
R8C/25 Group Performance
NOTES:
1. I
2
C bus is a trademark of Koninklijke Philips Electronics N. V.
2. Specify the D version when using it.
Item
Performance
CPU
Number of Basic Instructions
89 instructions
Minimum Instruction Execution
Time
50ns (f(XIN)=20MHz, VCC=3.0 to 5.5V)
100ns (f(XIN)=10MHz, VCC=2.7 to 5.5V)
TBD (f(XIN)=TBD, VCC=2.2 to 5.5V)
Operating Mode
Single-chip
Memory Space
1 Mbyte
Memory Capacity
See Table 1.4 Product Information of R8C/25 Group
Peripheral
Function
Port
I/O: 41 pins, Input: 3 pins
LED Drive Port
I/O port: 8 pins
Timer
Timer RA: 8 bits 1 channel, Timer RB: 8 bits 1
channel (Each timer equipped with 8-bit prescaler)
Timer RD: 16 bits 2 channel
(Circuits of input capture and output compare)
Timer RE:
(With real-time clock and compare match function)
Serial Interface
1 channel
Clock synchronous, UART
1 channel
UART
1 channel
I
2
C Bus Interface
(1)
Chip-select clock synchronous (SSU)
LIN Module
Hardware LIN: 1 channel (Timer RA, UART)
A/D Converter
10-bit A/D converter: 1 circuit, 12 channels
Watchdog Timer
15 bits 1 channel (with prescaler)
Reset start selectable
Interrupt
Internal: 11 factors, External: 5 factors, Software: 4 factors,
Priority level: 7 levels
Clock Generation Circuit
3 circuits
XIN clock generation circuit (Equipped with a built-in
feedback resistor)
On-chip oscillator (High speed, low speed)
Equipped with frequency adjustment function on high
speed on-chip oscillator
XCIN clock generation circuit (32 kHz)
Oscillation Stop Detection Function XIN clock oscillation stop detection function
Voltage Detection Circuit
Included
Power-On Reset Circuit
Included
Electric
Characteristics
Supply Voltage
VCC=3.0 to 5.5V (f(XIN)=20MHz)
VCC=2.7 to 5.5V (f(XIN)=10MHz)
VCC=2.2 to 5.5V (f(XIN)=TBD)
Power Consumption
TBD
Flash Memory Program/Erase Supply Voltage VCC=2.7 to 5.5V
Program/Erase Endurance
1,0000 times (Data area)
1,000 times (Program area)
Operating Ambient Temperature
-20 to 85
C
-40 to 85
C (D Version)
(2)
Package
52-pin plastic mold LQFP
Rev.0.20
Mar 8, 2005
Page 4 of 22
REJ03B0117-0020
Under development
R8C/24, R8C/25 Group
1. Overview
Preliminary specification
Specifications in this manual are tentative and subject to change.
1.3
Block Diagram
Figure 1.1 shows a Block Diagram.
Figure 1.1
Block Diagram
R8C/Tiny Series CPU Core
Timer
Timer RA (8 bits)
Timer RB (8 bits)
Timer RD (16 bits
2 channels
)
Timer RE (8 bits)
A/D Converter
(10 bits
12 channels)
System Clock Generation
XIN-XOUT
High-Speed On-Chip Oscillator
Low-Speed On-Chip Oscillator
XCIN-XCOUT
UART or
Clock Synchronous Serial Interface
(8 bits
1 channel)
Memory
Watchdog Timer
(15 bits)
ROM
(1)
RAM
(2)
Multiplier
R0H
R0L
R1H
R2
R3
R1L
A0
A1
FB
SB
USP
ISP
INTB
PC
FLG
I/O port
NOTES:
1. ROM size depends on MCU type.
2. RAM size depends on MCU type.
I
2
C Bus Interface or Chip-select
Clock Synchronous Serial Interface
(8 bits
1 channel)
8
Port P1
6
Port P3
3
3
Port P4
8
Port P0
8
Port P2
8
Port P6
UART
(8 bits
1 channel)
LIN Module
(1 channel)
Rev.0.20
Mar 8, 2005
Page 5 of 22
REJ03B0117-0020
Under development
R8C/24, R8C/25 Group
1. Overview
Preliminary specification
Specifications in this manual are tentative and subject to change.
1.4
Product Information
Table 1.3 lists the Product Information of R8C/24 Group.
Table 1.4 lists the Product Information of R8C/25 Group.
(P): Planning, (D): Under Development
Figure 1.2
Type Number, Memory Size and Package of R8C/24 Group
Table 1.3
Product Information of R8C/24 Group
As of Mar 2005
Type No.
ROM Capacity RAM Capacity
Package Type
Remarks
R5F21244SNFP(D)
16 Kbytes
1 Kbytes
PLQP0052JA-A
Flash Memory
R5F21246SNFP(D)
32 Kbytes
2 Kbytes
PLQP0052JA-A
Version
R5F21247SNFP(P)
48 Kbytes
2.5 Kbytes
PLQP0052JA-A
R5F21248SNFP(P)
64 Kbytes
3 Kbytes
PLQP0052JA-A
R5F21244SDFP(D)
16 Kbytes
1 Kbytes
PLQP0052JA-A
D Version
R5F21246SDFP(D)
32 Kbytes
2 Kbytes
PLQP0052JA-A
R5F21247SDFP(P)
48 Kbytes
2.5 Kbytes
PLQP0052JA-A
R5F21248SDFP(P)
64 Kbytes
3 Kbytes
PLQP0052JA-A
Type No. R 5 F 21 24 6 S N FP
Package Type:
FP: PLQP0052JA-A (0.65 mm pin-pitch, 10 mm square body)
Grouping
N : Operating Ambient Temperature -20 C to 85 C
D : Operating Ambient Temperature -40 C to 85 C
S : Low voltage version
ROM Capacity
4 : 16 KB
6 : 32 KB
7 : 48 KB
8 : 64 KB
R8C/24 Group
R8C/Tiny Series
Memory Type
F : Flash Memory Version
Renesas MCU
Renesas Semiconductors
Rev.0.20
Mar 8, 2005
Page 6 of 22
REJ03B0117-0020
Under development
R8C/24, R8C/25 Group
1. Overview
Preliminary specification
Specifications in this manual are tentative and subject to change.
(P): Planning, (D): Under Development
Figure 1.3
Type Number, Memory Size and Package of R8C/25 Group
Table 1.4
Product Information of R8C/25 Group
As of Mar 2005
Type No.
ROM Capacity
RAM
Capacity
Package Type
Remarks
Program Area
Data Area
R5F21254SNFP(D)
16 Kbytes
1 Kbytes X 2 1 Kbytes
PLQP0052JA-A
Flash Memory
R5F21256SNFP(D)
32 Kbytes
1 Kbytes X 2 2 Kbytes
PLQP0052JA-A
Version
R5F21257SNFP(P)
48 Kbytes
1 Kbytes X 2 2.5 Kbytes
PLQP0052JA-A
R5F21258SNFP(P)
64 Kbytes
1 Kbytes X 2 3 Kbytes
PLQP0052JA-A
R5F21254SDFP(D)
16 Kbytes
1 Kbytes X 2 1 Kbytes
PLQP0052JA-A
D Version
R5F21256SDFP(D)
32 Kbytes
1 Kbytes X 2 2 Kbytes
PLQP0052JA-A
R5F21257SDFP(P)
48 Kbytes
1 Kbytes X 2 2.5 Kbytes
PLQP0052JA-A
R5F21258SDFP(P)
64 Kbytes
1 Kbytes X 2 3 Kbytes
PLQP0052JA-A
Type No. R 5 F 21 25 6 S N FP
Package Type:
FP: PLQP0052JA-A (0.65 mm pin-pitch, 10 mm square body)
Grouping
N : Operating Ambient Temperature -20 C to 85 C
D : Operating Ambient Temperature -40 C to 85 C
S : Low voltage version
ROM Capacity
4 : 16 KB
6 : 32 KB
7 : 48 KB
8 : 64 KB
R8C/25 Group
R8C/Tiny Series
Memory Type
F : Flash Memory Version
Renesas MCU
Renesas Semiconductors
Rev.0.20
Mar 8, 2005
Page 7 of 22
REJ03B0117-0020
Under development
R8C/24, R8C/25 Group
1. Overview
Preliminary specification
Specifications in this manual are tentative and subject to change.
1.5
Pin Assignment
Figure 1.4 shows the Pin Assignment (top view).
Figure 1.4
Pin Assignment (top view)
52
P3_7/SSO
Pin Assignment (top view)
R8C/24, R8C/25 Group
51
P0_0/AN7
50
P0_1/AN6
49
P0_2/AN5
48
P0_3/AN4
47
P6_1
46
P6_2
45
P6_0/TREO
44
P4_2/VREF
43
P0_4/AN3
42
P0_5/AN2
41
P0_6/AN1
12
11
10
9
8
7
6
5
4
3
2
1
13
14
15
16
17
18
19
20
21
22
23
24
25
P2_6/TRDIOC1
P1_7/TRAIO/INT1
P1_6/CLK0
P1_5/RXD0/(TRAIO)/(INT1)
P1_4/TXD0
P1_3/KI3/AN11
P2_5/TRDIOB1
P2_4/TRDIOA1
P2_3/TRDIOD0
P2_2/TRDIOC0
P2_1/TRDIOB0
P2_0/TRDIOA0/TCLK
26
28
29
30
31
32
33
34
35
36
37
38
39
27
40
NC
P2
_7
/TRDIOD1
VCC
P4_6/XIN
VS
S
(1
)
XO
UT/
P
4
_
7
RESET
P4_4
/XC
O
U
T
P4_3/X
CIN
MO
D
E
P3_4/S
D
A/SCS
P3_3/SSI
P
3_5
/S
CL/
S
SC
K
P
3_1
/T
R
B
O
P
3_0
/T
R
A
O
P
6_5
P
6_4
P
6_3
P
0_7
/A
N0
P
4_5
/I
N
T
0
P
6_6
/I
N
T
2(
/T
XD
1
)
P
6_7
/I
N
T
3(
/R
XD
1)
P
1_2
/K
I2
/A
N10
P
1_1
/K
I1
/A
N9
P
1_0
/K
I0
/A
N8
NC
NC
NC
NOTES:
1. P4_7 is a port for the input.
Package: PLQP0052JA-A(52P6A-A)
0.65 mm pin-pitch, 10 mm square body
Rev.0.20
Mar 8, 2005
Page 8 of 22
REJ03B0117-0020
Under development
R8C/24, R8C/25 Group
1. Overview
Preliminary specification
Specifications in this manual are tentative and subject to change.
1.6
Pin Description
Table 1.5 lists the Pin Description.
I: Input
O: Output
I/O: Input and output
Table 1.5
Pin Description
Function
Pin name
I/O type
Description
Power Supply Input
VCC
VSS
I
Apply 2.2 V to 5.5 V to the VCC pin. Apply 0 V to the
VSS pin.
Reset Input
RESET
I
Input "L" on this pin resets the MCU.
MODE
MODE
I
Connect this pin to VCC via a resistor.
XIN Clock Input
XIN
I
These pins are provided for the XIN clock generation
circuit I/O. Connect a ceramic resonator or a crystal
oscillator between the XIN and XOUT pins. To use an
externally derived clock, input it to the XIN pin and leave
the XOUT pin open.
XIN Clock Output
XOUT
O
XCIN Clock Input
XCIN
I
These pins are provided for the XCIN clock generation
circuit I/O. Connect a crystal oscillator between the
XCIN and XCOUT pins. To use an externally derived
clock, input it to the XCIN pin and leave the XCOUT pin
open.
XCIN Clock Output
XCOUT
O
INT Interrupt Input
INT0 to INT3
I
INT interrupt input pins.
Key Input Interrupt
KI0 to KI3
I
Key input interrupt input pins.
Timer RA
TRAIO
I/O
Timer RA I/O pin.
TRAO
O
Timer RA output pin.
Timer RB
TRBO
O
Timer RB output pin.
Timer RD
TRDIOA0, TRDIOA1,
TRDIOB0, TRDIOB1,
TRDIOC0, TRDIOC1,
TRDIOD0, TRDIOD1
I/O
Timer RD I/O ports.
TCLK
I
External clock input pin.
Timer RE
TREO
O
Divided clock output pin.
Serial Interface
CLK0
I/O
Transfer clock I/O pin.
RXD0, RXD1
I
Serial data input pins.
TXD0, TXD1
O
Serial data output pins.
I
2
C Bus Interface (IIC)
SCL
I/O
Clock I/O pin.
SDA
I/O
Data I/O pin.
Reference Voltage Input VREF
I
Reference voltage input pin to A/D converter.
SSU
SSI
I/O
Data I/O pin.
SCS
I/O
Chip-select signal I/O pin.
SSCK
I/O
Clock I/O pin.
SSO
I/O
Data I/O pin.
A/D Converter
AN0 to AN11
I
Analog input pins to A/D converter.
I/O Port
P0_0 to P0_7,
P1_0 to P1_7,
P2_0 to P2_7,
P3_0, P3_1,
P3_3 to P3_5, P3_7,
P4_3 to P4_5,
P6_0 to P6_7
I/O
These are CMOS I/O ports. Each port contains an input/
output select direction register, allowing each pin in that
port to be directed for input or output individually.
Any port set to input can select whether to use a pull-up
resistor or not by program.
P2_0 to P2_7 also function as LED drive ports.
Input Port
P4_2, P4_6, P4_7
I
Ports for input-only.
Rev.0.20
Mar 8, 2005
Page 9 of 22
REJ03B0117-0020
Under development
R8C/24, R8C/25 Group
1. Overview
Preliminary specification
Specifications in this manual are tentative and subject to change.
Table 1.6
Pin Name Information by Pin Number
Pin
Number
Control Pin
Port
I/O Pin of Peripheral Function
Interrupt
Timer
Serial
Interface
Clock
Synchronous
Serial I/O with
Chip Select
I
2
C Bus
Interface
A/D
Converter
2
P3_5
SSCK
SCL
3
P3_3
SSI
4
P3_4
SCS
SDA
5
MODE
6
XCIN
P4_3
7
XCOUT
P4_4
8
RESET
9
XOUT
P4_7
10
VSS
11
XIN
P4_6
12
VCC
13
P2_7
TRDIOD1
14
P2_6
TRDIOC1
15
P2_5
TRDIOB1
16
P2_4
TRDIOA1
17
P2_3
TRDIOD0
18
P2_2
TRDIOC0
19
P2_1
TRDIOB0
20
P2_0
TRDIOA0/TCLK
21
P1_7
INT1
TRAIO
22
P1_6
CLK0
23
P1_5
(INT1)
(TRAIO)
RXD0
24
P1_4
TXD0
25
P1_3
KI3
AN11
27
P4_5
INT0
28
P6_6
INT2
(TXD1)
29
P6_7
INT3
(RXD1)
30
P1_2
KI2
AN10
31
P1_1
KI1
AN9
32
P1_0
KI0
AN8
33
P3_1
TRBO
34
P3_0
TRAO
35
P6_5
36
P6_4
37
P6_3
38
P0_7
AN0
41
P0_6
AN1
42
P0_5
AN2
43
P0_4
AN3
44
VREF
P4_2
45
P6_0
TREO
46
P6_2
47
P6_1
48
P0_3
AN4
49
P0_2
AN5
50
P0_1
AN6
51
P0_0
AN7
52
P3_7
SSO
Rev.0.20
Mar 8, 2005
Page 10 of 22
REJ03B0117-0020
Under development
R8C/24, R8C/25 Group
2. Central Processing Unit (CPU)
Preliminary specification
Specifications in this manual are tentative and subject to change.
2.
Central Processing Unit (CPU)
Figure 2.1 shows the CPU Register. The CPU contains 13 registers. Of these, R0, R1, R2, R3, A0, A1 and
FB comprise a register bank. Two sets of register banks are provided.
Figure 2.1
CPU Register
R2
b31
b15
b8b7
b0
Data Registers
(1)
Address Registers
(1)
R3
R0H (high-order of R0)
R2
R3
A0
A1
INTBH
b15
b19
b0
INTBL
FB
Frame Bass Register
(1)
The 4-high order bits of INTB are INTBH and
the 16-low order bits of INTB are INTBL.
Interrupt Table Register
b19
b0
USP
Program Counter
ISP
SB
User Stack Pointer
Interrupt Stack Pointer
Static Base Register
PC
FLG
Flag Register
Carry Flag
Debug Flag
Zero Flag
Sign Flag
Register Bank Select Flag
Overflow Flag
Interrupt Enable Flag
Stack Pointer Select Flag
Reserved Area
Processor Interrupt Priority Level
Reserved Area
C
IPL
D
Z
S
B
O
I
U
b15
b0
b15
b0
b15
b0
b8
b7
NOTES:
1. These registers comprise a register bank. There are two register banks.
R1H (high-order of R1)
R0L (low-order of R0)
R1L (low-order of R1)
Rev.0.20
Mar 8, 2005
Page 11 of 22
REJ03B0117-0020
Under development
R8C/24, R8C/25 Group
2. Central Processing Unit (CPU)
Preliminary specification
Specifications in this manual are tentative and subject to change.
2.1
Data Registers (R0, R1, R2 and R3)
R0 is a 16-bit register for transfer, arithmetic and logic operations. The same applies to R1 to R3. The
R0 can be split into high-order bit (R0H) and low-order bit (R0L) to be used separately as 8-bit data
registers. The same applies to R1H and R1L as R0H and R0L. R2 can be combined with R0 to be used
as a 32-bit data register (R2R0). The same applies to R3R1 as R2R0.
2.2
Address Registers (A0 and A1)
A0 is a 16-bit register for address register indirect addressing and address register relative addressing.
They also are used for transfer, arithmetic and logic operations. The same applies to A1 as A0. A1 can
be combined with A0 to be used as a 32-bit address register (A1A0).
2.3
Frame Base Register (FB)
FB is a 16-bit register for FB relative addressing.
2.4
Interrupt Table Register (INTB)
INTB is a 20-bit register indicates the start address of an interrupt vector table.
2.5
Program Counter (PC)
PC, 20 bits wide, indicates the address of an instruction to be executed.
2.6
User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
The stack pointer (SP), USP and ISP, are 16 bits wide each. The U flag of FLG is used to switch
between
USP and ISP.
2.7
Static Base Register (SB)
SB is a 16-bit register for SB relative addressing.
2.8
Flag Register (FLG)
FLG is a 11-bit register indicating the CPU state.
2.8.1
Carry Flag (C)
The C flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic and logic unit.
2.8.2
Debug Flag (D)
The D flag is for debug only. Set to "0".
2.8.3
Zero Flag (Z)
The Z flag is set to "1" when an arithmetic operation resulted in 0; otherwise, "0".
2.8.4
Sign Flag (S)
The S flag is set to "1" when an arithmetic operation resulted in a negative value; otherwise, "0".
2.8.5
Register Bank Select Flag (B)
The register bank 0 is selected when the B flag is "0". The register bank 1 is selected when this flag
is set to "1".
2.8.6
Overflow Flag (O)
The O flag is set to "1" when the operation resulted in an overflow; otherwise, "0".
Rev.0.20
Mar 8, 2005
Page 12 of 22
REJ03B0117-0020
Under development
R8C/24, R8C/25 Group
2. Central Processing Unit (CPU)
Preliminary specification
Specifications in this manual are tentative and subject to change.
2.8.7
Interrupt Enable Flag (I)
The I flag enables a maskable interrupt.
An interrupt is disabled when the I flag is set to "0", and are enabled when the I flag is set to "1". The
I flag is set to "0" when an interrupt request is acknowledged.
2.8.8
Stack Pointer Select Flag (U)
ISP is selected when the U flag is set to "0", USP is selected when the U flag is set to "1".
The U flag is set to "0" when a hardware interrupt request is acknowledged or the INT instruction of
software interrupt numbers 0 to 31 is executed.
2.8.9
Processor Interrupt Priority Level (IPL)
IPL, 3 bits wide, assigns processor interrupt priority levels from level 0 to level 7.
If a requested interrupt has greater priority than IPL, the interrupt is enabled.
2.8.10
Reserved Area
When write to this bit, set to "0". When read, its content is indeterminate.
Rev.0.20
Mar 8, 2005
Page 13 of 22
REJ03B0117-0020
Under development
R8C/24, R8C/25 Group
3. Memory
Preliminary specification
Specifications in this manual are tentative and subject to change.
3.
Memory
3.1
R8C/24 Group
Figure 3.1 is a Memory Map of R8C/24 Group. The R8C/24 group provides the 1-Mbyte address space
from addresses 00000h to FFFFFh.
The internal ROM is allocated lower addresses beginning with address 0FFFFh. For example, a 48-
Kbyte internal ROM is allocated addresses 04000h to 0FFFFh.
The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. They store the starting
address of each interrupt routine.
The internal RAM is allocated higher addresses beginning with address 00400h. For example, a 2-
Kbyte internal RAM is allocated addresses 00400h to 00BFFh. The internal RAM is used not only for
storing data but for calling subroutines and stacks when interrupt request is acknowledged.
Special function registers (SFR) are allocated addresses 00000h to 002FFh. The peripheral function
control registers are allocated them. All addresses, which have nothing allocated within the SFR, are
reserved area and cannot be accessed by users.
Figure 3.1
Memory Map of R8C/24 Group
Undefined Instruction
Overflow
BRK Instruction
Address Match
Single Step
Watchdog TimerOscillation Stop DetectionVoltage Monitor
(Reserved)
(Reserved)
Reset
Part Number
Internal ROM
Internal RAM
Size
Address 0YYYYh
R5F21244SNFP, R5F21244SDFP
R5F21246SNFP, R5F21246SDFP
R5F21247SNFP, R5F21247SDFP
R5F21248SNFP, R5F21248SDFP
16 kbytes
32 kbytes
48 kbytes
64 kbytes
-
-
-
13FFFh
007FFh
00BFFh
00DFFh
00FFFh
00400h
002FFh
00000h
Internal RAM
SFR
(See 4. Special Function
Register (SFR))
0FFFFh
0FFDCh
Address 0XXXXh
NOTES:
1. Blank spaces are reserved. No access is allowed.
Address 1ZZZZh
Size
1 kbytes
2 kbytes
2.5 kbytes
3 kbytes
0C000h
08000h
04000h
04000h
FFFFFh
0FFFFh
0YYYYh
Internal ROM
(Program Area)
Expansion Area
Internal ROM
(Program Area)
1ZZZZh
0XXXh
Rev.0.20
Mar 8, 2005
Page 14 of 22
REJ03B0117-0020
Under development
R8C/24, R8C/25 Group
3. Memory
Preliminary specification
Specifications in this manual are tentative and subject to change.
3.2
R8C/25 Group
Figure 3.2 is a Memory Map of R8C/25 Group. The R8C/25 group provides the 1-Mbyte address space
from addresses 00000h to FFFFFh.
The internal ROM is allocated lower addresses beginning with address 0FFFFh. For example, a 48-
Kbyte internal ROM is allocated addresses 04000h to 0FFFFh.
The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. They store the starting
address of each interrupt routine.
The internal ROM (data area) is allocated addresses 02400h to 02BFFh.
The internal RAM is allocated higher addresses beginning with address 00400h. For example, a 2-
Kbyte internal RAM is allocated addresses 00400h to 00BFFh. The internal RAM is used not only for
storing data but for calling subroutines and stacks when interrupt request is acknowledged.
Special function registers (SFR) are allocated addresses 00000h to 002FFh. The peripheral function
control registers are allocated them. All addresses, which have nothing allocated within the SFR, are
reserved area and cannot be accessed by users.
Figure 3.2
Memory Map of R8C/25 Group
Undefined Instruction
Overflow
BRK Instruction
Address Match
Single Step
Watchdog TimerOscillation Stop DetectionVoltage Monitor
(Reserved)
(Reserved)
Reset
Part Number
Internal ROM
Internal RAM
Size
Address 0YYYYh
R5F21254SNFP, R5F21254SDFP
R5F21256SNFP, R5F21256SDFP
R5F21257SNFP, R5F21257SDFP
R5F21258SNFP, R5F21258SDFP
16 kbytes
32 kbytes
48 kbytes
64 kbytes
007FFh
00BFFh
00DFFh
00FFFh
FFFFFh
0FFFFh
0YYYYh
00400h
002FFh
00000h
Internal ROM
(Program Area)
Expansion Area
Internal RAM
SFR
(See 4. Special Function
Register (SFR))
0FFFFh
0FFDCh
Address 0XXXXh
Address 1ZZZZh
Size
1 kbytes
2 kbytes
2.5 kbytes
3 kbytes
Internal ROM
(Data Area)
(1)
NOTES:
1. The data flash ROM block A (1 Kbytes) and B (1 Kbytes) are shown.
2. Blank spaces are reserved. No access is allowed.
0XXXXh
02400h
02BFFh
Internal ROM
(Program Area)
1ZZZZh
-
-
-
13FFFh
0C000h
08000h
04000h
04000h
Rev.0.20
Mar 8, 2005
Page 15 of 22
REJ03B0117-0020
Under development
R8C/24, R8C/25 Group
4. Special Function Register (SFR)
Preliminary specification
Specifications in this manual are tentative and subject to change.
4.
Special Function Register (SFR)
SFR (Special Function Register) is the control register of peripheral functions. Tables 4.1 to 4.7 list the SFR
information.
Table 4.1
SFR Information(1)
(1)
X: Undefined
NOTES:
1. Blank spaces are reserved. No access is allowed.
2. Software reset, the watchdog timer reset or the voltage monitor 2 reset does not affect this register.
3. Owing to Hardware reset.
4. Owing to Power-on reset or the voltage monitor 1 reset.
5. Software reset, the watchdog timer reset or the voltage monitor 2 reset does not affect b2 and b3.
Address
Register
Symbol
After reset
0000h
0001h
0002h
0003h
0004h
Processor Mode Register 0
PM0
00h
0005h
Processor Mode Register 1
PM1
00h
0006h
System Clock Control Register 0
CM0
01101000b
0007h
System Clock Control Register 1
CM1
00100000b
0008h
0009h
000Ah
Protect Register
PRCR
00XXX000b
000Bh
000Ch
Oscillation Stop Detection Register
OCD
00000100b
000Dh
Watchdog Timer Reset Register
WDTR
XXh
000Eh
Watchdog Timer Start Register
WDTS
XXh
000Fh
Watchdog Timer Control Register
WDC
00011111b
0010h
Address Match Interrupt Register 0
RMAD0
00h
0011h
00h
0012h
X0h
0013h
Address Match Interrupt Enable Register
AIER
XXXXXX00b
0014h
Address Match Interrupt Register 1
RMAD1
00h
0015h
00h
0016h
X0h
0017h
0018h
0019h
001Ah
001Bh
001Ch
Count Source Protect Mode Register
CSPR
00h
001Dh
001Eh
001Fh
0020h
0021h
0022h
0023h
High-Speed On-Chip Oscillator Control Register 0
FRA0
00h
0024h
High-Speed On-Chip Oscillator Control Register 1
FRA1
TBD
0025h
High-Speed On-Chip Oscillator Control Register 2
FRA2
00h
0026h
0027h
0028h
Clock Prescaler Reset Flag
CPSRF
00h
0029h
0030h
0031h
Voltage Detection Register 1
(2)
VCA1
00001000b
0032h
Voltage Detection Register 2
(2)
VCA2
00h
(3)
00100000b
(4)
0033h
0034h
0035h
0036h
Voltage Monitor 1 Control Register
(2)
VW1C
00001000b
0037h
Voltage Monitor 2 Control Register
(5)
VW2C
00h
0038h
Voltage Monitor 0 Control Register
(2)
VW0C
00001000b
(3)
01000001b
(4)
0039h
003Ah
003Bh
003Ch
003Dh
003Eh
003Fh
Rev.0.20
Mar 8, 2005
Page 16 of 22
REJ03B0117-0020
Under development
R8C/24, R8C/25 Group
4. Special Function Register (SFR)
Preliminary specification
Specifications in this manual are tentative and subject to change.
Table 4.2
SFR Information(2)
(1)
X: Undefined
NOTES:
1. Blank spaces are reserved. No access is allowed.
Address
Register
Symbol
After reset
0040h
0041h
0042h
0043h
0044h
0045h
0046h
0047h
0048h
Timer RD0 Interrupt Control Register
RD0IC
XXXXX000b
0049h
Timer RD1 Interrupt Control Register
RD1IC
XXXXX000b
004Ah
Timer RE Interrupt Control Register
REIC
XXXXX000b
004Bh
004Ch
004Dh
Key Input Interrupt Control Register
KUPIC
XXXXX000b
004Eh
A/D Conversion Interrupt Control Register
ADIC
XXXXX000b
004Fh
IIC/SSU Interrupt Control Register
IIC2IC
XXXXX000b
0050h
0051h
UART0 Transmit Interrupt Control Register
S0TIC
XXXXX000b
0052h
UART0 Receive Interrupt Control Register
S0RIC
XXXXX000b
0053h
UART1 Transmit Interrupt Control Register
S1TIC
XXXXX000b
0054h
UART1 Receive Interrupt Control Register
S1RIC
XXXXX000b
0055h
INT2 Interrupt Control Register
INT2IC
XX00X000b
0056h
Timer RA Interrupt Control Register
RAIC
XXXXX000b
0057h
0058h
Timer RB Interrupt Control Register
RBIC
XXXXX000b
0059h
INT1 Interrupt Control Register
INT1IC
XX00X000b
005Ah
INT3 Interrupt Control Register
INT3IC
XX00X000b
005Bh
005Ch
005Dh
INT0 Interrupt Control Register
INT0IC
XX00X000b
005Eh
005Fh
0060h
0061h
0062h
0063h
0064h
0065h
0066h
0067h
0068h
0069h
006Ah
006Bh
006Ch
006Dh
006Eh
006Fh
0070h
0071h
0072h
0073h
0074h
0075h
0076h
0077h
0078h
0079h
007Ah
007Bh
007Ch
007Dh
007Eh
007Fh
Rev.0.20
Mar 8, 2005
Page 17 of 22
REJ03B0117-0020
Under development
R8C/24, R8C/25 Group
4. Special Function Register (SFR)
Preliminary specification
Specifications in this manual are tentative and subject to change.
Table 4.3
SFR Information(3)
(1)
X: Undefined
NOTES:
1. Blank spaces are reserved. No access is allowed.
2. Selected by the IICSEL bit in the PMR register.
Address
Register
Symbol
After reset
0080h
0081h
0082h
0083h
0084h
0085h
0086h
0087h
0088h
0089h
008Ah
008Bh
008Ch
008Dh
008Eh
008Fh
0090h
0091h
0092h
0093h
0094h
0095h
0096h
0097h
0098h
0099h
009Ah
009Bh
009Ch
009Dh
009Eh
009Fh
00A0h
UART0 Transmit/Receive Mode Register
U0MR
00h
00A1h
UART0 Bit Rate Register
U0BRG
XXh
00A2h
UART0 Transmit Buffer Register
U0TB
XXh
00A3h
XXh
00A4h
UART0 Transmit/Receive Control Register 0
U0C0
00001000b
00A5h
UART0 Transmit/Receive Control Register 1
U0C1
00000010b
00A6h
UART0 Receive Buffer Register
U0RB
XXh
00A7h
XXh
00A8h
UART1 Transmit/Receive Mode Register
U1MR
00h
00A9h
UART1 Bit Rate Register
U1BRG
XXh
00AAh
UART1 Transmit Buffer Register
U1TB
XXh
00ABh
XXh
00ACh
UART1 Transmit/Receive Control Register 0
U1C0
00001000b
00ADh
UART1 Transmit/Receive Control Register 1
U1C1
00000010b
00AEh
UART1 Receive Buffer Register
U1RB
XXh
00AFh
XXh
00B0h
00B1h
00B2h
00B3h
00B4h
00B5h
00B6h
00B7h
00B8h
SS Control Register H / IIC bus Control Register 1
(2)
SSCRH / ICCR1
00h
00B9h
SS Control Register L / IIC bus Control Register 2
(2)
SSCRL / ICCR2
01111101b
00BAh
SS Mode Register / IIC bus Mode Register
(2)
SSMR / ICMR
00011000b
00BBh
SS Enable Register / IIC bus Interrupt Enable Register
(2)
SSER / ICIER
00h
00BCh
SS Status Register / IIC bus Status Register
(2)
SSSR / ICSR
00h
00BDh
SS Mode Register 2 / Slave Address Register
(2)
SSMR2 / SAR
00h
00BEh
SS Transmit Data Register / IIC bus Transmit Data Register
(2)
SSTDR / ICDRT
FFh
00BFh
SS Receive Data Register / IIC bus Receive Data Register
(2)
SSRDR / ICDRR
FFh
Rev.0.20
Mar 8, 2005
Page 18 of 22
REJ03B0117-0020
Under development
R8C/24, R8C/25 Group
4. Special Function Register (SFR)
Preliminary specification
Specifications in this manual are tentative and subject to change.
Table 4.4
SFR Information(4)
(1)
X: Undefined
NOTES:
1. Blank spaces are reserved. No access is allowed.
Address
Register
Symbol
After reset
00C0h
A/D Register
AD
XXh
00C1h
XXh
00C2h
00C3h
00C4h
00C5h
00C6h
00C7h
00C8h
00C9h
00CAh
00CBh
00CCh
00CDh
00CEh
00CFh
00D0h
00D1h
00D2h
00D3h
00D4h
A/D Control Register 2
ADCON2
00h
00D5h
00D6h
A/D Control Register 0
ADCON0
00000XXXb
00D7h
A/D Control Register 1
ADCON1
00h
00D8h
00D9h
00DAh
00DBh
00DCh
00DDh
00DEh
00DFh
00E0h
Port P0 Register
P0
XXh
00E1h
Port P1 Register
P1
XXh
00E2h
Port P0 Direction Register
PD0
00h
00E3h
Port P1 Direction Register
PD1
00h
00E4h
Port P2 Register
P2
XXh
00E5h
Port P3 Register
P3
XXh
00E6h
Port P2 Direction Register
PD2
00h
00E7h
Port P3 Direction Register
PD3
00h
00E8h
Port P4 Register
P4
XXh
00E9h
00EAh
Port P4 Direction Register
PD4
00h
00EBh
00ECh
Port P6 Register
P6
XXh
00EDh
00EEh
Port P6 Direction Register
PD6
00h
00EFh
00F0h
00F1h
00F2h
00F3h
00F4h
Port P2 Drive Capacity Control Register
P2DRR
00h
00F5h
00F6h
00F7h
00F8h
Port Mode Register
PMR
00h
00F9h
External Input Enable Register
INTEN
00h
00FAh
INT Input filter select Register
INTF
00h
00FBh
Key Input Enable Register
KIEN
00h
00FCh
Pull-Up Control Register 0
PUR0
00h
00FDh
Pull-Up Control Register 1
PUR1
XX00XX00b
00FEh
00FFh
Rev.0.20
Mar 8, 2005
Page 19 of 22
REJ03B0117-0020
Under development
R8C/24, R8C/25 Group
4. Special Function Register (SFR)
Preliminary specification
Specifications in this manual are tentative and subject to change.
Table 4.5
SFR Information(5)
(1)
X: Undefined
NOTES:
1. Blank spaces are reserved. No access is allowed.
Address
Register
Symbol
After reset
0100h
Timer RA Control Register
TRACR
00h
0101h
Timer RA I/O Control Register
TRAIOC
00h
0102h
Timer RA Mode Register
TRAMR
00h
0103h
Timer RA Prescaler Register
TRAPRE
FFh
0104h
Timer RA Register
TRA
FFh
0105h
0106h
LIN Control Register
LINCR
00h
0107h
LIN Status Register
LINST
00h
0108h
Timer RB Control Register
TRBCR
00h
0109h
Timer RB One-Shot Control Register
TRBOCR
00h
010Ah
Timer RB I/O Control Register
TRBIOC
00h
010Bh
Timer RB Mode Register
TRBMR
00h
010Ch
Timer RB Prescaler Register
TRBPRE
FFh
010Dh
Timer RB Secondary Register
TRBSC
FFh
010Eh
Timer RB Primary Register
TRBPR
FFh
010Fh
0110h
0111h
0112h
0113h
0114h
0115h
0116h
0117h
0118h
Timer RE Second Data Register/Counter Register
TRESEC
00h
0119h
Timer RE Minute Data Register/Compare Register
TREMIN
00h
011Ah
Timer RE Time Data Register
TREHR
00h
011Bh
Timer RE Day Data Register
TREWK
00h
011Ch
Timer RE Control Register 1
TRECR1
00h
011Dh
Timer RE Control Register 2
TRECR2
00h
011Eh
Timer RE Clock Source Select Register
TRECSR
00001000b
011Fh
0120h
0121h
0122h
0123h
0124h
0125h
0126h
0127h
0128h
0129h
012Ah
012Bh
012Ch
012Dh
012Eh
012Fh
0130h
0131h
0132h
0133h
0134h
0135h
0136h
0137h
Timer RD Start Register
TRDSTR
11111100b
0138h
Timer RD Mode Register
TRDMDR
00001110b
0139h
Timer RD PWM Mode Register
TRDPMR
10001000b
013Ah
Timer RD Function Control Register
TRDFCR
10000000b
013Bh
Timer RD Output Master Enable Register
TRDOER1
FFh
013Ch
Timer RD Output Master Enable Register 2
TRDOER2
01111111b
013Dh
Timer RD Output Control Register
TRDOCR
00h
013Eh
Timer RD Digital Filter Function Select Register 0
TRDDF0
00h
013Fh
Timer RD Digital Filter Function Select Register 1
TRDDF1
00h
Rev.0.20
Mar 8, 2005
Page 20 of 22
REJ03B0117-0020
Under development
R8C/24, R8C/25 Group
4. Special Function Register (SFR)
Preliminary specification
Specifications in this manual are tentative and subject to change.
Table 4.6
SFR Information(6)
(1)
X: Undefined
NOTES:
1. Blank spaces are reserved. No access is allowed.
Address
Register
Symbol
After reset
0140h
Timer RD Control Register 0
TRDCR0
00h
0141h
Timer RD I/O Control Register A0
TRDIORA0
10001000b
0142h
Timer RD I/O Control Register C0
TRDIORC0
10001000b
0143h
Timer RD Status Register 0
TRDSR0
11000000b
0144h
Timer RD Interrupt Enable Register 0
TRDIER0
11100000b
0145h
Timer RD PWM Mode Output Level Control Register 0
POCR0
11111000b
0146h
Timer RD Counter 0
TRDCNT0
00h
0147h
00h
0148h
Timer RD General Register A0
GRA0
FFh
0149h
FFh
014Ah
Timer RD General Register B0
GRB0
FFh
014Bh
FFh
014Ch
Timer RD General Register C0
GRC0
FFh
014Dh
FFh
014Eh
Timer RD General Register D0
GRD0
FFh
014Fh
FFh
0150h
Timer RD Control Register 1
TRDCR1
00h
0151h
Timer RD I/O Control Register A1
TRDIORA1
10001000b
0152h
Timer RD I/O Control Register C1
TRDIORC1
10001000b
0153h
Timer RD Status Register 1
TRDSR1
11000000b
0154h
Timer RD Interrupt Enable Register 1
TRDIER1
11100000b
0155h
Timer RD PWM Mode Output Level Control Register 1
POCR1
11111000b
0156h
Timer RD Counter 1
TRDCNT1
00h
0157h
00h
0158h
Timer RD General Register A1
GRA1
FFh
0159h
FFh
015Ah
Timer RD General Register B1
GRB1
FFh
015Bh
FFh
015Ch
Timer RD General Register C1
GRC1
FFh
015Dh
FFh
015Eh
Timer RD General Register D1
GRD1
FFh
015Fh
FFh
0160h
0161h
0162h
0163h
0164h
0165h
0166h
0167h
0168h
0169h
016Ah
016Bh
016Ch
016Dh
016Eh
016Fh
0170h
0171h
0172h
0173h
0174h
0175h
0176h
0177h
0178h
0179h
017Ah
017Bh
017Ch
017Dh
017Eh
017Fh
Rev.0.20
Mar 8, 2005
Page 21 of 22
REJ03B0117-0020
Under development
R8C/24, R8C/25 Group
4. Special Function Register (SFR)
Preliminary specification
Specifications in this manual are tentative and subject to change.
Table 4.7
SFR Information(7)
(1)
1. Blank spaces are reserved. No access is allowed.
2. The OFS register cannot be changed by program. Use a flash programmer to write to it.
Address
Register
Symbol
After reset
0180h
0181h
0182h
0183h
0184h
0185h
0186h
0187h
0188h
0189h
018Ah
018Bh
018Ch
018Dh
018Eh
018Fh
0190h
0191h
0192h
0193h
0194h
0195h
0196h
0197h
0198h
0199h
019Ah
019Bh
019Ch
019Dh
019Eh
019Fh
01A0h
01A1h
01A2h
01A3h
01A4h
01A5h
01A6h
01A7h
01A8h
01A9h
01AAh
01ABh
01ACh
01ADh
01AEh
01AFh
01B0h
01B1h
01B2h
01B3h
Flash Memory Control Register 4
FMR4
01000000b
01B4h
01B5h
Flash Memory Control Register1
FMR1
01000101b
01B6h
01B7h
Flash Memory Control Register 0
FMR0
XX000001b
01B8h
01B9h
01BAh
01BBh
01BCh
01BDh
01BEh
01BFh
FFFFh
Option function select Register
OFS
FFh
Rev.0.20
Mar 8, 2005
Page 22 of 22
REJ03B0117-0020
R8C/24, R8C/25 Group
Package Dimensions
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
Package Dimensions (TBD)
A - 1
REVISION HISTORY
R8C/24, R8C/25 Group Short Sheet
Rev.
Date
Description
Page
Summary
0.01
Sep 17, 2004
-
First Edition issued
0.02
Dec 10, 2004
All pages Part Number revised. R8C/26
R8C/24, R8C/27
R8C/25
2, 3
Table 1.1 R8C/24 Group Performance, Table 1.2 R8C/25 Group
Performance
- Serial Interface: I
2
C Bus Interface and Chip-select clock synchronous
(SSU) added.
- LIN Module added.
- Interrupt: Internal factors revised; 10
11
- Note on Operating Ambient Temperature added.
4
Figure 1.1 Block Diagram
- LIN Module added.
- Chip-select clock synchronous (SSU) is added to I
2
C Bus Interface.
5, 6
Table 1.3 Product Information of R8C/24 Group, Table 1.4 Product
Information of R8C/25 Group
Date and Development state revised.
7
Figure 1.4 Pin Assignment
P3_5/SCL
P3_5/SCL/SSCK, P3_3
P3_3/SSI,
P3_4/SDA
P3_4/SDA/SCS, P3_7
P3_7/SSO, VSS/AVSS
VSS,
XIN/P4_6
P4_6/XIN, VCC/AVSS
VCC
12pin P1_7/TRAIO/INT1 to 22pin P1_0/KI0/AN8
20pin P1_7/TRAIO/INT1 to 30pin P1_0/KI0/AN8
8
Table 1.5 Pin Description
- Analog Power Supply Input eliminated.
- SSU added.
9
Table 1.6 Pin Name Information by Pin Number added.
15
Table 4.1 SFR Information (1)
- 0031h: Voltage Detection Register 1
Voltage Detection A Register 1
- 0032h: Voltage Detection Register 1
Voltage Detection A Register 2
01000001b
00100001b (Note 4)
- 0036h: "
(3)
, 01000001b
(4)
" eliminated.
- 0038h: Voltage Monitor 0 Control Register
(2)
, VW0C,
00001000b
(3)
, 01000001b
(4)
added.
16
Table 4.2 SFR Information (2)
- 0048h: Timer RD0 Interrupt Control Register, RD0IC, XXXXX000b added.
- 0049h: Timer RD Interrupt Control Register, RDIC
Timer RD1 Interrupt Control Register, RD1IC
- 004Fh: IIC Interrupt Control Register, IIC
IIC/SSU Interrupt Control Register, IIC2IC
19
Table 4.5 SFR Information (3)
- 0106h: LIN Control Register, LINCR, 00h added.
-0107h: LIN Status Register, LINST, 00h added.
A - 2
REVISION HISTORY
R8C/24, R8C/25 Group Short Sheet
Rev.
Date
Description
Page
Summary
0.10
Feb 24, 2005 1 to 3
5, 6
Pin type changed: 48-pin(under consideration)
52-pin.
5 to 7 Package type revised: 48-pin LQFP(under consideration)
PLQP0052JA-A
8
Table 1.5 TCLK added, VREF revised.
9
Table 1.6 revised.
13, 14 Figures 3.1 and 3.2 part number revised.
15
Tabel 4.1 revised:
- 000Fh: 000XXXXXb
00011111b
- 0023h: FR0
FRA0
- 0024h: FR1
FRA1
- 0025h: FR2
FRA2
- 0031h: Voltage Detection A Register 1, VC1
Voltage Detection Register 1, VCA1
- 0032h: Voltage Detection A Register 2, VC2
Voltage Detection Register 2, VCA2
17
Tabel 4.3 Register name and the value after reset at 00B8h to 00BFh
revised; NOTE2 added.
19
Tabel 4.5 revised:
- 0107h: LINSR
LINST
- 0137h to 013Fh: Register symbol revised
20
Tabel 4.6 revised:
- 0140h to 015Fh: Register symbol revised
- 0158h, 0159h: Timer RD General Register
Timer RD General Register A1
0.20
Mar 8, 2005
2, 3
8
Tables 1.1, 1.2 and 1.5 revised: "main clock"
"XIN clock"; "sub clock"
"XCIN clock"
15
- 0023h to 0025h: 40MHz On-Chip Oscillator Control Register
High-Speed On-Chip Oscillator Control Register
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