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Product Description
Ordering Information
Typical Applications
Features
Functional Block Diagram
RF Micro Devices, Inc.
7628 Thorndike Road
Greensboro, NC 27409, USA
Tel (336) 664 1233
Fax (336) 664 0454
http://www.rfmd.com
Optimum Technology Matching Applied
Si BJT
GaAs MESFET
GaAs HBT
Si Bi-CMOS
SiGe HBT
Si CMOS
1
GN
D
16
V
CC2
15
V
CC2
14
NC
13
2F0
3
RF IN
4
GND1
9
GN
D
8
VC
C
7
APC
2
6
APC
1
5
V
CC1
12
RF OUT
11
RF OUT
10
RF OUT
2
GND2
RF2173
3V GSM POWER AMPLIFIER
3V GSM Cellular Handsets
3V Dual-Band/Triple-Band Handsets
GPRS Compatible
Commercial and Consumer Systems
Portable Battery-Powered Equipment
The RF2173 is a high power, high efficiency power ampli-
fier module offering high performance in GSM or GPRS
applications. The device is manufactured on an advanced
GaAs HBT process, and has been designed for use as
the final RF amplifier in GSM hand-held digital cellular
equipment and other applications in the 800 MHz to
950MHz band. On-board power control provides over
70dB of control range with an analog voltage input, and
provides power down with a logic "low" for standby opera-
tion. The device is self-contained with 50
input and the
output can be easily matched to obtain optimum power
and efficiency characteristics. The RF2173 can be used
together with the RF2174 for dual-band operation. The
device is packaged in an ultra-small plastic package, min-
imizing the required board space.
Single 2.7V to 4.8V Supply Voltage
+36dBm Output Power at 3.5V
32dB Gain with Analog Gain Control
56% Efficiency
800MHz to 950MHz Operation
Supports GSM and E-GSM
RF2173
3V GSM Power Amplifier
RF2173 PCBA
Fully Assembled Evaluation Board
2
Rev A4 010914
3.75
3.75
+
1.50 SQ
4.00
4.00
1
0.45
0.28
3.20
1.60
0.75
0.50
12
INDEX AREA 3
1.00
0.90
0.75
0.65
0.05
0.00
NOTES:
5
Package Warpage: 0.05 max.
4
Pins 1 and 9 are fused.
Shaded Pin is Lead 1.
1
Dimension applies to plated terminal and is measured between
0.10 mm and 0.25 mm from terminal tip.
2
The terminal #1 identifier and terminal numbering convention
shall conform to JESD 95-1 SPP-012. Details of terminal #1
identifier are optional, but must be located within the zone
indicated. The identifier may be either a mold or marked
feature.
3
0.80
TYP
2
1
Dimensions in mm.
Package Style: LCC, 16-Pin, 4x4
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Absolute Maximum Ratings
Parameter
Rating
Unit
Supply Voltage
-0.5 to +6.0
V
DC
Power Control Voltage (V
APC1,2
)
-0.5 to +3.0
V
DC Supply Current
2400
mA
Input RF Power
+13
dBm
Duty Cycle at Max Power
50
%
Output Load VSWR
10:1
Operating Case Temperature
-40 to +85
C
Storage Temperature
-55 to +150
C
Parameter
Specification
Unit
Condition
Min.
Typ.
Max.
Overall
Temp= 25C, V
CC
=3.5V, V
APC1,2
= 2.6V,
P
IN
=+6dBm, Freq= 880MHz to 915MHz,
25% Duty Cycle, pulse width=1154
s
Operating Frequency Range
880 to 915
MHz
See evaluation board schematic.
Usable Frequency Range
800 to 950
MHz
Maximum Output Power
+35.0
+36
dBm
Temp= 25C, V
CC
=3.5V, V
APC1,2
= 2.6V
+34.0
+35.2
dBm
Temp= +25C, V
CC
= 3.2V, V
APC1,2
= 2.6V
+34.0
dBm
Temp= +85C, V
CC
= 3.2V, V
APC1,2
= 2.6V
+33.0
+34.0
dBm
Temp= 25C, V
CC
=2.7V, V
APC1,2
= 2.6V
+32.5
dBm
Temp= +85C, V
CC
= 2.7V, V
APC1,2
= 2.6V
Total Efficiency
50
56
%
At P
OUT,MAX
, V
CC
= 3.2V
56
%
At P
OUT,MAX
, V
CC
= 3.0V
12
%
P
OUT
= +20dBm
5
%
P
OUT
= +10dBm
Input Power for Max Output
+4
+6
+8
dBm
Output Noise Power
-72
dBm
RBW= 100kHz, 925MHz to 935MHz,
P
OUT,MIN
< P
OUT
< P
OUT,MAX
,
P
IN,MIN
< P
IN
< P
IN,MAX
, V
CC
= 3.0V to 5.0V
-81
dBm
RBW= 100kHz, 935MHz to 960MHz,
P
OUT,MIN
< P
OUT
< P
OUT,MAX
,
P
IN,MIN
< P
IN
< P
IN,MAX
, V
CC
= 3.0V to 5.0V
Forward Isolation
-45
-40
dBm
V
APC1,2
= 0.2V, P
IN
=+6dBm
-30
dBm
V
APC1,2
= 0.2V, P
IN
=+8dBm
Second Harmonic
-50
-38
dBc
Third Harmonic
-65
-43
dBc
All Other Non-Harmonic
Spurious
-36
dBm
Input Impedance
50
Optimum Source Impedance
40+ j10
For best noise performance
Input VSWR
2.5:1
P
OUT,MAX
-5dB <P
OUT
< P
OUT,MAX
4:1
P
OUT
< P
OUT,MAX
-5dB
Output Load VSWR
10:1
Spurious<-36dBm, V
APC1,2
= 0.2V to 2.6V,
RBW= 100kHz
Output Load Impedance
1.5- j1.7
Load Impedance presented at RF OUT pad
Caution! ESD sensitive device.
RF Micro Devices believes the furnished information is correct and accurate
at the time of this printing. However, RF Micro Devices reserves the right to
make changes to its products without notice. RF Micro Devices does not
assume responsibility for the use of the described product(s).
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Parameter
Specification
Unit
Condition
Min.
Typ.
Max.
Power Control V
APC1
V
APC2
Power Control "ON"
2.6
V
Maximum P
OUT
, Voltage supplied to the
input
Power Control "OFF"
0.2
0.5
V
Minimum P
OUT
, Voltage supplied to the input
Power Control Range
75
dB
V
APC1,2
= 0.2V to 2.6V
Gain Control Slope
5
100
150
dB/V
P
OUT
=-10dBm to +35dBm
APC Input Capacitance
10
pF
DC to 2MHz
APC Input Current
4.5
5
mA
V
APC1,2
= 2.6V
10
A
V
APC1,2
=0V
Turn On/Off Time
100
ns
V
APC1,2
=0 to 2.6V
Power Supply
Power Supply Voltage
3.5
V
Specifications
2.7
4.8
V
Nominal operating limits, P
OUT
< +35dBm
5.5
V
With maximum output load VSWR 6:1,
P
OUT
< +35dBm
Power Supply Current
2
A
DC Current at P
OUT,MAX
50
200
375
mA
Idle Current, P
IN
< -30dBm
1
10
A
P
IN
< -30dBm, V
APC1,2
= 0.2V
1
10
A
P
IN
< -30dBm, V
APC1,2
= 0.2V, Temp= +85C
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Pin
Function
Description
Interface Schematic
1
GND
Internally connected to the ground slug.
2
GND2
Ground connection for the driver stage. To minimize the noise power at
the output, it is recommended to connect this pin with a trace of about
40mil to the ground plane. This will slightly reduce the small signal
gain, and lower the noise power. It is important for stability that this pin
have it's own vias to the ground plane, minimizing common inductance.
See pin 15.
3
RF IN
RF Input. This is a 50
input, but the actual impedance depends on the
interstage matching network connected to pin 5. An external DC block-
ing capacitor is required if this port is connected to a DC path to ground
or a DC voltage.
4
GND1
Ground connection for the pre-amplifier stage. Keep traces physically
short and connect immediately to the ground plane for best perfor-
mance. It is important for stability that this pin has it's own vias to the
groundplane, to minimize any common inductance.
See pin 3.
5
VCC1
Power supply for the pre-amplifier stage and interstage matching. This
pin forms the shunt inductance needed for proper tuning of the inter-
stage match. Refer to the application schematic for proper configura-
tion. Note that position and value of the components are important.
See pin 3.
6
APC1
Power Control for the driver stage and pre-amplifier. When this pin is
"low," all circuits are shut off. A "low" is typically 0.5V or less at room
temperature. A shunt bypass capacitor is required. During normal oper-
ation this pin is the power control. Control range varies from about 1.0V
for -10dBm to 2.6V for +35dBm RF output power. The maximum power
that can be achieved depends on the actual output matching; see the
application information for more details. The maximum current into this
pin is 5mA when V
APC1
=2.6V, and 0mA when V
APC
=0V.
7
APC2
Power Control for the output stage. See pin 6 for more details.
See pin 6.
8
VCC
Power supply for the bias circuits.
See pin 6.
9
GND
Internally connected to the ground slug.
10
RF OUT
RF Output and power supply for the output stage. Bias voltage for the
final stage is provided through this wide output pin. An external match-
ing network is required to provide the optimum load impedance.
11
RF OUT
Same as pin 10.
Same as pin 10.
12
RF OUT
Same as pin 10.
Same as pin 10.
13
2F0
Connection for the second harmonic trap. This pin is internally con-
nected to the RF OUT pins. The bonding wire together with an external
capacitor form a series resonator that should be tuned to the second
harmonic frequency in order to increase efficiency and reduce spurious
outputs.
Same as pin 10.
14
NC
Not connected.
15
VCC2
Power supply for the driver stage and interstage matching. This pin
forms the shunt inductance needed for proper tuning of the interstage
match. Please refer to the application schematic for proper configura-
tion, and note that position and value of the components are important.
16
VCC2
Same as pin 15.
Same as pin 15.
Pkg
Base
GND
Ground connection for the output stage. This pad should be connected
to the ground plane by vias directly under the device. A short path is
required to obtain optimum performance, as well as to provide a good
thermal path to the PCB for maximum heat dissipation.
GND1
RF IN
VCC1
From Bias
Stages
GND
VCC
To RF
Stages
GND
APC
GND
PCKG BASE
RF OUT
From Bias
Stages
GND2
VCC2
From Bias
Stages
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Theory of Operation and Application Information
The RF2173 is a three-stage device with 32 dB gain at
full power. Therefore, the drive required to fully satu-
rate the output is +3dBm. Based upon HBT (Hetero-
junction
Bipolar
Transistor)
technology,
the
part
requires only a single positive 3 V supply to operate to
full specification. Power control is provided through a
single pin interface, with a separate Power Down con-
trol pin. The final stage ground is achieved through the
large pad in the middle of the backside of the package.
First and second stage grounds are brought out
through separate ground pins for isolation from the out-
put. These grounds should be connected directly with
vias to the PCB ground plane, and not connected with
the output ground to form a so called "local ground
plane" on the top layer of the PCB. The output is
brought out through the wide output pad, and forms the
RF output signal path.
The amplifier operates in near Class C bias mode. The
final stage is "deep AB", meaning the quiescent current
is very low. As the RF drive is increased, the final stage
self-biases, causing the bias point to shift up and, at
full power, draws about 2000 mA. The optimum load for
the output stage is approximately 1.2
. This is the load
at the output collector, and is created by the series
inductance formed by the output bond wires, vias, and
microstrip, and 2 shunt capacitors external to the part.
The optimum load impedance at the RF Output pad is
1.5-j1.7
.
With this match, a 50
terminal impedance
is achieved. The input is internally matched to 50
with just a blocking capacitor needed. This data sheet
defines the configuration for GSM operation.
The input is DC coupled; thus, a blocking cap must be
inserted in series. Also, the first stage bias may be
adjusted by a resistive divider with high value resistors
on this pin to V
PC
and ground. For nominal operation,
however, no external adjustment is necessary as inter-
nal resistors set the bias point optimally.
VCC1 and VCC2 provide supply voltage to the first and
second stage, as well as provides some frequency
selectivity to tune to the operating band. Essentially,
the bias is fed to this pin through a short microstrip. A
bypass capacitor sets the inductance seen by the part,
so placement of the bypass cap can affect the fre-
quency of the gain peak. This supply should be
bypassed individually with 100pF capacitors before
being combined with V
CC
for the output stage to pre-
vent feedback and oscillations.
The RF OUT pin provides the output power. Bias for
the final stage is fed to this output line, and the feed
must be capable of supporting the approximately 2 A of
current required. Care should be taken to keep the
losses low in the bias feed and output components. A
narrow microstrip line is recommended because DC
losses in a bias choke will degrade efficiency and
power.
While the part is safe under CW operation, maximum
power and reliability will be achieved under pulsed con-
ditions. The data shown in this data sheet is based on
a 12.5% duty cycle and a 600
s pulse, unless speci-
fied otherwise.
The part will operate over a 3.0 V to 5.0V range. Under
nominal conditions, the power at 3.5V will be greater
than +34.5dBm at +90C. As the voltage is increased,
however, the output power will increase. Thus, in a sys-
tem design, the ALC (Automatic Level Control) Loop
will back down the power to the desired level. This
must occur during operation, or the device may be
damaged from too much power dissipation. At 5.0 V,
over +38 dBm may be produced; however, this level of
power is not recommended, and can cause damage to
the device.
The HBT breakdown voltage is >20V, so there are no
issue with overvoltage. However, under worst-case
conditions, with the RF drive at full power during trans-
mit, and the output VSWR extremely high, a low load
impedance at the collector of the output transistors can
cause currents much higher than normal. Due to the
bipolar nature of the devices, there is no limitation on
the amount of current de device will sink, and the safe
current densities could be exceeded.
High current conditions are potentially dangerous to
any RF device. High currents lead to high channel tem-
peratures and may force early failures. The RF2173
includes temperature compensation circuits in the bias
network to stabilize the RF transistors, thus limiting the
current through the amplifier and protecting the
devices from damage. The same mechanism works to
compensate the currents due to ambient temperature
variations.
To avoid excessively high currents it is important to
control the V
APC
when operating at supply voltages
higher than 4.0V, such that the maximum output power
is not exceeded.
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Application Schematic
RF IN
33 pF
V
CC
V
CC
14 pF
6.2 pF
33 pF
RF OUT
33 pF
V
CC
0.9 pF
1 nF
120 pF
Very close to pin 15/16
V
CC
180
Note: All capacitors are standard 0402 multi layer
APC
33 pF
33 pF
1
16
15
14
13
2
3
4
9
8
7
6
5
12
11
10
Spacing between
edge of device and
capacitor 0.062"
Distance center to
center of capacitors
0.416"
Instead of a stripline,
an inductor of 2.7 nH
can be used
Instead of a stripline,
an inductor of ~10 nH
can be used
9 pF
33 pF
10 nH
1 nF
.040"
Quarter wave
length
50
strip
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Internal Schematic
RF IN
1.0k
VCC1
PKG BASE
4.5 pF
GND2
APC1
400
VCC
VCC2
RF OUT
APC2
300
VCC
PKG BASE
5
5
APC1
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Evaluation Board Schematic
(Download Bill of Materials from www.rfmd.com.)
C21
120 pF
C5
1 nF
C19
3.3 uF
+
1
16
15
14
13
3
4
9
8
7
6
5
12
11
10
2
C14
33 pF
C17
1 nF
C24
10 nF
C13
33 pF
J3
VAPC
C15
33 pF
C22
1 nF
VCC
C23
10 nF
VAPC
C16
1 nF
C25
10 nF
L1
10 nH
C11
33 pF
VCC
C12
1 nF
C1
1 nF
R2
180
J1
RF IN
50
strip
50
strip
VCC
C2
33 pF
J2
RF OUT
VCC
C9
33 pF
C8
1 nF
P1
1
2
3
4
5
CON5
NC
GND
P1-4
VCC
P1-3
VCC
GND
C20
3.3 uF
+
L2
8.8 nH
50
strip
C18
3.3 uF
+
2173400C
C7
3.3 uF
+
C3
9 pF
C10
0.9 pF
C6
14 pF
C4
6.2 pF
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Evaluation Board Layout
Board Size 2.0" x 2.0"
Board Thickness 0.032"; Board Material FR-4; Multi-Layer
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Typical Test Setup
Power Supply
10dB/5W
3dB
RF Generator
Spectrum
Analyzer
Buffer
x1 OpAmp
Pulse
Generator
A buffer amplifier is recommended because the current into the
V
APC
changes with voltage. As an alternative, the voltage may be
monitored with an oscilloscope.
V+
V-
S+
S-
Notes about testing the RF2173
The test setup shown above includes two attenuators. The 3dB pad at the input is to minimize the effects that the
switching of the input impedance of the PA has on the signal generator. When V
APC
is switched quickly, the resulting
input impedance change can cause the signal generator to vary its output signal, either in output level or in frequency.
Instead of an attenuator an isolator may also be used. The attenuator at the output is to prevent damage to the spec-
trum analyzer, and should be able to handle the power.
It is important not to exceed the rated supply current and output power. When testing the device at higher than nominal
supply voltage, the V
APC
should be adjusted to avoid the output power exceeding +36 dBm. During load-pull testing at
the output it is important to monitor the forward power through a directional coupler. The forward power should not
exceed +36dBm, and V
APC
needs to be adjusted accordingly. This simulates the behavior for the power control loop in
this respect. To avoid damage, it is recommended to set the power supply to limiting the current during the burst, not to
exceed the maximum current rating.
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