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Preliminary
Product Description
Ordering Information
Typical Applications
Features
Functional Block Diagram
RF Micro Devices, Inc.
7628 Thorndike Road
Greensboro, NC 27409, USA
Tel (336) 664 1233
Fax (336) 664 0454
http://www.rfmd.com
Optimum Technology Matching Applied
Si BJT
GaAs MESFET
GaAs HBT
Si Bi-CMOS
SiGe HBT
Si CMOS
Bias
15
11
10
9
7
RF OUT
12
RF OUT
13
RF OUT
14
VBIAS
16
VREG
8
RF IN
6
GND1
5
Q1C
4
3
VCC
1
2
LTUNE
NC
RF2175
3V 400MHZ LINEAR AMPLIFIER
3V TETRA Cellular Handsets
3V CDMA Cellular Handsets
Portable Battery-Powered Equipment
The RF2175 is a high-power, high-efficiency linear ampli-
fier IC targeting 3V handheld systems. The device is
manufactured on an advanced Gallium Arsenide Hetero-
junction Bipolar Transistor (HBT) process, and has been
designed for use as the final RF amplifier in TETRA
hand-held digital cellular equipment, spread-spectrum
systems, and other applications in the 380MHz to
512MHz band. The RF2175 has an analog bias control
voltage to maximize efficiency. The device is self-con-
tained with 50
input, and the output can be easily
matched to obtain optimum power, efficiency, and linear-
ity characteristics. The package is a small SSOP-16 plas-
tic with backside ground.
Single 3V Supply
31.8dBm Linear Output Power
37.5dB Linear Gain
30% Linear Efficiency
On-Board Power Down Mode
380MHz to 512MHz Operation
RF2175
3V 400MHz Linear Amplifier
RF2175 PCBA
Fully Assembled Evaluation Board
2
Rev A6 010718
EXPOSED HEATSINK
0.154
0.012
0.008
0.025
0.063
0.057
Exposed Heat
Sink
0.087
0.071
0.123
0.107
0.004
0.002 Note 3
-A-
0.196
0.189
0.035
0.016
8 MAX
0 MIN
0.010
0.007
0.237
NOTES:
1. Shaded lead in Pin 1.
2. Lead coplanarity - 0.003 with respect to datum "A".
3. Lead standoff is specified from the lowest point on the
package underside.
Package Style: SSOP-16 Slug
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RF2175
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Absolute Maximum Ratings
Parameter
Rating
Unit
Supply Voltage (RF Off)
+8.0
V
DC
Supply Voltage (RF Applied)
+4.5
V
DC
Mode Voltage (V
BIAS
)
+5.0
V
DC
Control Voltage (V
REG
)
+5.0
V
DC
Input RF Power (Avg.)
+5
dBm
Output VSWR - Inband
6:1
Output VSWR - Out of Band
20:1
Operating Ambient Temperature
-30 to +100
C
Storage Temperature
-40 to +120
C
Moisture Sensitivity
JEDEC Level 5 *
Parameter
Specification
Unit
Condition
Min.
Typ.
Max.
Overall
T = 25C, V
CC
= 3.6V, Freq=410MHz to
420MHz unless otherwise specified, 25%
duty cycle. P
OUT
=31.8dBm
Usable Frequency Range
380
512
MHz
Typical Frequency Range
410 to 420
MHz
Linear Gain
35.0
37.5
39.0
dB
Harmonic
-30
dBc
P3dB Output Power
34
dBm
Linear Output Power
(TETRA Modulation)
31.8
dBm
Total Linear Efficiency
25
30
%
Adjacent Channel Power Rejec-
tion
-35
dBc
ACPR @25kHz, TETRA modulation
-45
dBc
ACPR @50kHz, TETRA modulation
Power Supply
Power Supply Voltage
3.0
3.6
4.5
V
Idle Current
230
300
mA
All V
CC
pins, no RF input.
V
CC
Current
1650
mA
All V
CC
pins, P
OUT
=31.8dBm
V
REG
Current
13
mA
Pin 8
V
BIAS
Current
3
mA
Pin 16
Turn On/Off Time
<150
s
Time for power to rise to 95% of its final
value. Measured with 4.7
F and 2.2
F
capacitors on both V
REG
and V
BIAS
lines.
Total Current (Power Down)
10
A
V
REG
=Low
V
REG
"Low" Voltage
0
0.2
V
V
REG
"High" Voltage
2.7
2.8
2.9
V
V
BIAS
Control Voltage Range
2.8
2.9
V
* The RF2175 is considered JEDEC Level 5 for moisture sensitivity with a maximum peak reflow temperature of 220C. To assure reli-
able performance, this part must be handled in accordance with JEDEC specifications for a Level 5 part.
Caution! ESD sensitive device.
RF Micro Devices believes the furnished information is correct and accurate
at the time of this printing. However, RF Micro Devices reserves the right to
make changes to its products without notice. RF Micro Devices does not
assume responsibility for the use of the described product(s).
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Pin
Function
Description
Interface Schematic
1
VCC
Power supply for input bias circuitry. A 1nF high frequency bypass
capacitor is recommended.
2
L TUNE
Interstage Tuning. A shunt inductor to GND is required to optimize the
match.
3
NC
No connection.
4
Q1C
Power supply for stage 1. V
CC
should be fed through a 25nH or greater
inductor with a decoupling capacitor on the V
CC
side.
5
GND1
Ground for stage 1. For best performance, keep traces physically short
and connect immediately to ground plane. This ground should be iso-
lated from the backside ground contact.
6
RF IN
RF input. An external DC blocking capacitor is required if this port is
connected to a DC path to ground or a DC voltage.
7
NC
No connection.
8
VREG
Power Down control. When this pin is "low", all circuits are shut off.
When this pin is 2.8V, all circuits are operating normally. V
PD
requires a
regulated 2.8V for the amplifier to operate properly over all specified
temperature and voltage ranges. A dropping resistor from a higher reg-
ulated voltage may be used to provide the required 2.8V. A 100pF high
frequency bypass capacitor is recommended.
9
NC
No connection.
10
NC
No connection.
11
NC
No connection.
12
RF OUT
RF output and power supply for the output stage. The bias for the out-
put stage is provided through this pin and pin 13. An external matching
network is required to provide the optimum load impedance; see the
application schematics for details.
13
RF OUT
Same as pin 12.
14
RF OUT
Harmonic trap. This pin connects to the RF output but is used for pro-
viding a low impedance to the second harmonic of the operating fre-
quency. An inductor or transmission line resonating with a shunt
capacitor at 2f
0
is connected to this pin.
15
NC
No connection.
16
VBIAS
The bias pin allows higher efficiency in low power power modes. When
operating at full output, VBIAS should be 2.8V.
Pkg
Base
GND
Ground connection. The backside of the package should be soldered to
a top side ground pad, which is connected to the ground plane with
multiple vias. The pad should have a short thermal path to the ground
plane.
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Application Schematic
380MHz
1 nF
2.2 uF
56 nH
5.1 nH
1 nF
100 pF
2.2 uF
12.55 nH
Bias
15
11
10
9
2
7
12
13
14
16
8
6
5
4
3
1
VREG
VMODE
56 pF
3.6 nH
2.2 uF
100 pF
12 pF
1 nF
5.6 pF
0
100 pF
33 nH
4.7 pF
5.6 nH
33 nH
4.7
F
V
CC
VCC = 3.0 V to 5.2 V
RF IN
RF IN: TETRA Modulation
RF OUT
V
CC
VREG (VACP) = 2.6 V on, 0 V off
25% duty cycle, 14.17 ms pulse width
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Evaluation Board Schematic
(Download Bill of Materials from www.rfmd.com.)
C3
1 nF
C2
2.2 uF
L4
56 nH
L5
4.7 nH
C6
1 nF
C8
100 pF
C5
2.2 uF
L6
12.55 nH
Bias
15
11
10
9
2
7
12
13
14
16
8
6
5
4
3
1
VREG
VMODE
C9
56 pF
L1
3.6 nH
C14
2.2 uF
C15
100 pF
C10
12 pF
C11
1 nF
C13
5.1 pF
VCC
R1
0
50
strip
J1
RF IN
VCC
C4
100 pF
50
strip
J2
RF OUT
2175400A
P1
1
2
3
CON3
GND
P1-1
VCC
P1-3
VREG
P2
1
2
3
CON3
GND
P2-3
VMODE
P2-1
VCC
L3
33 nH
C16
4.7 pF
L7
5.6 nH
L2
33 nH
C17
4.7
F
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Evaluation Board Layout
Board Size 2.0" x 2.0"
Board Thickness 0.028", Board Material FR-4
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