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Preliminary
Product Description
Ordering Information
Typical Applications
Features
Functional Block Diagram
RF Micro Devices, Inc.
7628 Thorndike Road
Greensboro, NC 27409, USA
Tel (336) 664 1233
Fax (336) 664 0454
http://www.rfmd.com
Optimum Technology Matching Applied
Si BJT
GaAs MESFET
GaAs HBT
Si Bi-CMOS
SiGe HBT
Si CMOS
GN
D
VC
C
1
VC
C
1
VC
C
B
IAS
2F0
16
1
13
14
15
GND
GND
RF IN
2
3
4
VR
EG
1
VMO
D
E
VR
EG
2
BIAS
G
N
D
GN
D
9
8
7
6
5
RF OUT
RF OUT
RF OUT
12
11
10
RF2192
3V 900MHZ LINEAR POWER AMPLIFIER
3V CDMA/AMPS Cellular Handsets
3V JCDMA Cellular Handsets
3V CDMA2000 Cellular Handsets
3V TDMA/GAIT Cellular Handsets
Spread-Spectrum Systems
Portable Battery-Powered Equipment
The RF2192 is a high-power, high-efficiency linear ampli-
fier IC targeting 3V handheld systems. The device is
manufactured on an advanced Gallium Arsenide Hetero-
junction Bipolar Transistor (HBT) process, and has been
designed for use as the final RF amplifier in dual-mode
3 V CDMA/AMPS and CDMA2000 handheld digital cellu-
lar equipment, spread-spectrum systems, and other
applications in the 800MHz to 960MHz band. The
RF2192 has a low power mode to extend battery life
under low output power conditions. The device is pack-
aged in a 16 pin, 4mmx4mm leadless chip carrier.
Single 3V Supply
29dBm Linear Output Power
37% Linear Efficiency
Low Power Mode
45 mA idle current
47% Peak Efficiency 31dBm Output
RF2192
3V 900MHz Linear Power Amplifier
RF2192 PCBA
Fully Assembled Evaluation Board
2
Rev A1 010830
3.75
3.75
+
1.50 SQ
4.00
4.00
1
0.45
0.28
3.20
1.60
0.75
0.50
12
INDEX AREA
3
1.00
0.90
0.75
0.65
0.05
0.00
NOTES:
5
Package Warpage: 0.05 max.
4
Pins 1 and 9 are fused.
Shaded Pin is Lead 1.
1
Dimension applies to plated terminal and is measured
0.10 mm and 0.25 mm from terminal tip.
2
The terminal #1 identifier and terminal numbering conv
shall conform to JESD 95-1 SPP-012. Details of termin
identifier are optional, but must be located within the z
indicated. The identifier may be either a mold or marke
feature.
3
0.80
TYP
2
1
Dimensions in mm.
Package Style: LCC, 16-Pin, 4x4
Preliminary
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Absolute Maximum Ratings
Parameter
Rating
Unit
Supply Voltage (RF off)
+8.0
V
DC
Supply Voltage (P
OUT
31dBm)
+5.2
V
DC
Mode Voltage (V
MODE
)
+4.2
V
DC
Control Voltage (V
REG
)
+3.0
V
DC
Input RF Power
+10
dBm
Operating Case Temperature
-30 to +110
C
Storage Temperature
-30 to +150
C
Moisture Sensitivity
Modified JEDEC Level 2
Parameter
Specification
Unit
Condition
Min.
Typ.
Max.
High Power State
(V
MODE
Low)
Case T= 25C, V
CC
= 3.4V, V
REG
= 2.85V,
V
MODE
= 0V to 0.5V, Freq= 824MHz to
849MHz (unless otherwise specified)
Frequency Range
824
849
MHz
Linear Gain
27
30
dB
Second Harmonic
-33
dBc
Third Harmonic
<-60
dBc
Maximum Linear Output Power
(CDMA Modulation)
29
dBm
Total Linear Efficiency
37
%
P
OUT
=29dBm
Adjacent Channel Power Rejec-
tion
-48
-44
dBc
ACPR @885kHz
-58
-56
dBc
ACPR @1980kHz
Input VSWR
2:1
Output VSWR
10:1
No damage.
6:1
No oscillations. > -70dBc
Noise Power
-133
dBm/Hz
At 45MHz offset
Low Power State
(V
MODE
High)
Case T= 25 C, V
CC
= 3.4V, V
REG
=2.85V,
V
MODE
= 1.8V to 3V, Freq= 824MHz to
849MHz (unless otherwise specified)
Frequency Range
824
849
MHz
Linear Gain
19
22
dB
Second Harmonic
-33
dBc
Third Harmonic
<-60
dBc
Maximum Linear Output Power
(CDMA Modulation)
16
20
dBm
Max I
CC
150
mA
P
OUT
=+16dBm (all currents included)
Adjacent Channel Power Rejec-
tion
-48
-46
dBc
ACPR @885kHz
< -60
-58
dBc
ACPR @1980kHz
Input VSWR
2:1
Output VSWR
10:1
No damage.
6:1
No oscillations. > -70dBc
Caution! ESD sensitive device.
RF Micro Devices believes the furnished information is correct and accurate
at the time of this printing. However, RF Micro Devices reserves the right to
make changes to its products without notice. RF Micro Devices does not
assume responsibility for the use of the described product(s).
Preliminary
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Parameter
Specification
Unit
Condition
Min.
Typ.
Max.
High Power State CDMA
2000 1x (V
MODE
LOW)
Case T = 25
o
C, V
CC
= 3.4V, V
REG
=2.85V.
V
MODE
= 0V to 0.5V, Freq=824MHz to
849MHz (unless otherwise specified)
Frequency Range
824
849
MHz
Linear Gain
29
dB
Pilot+ DCCH 9600
Maximum Linear Output Power
(CDMA 2000 Modulation)
26.5
dBm
2.5dB Backoff included in IS98D CCDF 1%
5.4dB Peak Average Ratio at CCDF 1%
Adjacent Channel Power Rejec-
tion
-47
dBc
ACPR@ 885kHz
<-60
dBc
ACPR@ 1.98MHz
Pilot+ FCH 9600+SCHO 9600
Maximum Linear Output Power
(CDMA 2000 Modulation)
29
dBm
4.5dB Peak Average Ratio at CCDF 1%
Adjacent Channel Power Rejec-
tion
-47
dBc
ACPR@ 885kHz
<-60
dBc
ACPR@ 1.98MHz
Low Power State CDMA
2000 1x (V
MODE
HIGH)
Case T = 25
o
C, V
CC
= 3.4V, V
REG
=2.85V.
V
MODE
= 1.8V to 3V, Freq=824MHz to
849MHz
Frequency Range
824
849
MHz
Linear Gain
22
dB
Pilot+ DCCH 9600
Maximum Linear Output Power
(CDMA 2000 Modulation)
16
20
dBm
5.4dB Peak to Average Ratio at CCDF 1%
Adjacent Channel Power Rejec-
tion
-48
dBc
ACPR@ 885kHz
<-85
dBc
ACPR@ 1.98MHz
Efficiency
15
%
P
OUT
=20dBm
Pilot+ FCH 9600+SCHO 9600
Maximum Linear Output Power
(CDMA 2000 Modulation)
16
20
dBm
4.5dB Peak to Average Ratio at CCDF 1%
Adjacent Channel Power Rejec-
tion
< -50
dBc
ACPR@ 885kHz
< -65
dBc
ACPR@ 1.98MHz
FM Mode
Case T = 25C, V
CC
= 3.4V, V
REG
=2.85V,
V
MODE
= 0V to 0.5V, Freq=824MHz to
849MHz (unless otherwise specified)
Frequency Range
824
849
MHz
Gain
30
dB
Second Harmonic
-33
dBc
Third Harmonic
<-60
dBc
Max CW Output Power
31
32
dBm
Total Efficiency (AMPS mode)
47
%
P
OUT
= 31dBm (room temperature)
Input VSWR
2:1
Output VSWR
10:1
No damage.
6:1
No oscillations. > -70dBc
Note: DCCH: Dedicated Control Channel
FCH:
Fundamental Channel
CCDF: Complementary Cumulative Distribution Function
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Parameter
Specification
Unit
Condition
Min.
Typ.
Max.
DC Supply
Supply Voltage
3.0
3.4
4.2
V
The maximum power out for V
CC
= 3.0V is
28dBm.
Quiescent Current
160
mA
V
MODE
= Low
45
70
mA
V
MODE
= High
V
REG
Current
10
mA
V
MODE
Current
1
mA
Turn On/Off Time
<40
s
Time between V
REG
turned on and PA
reaching full power. Turn on/off time can be
reduced by lowering the bypass capacitor
value on the V
REG
line.
Total Current (Power Down)
10
A
V
REG
=Low
V
REG
"Low" Voltage
0
0.5
V
V
REG
"High" Voltage
2.75
2.85
2.95
V
V
MODE
"Low" Voltage
0
0.5
V
V
MODE
"High" Voltage
1.8
2.85
3.0
V
Preliminary
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Pin
Function
Description
Interface Schematic
1
GND
Ground connection.
2
GND
Ground connection.
3
GND
Ground connection.
4
RF IN
RF input. An external 100pF series capacitor is required as a DC block.
In addition, shunt inductor and series capacitor are required to provide
2:1VSWR.
5
VREG1
Power Down control for first stage. Regulated voltage supply for ampli-
fier bias. In Power Down mode, both V
REG
and V
MODE
need to be LOW
(<0.5V).
6
VMODE
For nominal operation (High Power Mode), V
MODE
is set LOW. When
set HIGH, the driver and final stage are dynamically scaled to reduce
the device size and as a result to reduce the idle current.
7
VREG2
Power Down control for the second stage. Regulated voltage supply for
amplifier bias. In Power Down mode, both V
REG
and V
MODE
need to be
LOW (< 0.5V).
8
BIAS GND
Bias circuitry ground. See application schematic.
9
GND
Ground connection.
10
RF OUT
RF output and power supply for final stage. This is the unmatched col-
lector output of the second stage. A DC block is required following the
matching components. The biasing may be provided via a parallel L-C
set for resonance at the operating frequency of 824MHz to 849MHz. It
is important to select an inductor with very low DC resistance with a 1A
current rating. Alternatively, shunt microstrip techniques are also appli-
cable and provide very low DC resistance. Low frequency bypassing is
required for stability.
11
RF OUT
Same as pin 10.
See pin 10.
12
RF OUT
Same as pin 10.
13
2FO
Harmonic trap. This pin connects to the RF output but is used for pro-
viding a low impedance to the second harmonic of the operating fre-
quency. An inductor or transmission line resonating with an on chip
capacitor at 2fo is required at this pin.
14
VCC BIAS
Power supply for bias circuitry. A 100pF high frequency bypass capaci-
tor is recommended.
15
VCC1
Power supply for first stage.
16
VCC1
Same as Pin 15.
Pkg
Base
GND
Ground connection. The backside of the package should be soldered to
a top side ground pad which is connected to the ground plane with mul-
tiple vias. The pad should have a short thermal path to the ground
plane.
GND1
RF IN
VCC1
From
Bias
Stages
100 pF
RF OUT
From Bias
Stages
Preliminary
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Evaluation Board Schematic
US - CDMA
(Download Bill of Materials from www.rfmd.com.)
C25
4.7
F
C30
C6
100 pF
C5
100 pF
C27
100 pF
R1
0
C13
100 pF
C1**
C14**
C3
100 pF
L1*
C4
100 pF
C28
10 nF
C2
4.7 uF
C17
2.4 pF
R3
0
TL
1
TL
2
C26
4.7
F
* L1 is a High Q inductor (i.e., Coilcraft 0805HQ-series).
**C1 and C14 are High Q capacitors
(i.e., Johanson C-series).
16
1
13
14
15
2
3
4
9
8
7
6
5
12
11
10
L4
39 nH
R4
0
L2
5.6 nH
J1
RF IN
VCC
L5
1 nH
J4
RF OUT
VREG
VMODE
TL
5
C24
12 pF
TL
3
Transmission
Line Length
CDMA (US)
TL
1
15 mils
TL
2
350 mils
TL
3
105 mils
TL
5
85 mils
CDMA (US)
100
9.1
20
9.1
Board
C30 (pF)
C1 (pF)
L1 (nH)
C14 (pF)
R2
510
C9
100 pF
Preliminary
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Evaluation Board Layout
2.0" x 2.0"
Board Thickness 0.031", Board Material FR-4, Multi-Layer, Ground Plane at 0.015"
Preliminary
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