8-103

Product Description

Ordering Information

Typical Applications

Features

Functional Block Diagram

RF Micro Devices, Inc.
7628 Thorndike Road
Greensboro, NC 27409, USA

Tel (336) 664 1233

Fax (336) 664 0454

http://www.rfmd.com

Optimum Technology Matching® Applied

Si BJT

GaAs MESFET

GaAs HBT

Si Bi-CMOS

SiGe HBT

Si CMOS

InGaP/HBT

GaN HEMT

SiGe Bi-CMOS

IF2+

IF2-

BYPASS

IF1+

IF1-

X I

GND3

ISET1

ISET2

A O

GND1B 5

VCC1 4

LNA IN 3

MIX GAIN 2

LNA GAIN 1

SEL

IP SET

ENABLE

L
O

VCC2

RF2461

CDMA/FM LOW NOISE AMPLIFIER/MIXER

900MHz DOWNCONVERTER

· CDMA/FM (AMPS) Systems
· Dual-Mode TACS/JCDMA Systems
· General Purpose Downconverter

· Commercial and Consumer Systems
· Portable Battery-Powered Equipment

The RF2461 is a receiver front-end designed for the
receive section of dual-mode CDMA/FM cellular applica-
tions. It is designed to amplify and downconvert RF sig-
nals, while providing 30dB of stepped gain control range.
Features include digital control of LNA gain, mixer gain,
and power down mode. Another feature of the chip is
adjustable IIP3 of the LNA and mixer using an off-chip
current setting resistor. Noise figure, IP3, and gain are
designed to be compatible with the IS-98B interim stan-
dard for CDMA cellular communications. The IC is manu-
factured on an advanced Silicon Germanium HBT
process and is in a 4mmx4mm, 20-pin, leadless chip car-
rier.

· Complete Receiver Front-End
· Stepped LNA/Mixer Gain Control
· Adjustable LNA/Mixer Bias Current
· Adjustable LNA/Mixer IIP3
· Meets IMD Tests with Three Gain

States/Two Logic Control Lines

RF2461

CDMA/FM Low Noise Amplifier/Mixer 900MHz
Downconverter

RF2461 PCBA

Fully Assembled Evaluation Board

Rev B3 030124

Dimensions in mm.

Note orientation of package.

12°

MAX

-C-

0.05

1.00
0.90

0.05 C

0.60
0.24 TYP

0.20

0.10

C A B

0.65
0.30

4 PLCS

2.10 SQ.

0.23
0.13

4 PLCS

0.50

0.75
0.50

NOTES:

Shaded lead is Pin 1.

Dimension applies to plated terminal:
to be measured between 0.02 mm and
0.25 mm from terminal end.

0.15 C A

2 PLCS

-A-

4.00

3.75

2 PLCS

0.15 C

4.00

0.15 C B

2 PLCS

-B-

3.75

2 PLCS

0.15 C

Package Style: LCC, 20-Pin, 4x4

8-104

RF2461

Rev B3 030124

Absolute Maximum Ratings

Parameter

Rating

Unit

Supply Voltage

-0.5 to +5.0

Input LO and RF Levels

dBm

Operating Ambient Temperature

-40 to +85

°C

Storage Temperature

-40 to +150

°C

Parameter

Specification

Unit

Condition

Min.

Typ.

Max.

Overall

T = 25°C, V

=3.0V

RF Frequency Range

800

869 to 894

1000

MHz

832 to 870

LO Frequency Range

700

954 to 979

1000

MHz

722 to 760

IF Frequency Range

0.1

250

MHz

Power Down Current

LNA - CDMA/JCDMA

LNA Gain=1

Gain

14.0

15.0

16.0

IPSET=1

13.5

14.5

15.0

IPSET=0

Noise Figure

1.8

IPSET=1

1.8

IPSET=0

Input IP3

+9.0

+11.0

dBm

IPSET=1

+7.0

+9.0

dBm

IPSET=0

Current

6.5

IPSET=1

5.0

IPSET=0

LNA Bypass -

CDMA/JCDMA

LNA Gain=0

Gain

-8

-6

Noise Figure

Input IP3

+16.0

+18.0

dBm

Current

Mixer - CDMA

balanced load. IIP3 is adjustable.

Decreasing R4/R5 will increase IIP3.

LO=965MHz@-10dBm, IF=85.38MHz

Gain

14.5

Mixer Preamp ON, Mix Gain=1

5.8

Mixer Preamp OFF, Mix Gain=0

Noise Figure

5.5

Mixer Preamp ON, Mix Gain=1

Mixer Preamp OFF, Mix Gain=0

Input IP3

+3.0

+4.0

dBm

Mixer Preamp ON, Mix Gain=1

+13.0

+14.0

dBm

Mixer Preamp OFF, Mix Gain=0

Current

Mixer Preamp ON, Mix Gain=1

Mixer Preamp OFF, Mix Gain=0

Mixer - JCDMA

balanced load. IIP3 is adjustable.

Decreasing R4/R5 will increase IIP3.

LOIN=741MHz@-4dBm, IF=110MHz

Gain

Mixer Preamp ON, Mix Gain=1

2.5

4.0

Mixer Preamp OFF, Mix Gain=0

Noise Figure

5.5

Mixer Preamp ON, Mix Gain=1

Mixer Preamp OFF, Mix Gain=0

Input IP3

+2.0

+3.0

dBm

Mixer Preamp ON, Mix Gain=1

+10.0

+12.0

dBm

Mixer Preamp OFF, Mix Gain=0

Current

Mixer Preamp ON, Mix Gain=1

Mixer Preamp OFF, Mix Gain=0

Caution! ESD sensitive device.

RF Micro Devices believes the furnished information is correct and accurate
at the time of this printing. However, RF Micro Devices reserves the right to
make changes to its products without notice. RF Micro Devices does not
assume responsibility for the use of the described product(s).

8-105

RF2461

Rev B3 030124

Parameter

Specification

Unit

Condition

Min.

Typ.

Max.

Local Oscillator Input

Input Level

-10

dBm

LO to IF Isolation

-70

LO to LNA Isolation

-60

Any gain state.

Power Supply

Voltage

2.65

3.0

3.15

Cascade -
High Gain Mode

LNA High Gain/Mixer High Gain.

LNA Gain=1, Mix Gain=1.

Assumes 3dB Image filter insertion loss.

Gain

23.5

Noise Figure

2.4

Input IP3

-11

-9

dBm

Current

Cascade -
Mid Gain Mode

LNA High Gain/Mixer Low Gain.

LNA Gain=1, Mix Gain=0.

Assumes 3dB Image filter insertion loss.

Gain

16.5

Noise Figure

4.9

Input IP3

dBm

Current

Cascade -
Low Gain Mode

LNA Low Gain/Mixer High Gain.

LNA Gain=0, Mix Gain=1.

Assumes 3dB Image filter insertion loss.

Gain

Noise Figure

15.5

Input IP3

11.8

dBm

Current

Cascade -
Ultra-Low Gain Mode

LNA Low Gain/Mixer Low Gain.

LNA Gain=0, Mix Gain=0.

Assumes 3dB Image filter insertion loss.

Gain

-7

-4.5

-3

Noise Figure

22.5

Input IP3

+14

+20

dBm

Current

Cellular CDMA, IPSET=1

Mode

LNA GAIN

MIX GAIN

High Gain

Recommended for IMD Tests 1 and 2

Mid Gain

Recommended for IMD Tests 3 and 4

Low Gain

Recommended for IMD Tests 5 and 6

Ultra-Low Gain

Alternative Lowest Current Mode for

IMD Tests 5 and 6

8-106

RF2461

Rev B3 030124

Pin

Function

Description

Interface Schematic

LNA GAIN

Controls the bypass feature of the LNA. A logic low (<1.0V) selects the

bypass mode. A logic high (>2.0V) turns on the LNA.

MIX GAIN

Controls the bypass feature of the mixer preamp. A logic low (<1.0V)

selects the bypass mode. A logic high (>2.0V) turns on the preamp-

preamp.

LNA IN

LNA input pin.

VCC1

VCC pin for all circuits except the LO. Buffer/bias circuitry.

GND1B

LNA emitter. This pin provides the DC path to ground for the LNA. A

lumped element or a transmission line inductor can be placed between

this pin and ground to degenerate the LNA. This will decrease the gain

and increase the IP3 of the LNA. As the value of inductance is

increased, these effects will become more pronounced.

LNA OUT

LNA output pin.

See pin 3.

ISET2

An external resistor R2 connected to this pin sets the current of the

preamp and the mixer.

ISET1

An external resistor R3 connected to this pin sets the current of the

LNA when IP SET is high (see pin 19).

GND3B

Ground pin for preamp circuit. A 3.3nH inductor is used between pin 9

and ground to degenerate the mixer preamp. Degenerating the preamp

will reduce the gain, increase the IP3 and affect the preamp input

impedance.

MIX IN

Mixer preamp input pin.

See pin 9.

IF1-

Second differential output pin for the first mixer.

See pin 12.

IF1+

First differential output pin for the first mixer. Open collector. A current

combiner external network performs a differential to single-ended con-

version and sets the output impedance. A DC blocking cap must be

present if the IF filter input has a DC path to ground. Mixer (IF2+ and

IF-) needs to "see" a differential impedance between 2k

to 4k

BYPASS

Bypass pin for the LO bias reference.

IF2-

Second differential output pin for the second mixer.

See pin 15.

LNA GAIN

MIX GAIN

LNA IN

LNA OUT

GND1B

MIX IN

GND3B

VCC2

IF1-

IF1+

8-107

RF2461

Rev B3 030124

Pin

Function

Description

Interface Schematic

IF2+

First differential output pin for the second mixer. Open collector. A cur-

rent combiner external network performs a differential to single-ended

conversion and sets the output impedance. A DC blocking cap must be

present if the IF filter input has a DC path to ground. Mixer (IF2+ and

IF2-) needs to "see" a differential impedance between 2k

to 4k

VCC2

VCC pin for the LO buffer/bias circuitry.

LO IN

LO limiter input pin.

ENABLE

This pin is used to enable or disable the RF2461. A logic high (>2.0V)

enables the circuitry. A logic low (<1.0V) disables the circuitry.

IP SET

Controls the setting of the LNA current. A logic low (<1.0V) selects the

internal resistance (49.5k

), resulting in an LNA current of 5mA. A

logic high (>2.0V) selects the external resistance at pin 8.

IF SEL

Determines which IF port is active. A logic low (<1.0V) activates IF1

and deactivates IF2. A logic high (>2.0V) activates IF2 and deactivates

IF1. Mixers are identical. Either IF output may be used for CDMA or

AMPS applications.

Pkg

Base

GND

Ground connection. The backside of the package should be soldered to

a top side ground pad which is connected to the ground plane with mul-

tiple vias.

IF2-

IF2+

LO IN

ENABLE

IP SET

IF SEL

8-108

RF2461

Rev B3 030124

Application Schematic

VCC1

100 pF

33 nF

16 nH

4.3 nH

IF SEL

100 pF

VCC1

100 pF

strip

620

4 pF

100 pF

0.1

VCC1

22 k

47 k

3.3 nH

LNA GAIN

MIX GAIN

VCC2
VCC1

NOTE:
Microstrip Inductor, Z

= 50

, L = 102 mils

suggested compared values.

Filter

33 nF

47 nH

Filter

IF+
IF-

Filter

IF2+
IF2-

LO IN

LNA IN

7.5 nH

strip

L=130 mils

W=12 mils

=50

ENABLE

IP SET

*This resistor improves NF and IIP3 for

= 3.0 V.

BYPASS

See

Note 4

See

Note 5

See

Note 3

See

Note 1

See

Note 6

See

Note 8

See

Note 8

See

Note 8

See

Note 8

See

Note 7

See Note 2

See Note 8

See

Note 10

See Note 11

See

Note 9

NOTES:
1. DC blocking capacitor.
2. LNA emitter degenerator. As the value of inductance is increased, the gain will decrease, and the IIP3 will increase.
3. Mixer preamp degeneration inductor. As the value of inductance is increased, the gain will decrease, and the IIP3 will increase.
4. An external resistor connected to this pin sets the current of the preamp and the mixer. Higher resistance to ground results in lower current. See chart at end of datasheet.
5. An external resistor connected to this pin sets the current of the LNA when IPSET is high. Higher resistance to ground results in lower current. See chart at end of datasheet.
6. Mixer input matching inductor.
7. LO input matching resistor.
8. Bypass capacitor.
9. LNA output matching and bias choke.
10. For stability of the LNA.
11. LNA input and output matching.
12. Low pass path to ground for two-tone beat frequency for optimum IIP3 of LNA.

See Note 11

See Note 12

See Note 8

Output Interface Network

L1, C1, and R form a current combiner which performs
a differential to single-ended conversion at the IF fre-
quency and sets the output impedance. In most cases,
the resonance frequency is independent of R and can
be set according to the following equation:

Where C

is the equivalent stray capacitance and

capacitance looking into pins 11 and 12. An average
value to use for C

is 2.5pF to 3pF.

R can then be used to set the output impedance
according to the following equation:

where R

OUT

is the desired output impedance and R

the parasitic equivalent parallel resistance of L1.

C1 should be chosen as high as possible (not greater
than 15pF), while maintaining an R

of L1 that allows

for the desired R

OUT

L2 and C2 serve dual purposes. L2 serves as an out-
put bias choke, and C2 serves as a series DC block.

In addition, L2 and C2 may be chosen to form an
impedance matching network if the input impedance of
the IF filter is not equal to ROUT. Otherwise, L2 is cho-
sen to be large, and C2 is chosen to be large if a DC
path to ground is present in the IF filter, or omitted if the
filter is DC blocked.

(C1 + C

)

R =

4 R

OUT

(

)

-1

8-109

RF2461

Rev B3 030124

Evaluation Board Schematic - CDMA

LO@965MHz, RF@880MHz, IF@85MHz

(Download Bill of Materials from www.rfmd.com.)

VCC1

strip

33 nF

16 nH

strip

4.3 nH

strip

IF SEL

ENABLE

IP SET

C16

100 pF

strip

390 nH

C15

100 pF

strip

C14

10 pF

strip

470 nH

strip

10 k

C13

11 pF

C12

11 pF

C11

100 pF

strip

10 pF

strip

470 nH

10 k

11 pF

strip

C10

11 pF

390 nH

VCC1

100 pF

strip

620

7.5 nH

4 pF

strip

100 pF

0.1

VCC1

18 k

47 k

3.3 nH

strip

33 nF

strip

47 nH

strip

CON3

P1-3

LNA GAIN

GND

P1-1

MIX GAIN

CON3

P2-3

ENABLE

P2-2

IP SET

P2-1

IF SEL

CON3

P3-1

VCC1

GND

P3-3

VCC2

VCC2
VCC1

Note: R14 improves NF and IIP3 for V

= 3.0 V

R14

strip

L=130 mils

W=12 mils

=50

LO IN

447 pS Electrical Delay

0.13 dB Line Loss

LNA IN

329 pS Electrical Delay

0.10 dB Line Loss

LNA GAIN

MIX GAIN

LNA OUT

498 pS Electrical Delay

0.15 dB Line Loss

IF1 OUT

348 pS Electrical Delay @ 110 MHz

0.03 dB Line Loss

MIXER IN

320 pS Electrical Delay @ 880 MHz

0.10 dB Line Loss

IF2 OUT

348 pS Electrical Delay @ 110 MHz

0.03 dB Line Loss

BYPASS

100 pF

8-110

RF2461

Rev B3 030124

Evaluation Board Schematic - JCDMA

LO@741MHz, RF@851MHz, IF@110MHz

VCC1

strip

33 nF

16 nH

strip

4.3 nH

strip

IF SEL

ENABLE

IP SET

C16

100 pF

strip

270 nH

C15

100 pF

strip

C14

7 pF

strip

330 nH

strip

4.3 k

C13

9 pF

C12

10 pF

C11

100 pF

strip

7 pF

strip

330 nH

4.3 k

9 pF

strip

C10

11 pF

270 nH

VCC1

100 pF

strip

620

7.5 nH

4 pF

strip

100 pF

0.1

VCC1

18 k

33 k

7.5 nH

strip

33 nF

strip

30 nH

strip

CON3

P1-3

LNA GAIN

GND

P1-1

MIX GAIN

CON3

P2-3

ENABLE

P2-2

IP SET

P2-1

IF SEL

CON3

P3-1

VCC1

GND

P3-3

VCC2

VCC2
VCC1

Note: R14 improves NF and IIP3 for V

= 3.0 V

R14

strip

L=130 mils

W=12 mils

=50

LO IN

447 pS Electrical Delay

0.13 dB Line Loss

LNA IN

329 pS Electrical Delay

0.10 dB Line Loss

LNA GAIN

MIX GAIN

LNA OUT

498 pS Electrical Delay

0.15 dB Line Loss

IF1 OUT

348 pS Electrical Delay @ 110 MHz

0.03 dB Line Loss

MIXER IN

320 pS Electrical Delay @ 880 MHz

0.10 dB Line Loss

IF2 OUT

348 pS Electrical Delay @ 110 MHz

0.03 dB Line Loss

BYPASS

100 pF

8-113

RF2461

Rev B3 030124

Condition T=25

C, VCC=2.75V, RF=880 and 881MHz, LO=965MHz @-10dBm

LNA Gain, Noise Figure and IIP3 versus I

LNA Only (LNA High Gain)

0.0

2.0

4.0

6.0

8.0

10.0

12.0

14.0

16.0

0.0

2.0

4.0

6.0

8.0

10.0

12.0

14.0

16.0

(mA)

Gain and Noise Figure (dB)

-20.0

-15.0

-10.0

-5.0

0.0

5.0

10.0

15.0

IIP3 (dBm)

Gain (dB)

NF (dB)

IIP3 (dBm)

Mixer Gain, Noise Figure and IIP3 versus I

Mixer (Mixer High Gain, LO=-7dBm)

-20.00

-15.00

-10.00

-5.00

0.00

5.00

10.00

15.00

20.00

25.00

10.00

15.00

20.00

25.00

30.00

35.00

40.00

(mA)

Gain and Noise Figure (dB)

-10.00

-5.00

0.00

5.00

10.00

IIP3 (dBm)

Gain (dB)

NF (dB)

IIP3 (dBm)

Resistor (R3) versus I

(mA) -

LNA Only (LNA High Gain)

0.0

20.0

40.0

60.0

80.0

100.0

120.0

140.0

160.0

180.0

200.0

0.0

2.0

4.0

6.0

8.0

10.0

12.0

14.0

16.0

(mA)

Resistor R3 (k

)

R3 (kohm)

Resistor (R2) versus I

- Mixer (Mixer High Gain,

LO=2170@-7dBm)

0.0

20.0

40.0

60.0

80.0

100.0

120.0

140.0

160.0

180.0

200.0

10.0

15.0

20.0

25.0

30.0

35.0

40.0

(mA)

Resistor R2 ( k

)

R2 (kohm)

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