10-39
10
IF
AMP
L
IE
R
S
Product Description
Ordering Information
Typical Applications
Features
Functional Block Diagram
RF Micro Devices, Inc.
7628 Thorndike Road
Greensboro, NC 27409, USA
Tel (336) 664 1233
Fax (336) 664 0454
http://www.rfmd.com
Optimum Technology Matching Applied
Si BJT
GaAs MESFET
GaAs HBT
Si Bi-CMOS
SiGe HBT
Si CMOS
1
2
3
4
8
7
6
5
IN+
IN-
GND
GC
VCC1
VCC2
OUT+
OUT-
GAIN
CONTROL
NOTES:
1. Shaded lead is pin 1.
2. All dimensions are exclusive of
flash, protrusions or burrs.
3. Lead coplanarity: 0.002 with
respect to datum "A".
0.012
6 MAX
0 MIN
0.021
+ 0.004
0.006
+ 0.002
0.192
+ 0.008
0.0256
0.118
+ 0.004 sq.
0.006
+ 0.003
0.034
-A-
RF2629
3V CDMA/FM TRANSMIT AGC AMPLIFIER
3V CDMA/FM Cellular Systems
3V CDMA PCS Systems
3V TDMA Cellular/PCS Systems
Supports Dual-Mode AMPS/CDMA
Supports Dual-Mode TACS/CDMA
Portable Battery-Powered Equipment
The RF2629 is a complete AGC amplifier designed for
the transmit section of 3V dual-mode CDMA/FM cellular
and PCS applications. It is designed to amplify IF signals
while providing more than 84dB of gain control range.
Noise Figure, IP3, and other specifications are designed
for CDMA and dual mode CDMA/AMPS handsets. This
circuit is designed as part of the RFMD CDMA Chip Set,
consisting of this Transmit IF AGC Amp, a Transmit
Upconverter, a Receive LNA/Mixer, and a Receive IF
AGC Amp. The IC is manufactured on an advanced high
frequency Silicon Bipolar process and is packaged in a
standard miniature 8-lead plastic MSOP package.
Supports Dual Mode Operation
Supports PCS and Cellular Applications
-48dB to +38dB Gain Control Range
Single 3V Power Supply
12MHz to 175MHz Operation
Miniature Surface Mount Package
RF2629
3V CDMA/FM Transmit AGC Amplifier
RF2629 PCBA
Fully Assembled Evaluation Board
10
Rev B4 010720
Package Style: MSOP-8
10-40
RF2629
Rev B4 010720
10
IF
AMP
L
IE
R
S
Absolute Maximum Ratings
Parameter
Rating
Unit
Supply Voltage
-0.5 to +7.0
V
DC
Control Voltage
-0.5 to +5.0
V
Input Power Levels
+10
dBm
Operating Ambient Temperature
-40 to +85
C
Storage Temperature
-40 to +150
C
Parameter
Specification
Unit
Condition
Min.
Typ.
Max.
Overall
T = 25C, 130MHz, V
CC
=3.0V, Pin=-40dBm,
Z
S
=1k
, Z
L
=1k
, 1k
External Output Ter-
minating Resistor (Effective Z
L
= 500
) (See
Application Example)
Frequency Range
12 to 175
MHz
Maximum Gain
+35
+38
dB
V
GC
= 2.3V
Minimum Gain
-48
-45
dB
V
GC
= 0.3V
Gain Slope
57
dB/V
Measured in 0.5V increments
Gain Control Voltage Range
0 to 2.4
V
DC
Gain Control Input Impedance
30
k
Noise Figure
10.5
13
dB
At maximum gain and 130MHz
Input IP3
-26
-28
-25
-26
dBm
dBm
At +10dB gain and referenced to 1k
,
Pin=-45dBm per tone
At +35dB gain and referenced to 1k
,
Pin=-45dBm per tone
Input Impedance
1
k
Differential
Stability (Max VSWR)
10:1
Spurious< -70dBm
Power Supply
Voltage
2.7 to 3.3
V
Current Consumption
23
25
mA
Maximum gain, V
CC
= 3.0V
Current Consumption
22
24
mA
Minimum gain, V
CC
= 3.0V
Caution! ESD sensitive device.
RF Micro Devices believes the furnished information is correct and accurate
at the time of this printing. However, RF Micro Devices reserves the right to
make changes to its products without notice. RF Micro Devices does not
assume responsibility for the use of the described product(s).
10-41
RF2629
Rev B4 010720
10
IF
AMP
L
IE
R
S
Pin
Function
Description
Interface Schematic
1
IN+
Balanced input pin. This pin is internally DC-biased and should be DC
blocked if connected to a device with a DC level, other than V
CC
,
present. A DC to connection to V
CC
is acceptable. For single-ended
input operation, one pin is used as an input and the other input is AC-
coupled to ground. The balanced input impedance is 1k
, while the
single-ended input impedance is 500
.
2
IN-
Same as pin 2, except complementary input.
See pin 1 schematic.
3
GND
Ground connection. For best performance, keep traces physically short
and connect immediately to ground plane.
4
GC
Analog gain adjustment for all amplifiers. Valid control ranges are from
0V to 3.0V. Maximum gain is selected with 3.0V. Minimum gain is
selected with 0V. These voltages are valid only for a 3.3k
DC source
impedance.
5
OUT-
Balanced output pin. This is an open-collector output, designed to
operate into a 500
balanced load. The load sets the operating imped-
ance, but an external choke or matching inductor to V
CC
must also be
supplied in order to correctly bias this output. This bias inductor is typi-
cally incorporated in the matching network between the output and next
stage. Because this pin is biased to V
CC
, a DC-blocking capacitor must
be used if the next stage's input has a DC path to ground.
6
OUT+
Same as pin 5, except complementary output.
See pin 5 schematic.
7
VCC1
Supply voltage pin. External bypassing is required. The trace length
between the pin and the bypass capacitors should be minimized. The
ground side of the bypass capacitors should connect immediately to
ground plane. Pins 7 and 8 may share one bypass capacitor if trace
lengths are kept minimal.
8
VCC2
Same as pin 7.
580
V
CC
580
CDMA-
CDMA+
23.5 k
15 k
12.7 k
V
CC
OUT-
OUT+
10-42
RF2629
Rev B4 010720
10
IF
AMP
L
IE
R
S
Application Schematic
Evaluation Board Schematic
(Download Bill of Materials from www.rfmd.com.)
1
2
3
4
8
7
6
5
GAIN
CONTROL
10 nF
10 nF
IN+
IN-
Measurement
Reference Plane
Z
IN
=1 k
Z
S
=1 k
R2:
1 k
C2
C2
L1
C1
L1
C1
V
CC
10 nF
V
CC
CDMA Filter
OUT+
OUT-
Z
OUT
=1 k
Z
LOAD
=1 k
Z
LOAD,EFF
=500
Measurement
Reference Plane
10 nF
3.3 k
GAIN
R2 sets the balanced output impedance to 1 k
. L1 and C2
serve dual purposes. L1 serves as an output bias choke, and C2
serves as a series DC block. In addition, the values of L1 and
C2 may be chosen to form an impedance matching network if
the load impedance is not 1 k
. Otherwise, the values of L1 and
C1 are chosen to form a parallel-resonant tank circuit at the IF
when the IF filter's input impedance is 1 k
.
GAIN
CONTROL
C8
33 pF
L3
100nH
L4
100nH
C6
10 nF
C7
10 nF
R1
3.3 k
T1
C3
5 pF
C1
10 nF
C4
5 pF
C2
10 nF
L1
270 nH
L2
270 nH
1
2
3
4
8
7
6
5
T2
C5
1 nF
50
strip
J2
SMA
OUT
50
strip
J1
SMA
CDMA
1
2
3
P1-1
P1-3
VCC
GND
P1
GC
GC
VCC
2629400, Rev A
VCC
C10
10 nF
R2
510
R3
510
1
1
C11
22 pF
C12
22 pF
C9
33 pF
10-43
RF2629
Rev B4 010720
10
IF
AMP
L
IE
R
S
Evaluation Board Layout
Board Size 2.750" x 2.000"
Board Thickness 0.031", FR-4
10-44
RF2629
Rev B4 010720
10
IF
AMP
L
IE
R
S
Gain versus Gain Control Voltage
(VCC = 3.0 V, 130 MHz)
-60.0
-50.0
-40.0
-30.0
-20.0
-10.0
0.0
10.0
20.0
30.0
40.0
50.0
60.0
0.0
0.5
1.0
1.5
2.0
2.5
GC (Volts)
Gain
(dB)
-30 C
+25 C
+85 C
IIP3 versus Gain
(VCC = 3.0 V, 130 MHz)
-50.0
-40.0
-30.0
-20.0
-10.0
0.0
10.0
-60.0
-40.0
-20.0
0.0
20.0
40.0
60.0
Gain (dB)
IIP3
(dB)
+25 C
+85 C
-30 C
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