sames
SA9101
FEATURES
PCM FRAME ALIGNER
1/40
n
Frame alignment/synthesis for PCM30
double frame and CRC-multiframe
format.
n
Meets CCITT Rec.G704
n
Interface to route selectable between
HDB3 and fibre optical
n
HDB3 outputs switchable between fully
bauded and half bauded format
n
Error checking via CRC4 procedure
n
Insertion and extraction of alarms and
facility signals
n
Selectable system - clock (4096 kHz/
8192 kHz)
n
Selectable Interface mode (2048/4096
kBit/s) to system internal highway
n
Programmable offsets for receive and
transmit data
n
Two frame receive buffer for receive
route clock wander and jitter
compensation
n
Slip detection and direction indication
n
Extended HDB3 error detection
M71-1797
PDS039-SA9101-001
REV.A 09-09-94
DESCRIPTION:
The SA9101 (Frame Alignment unit for PCM30 Systems) is a C-MOS device which
implements the interface to PCM30 Transmission Systems.
In the receive direction, the device performs HDB3 decoding, Frame alignment
(selectable between doubleframe and CRC-Multiframe) and extraction of signalling
data.
Wander absorption between the PCM carrier and the system internal highway is
performed using an internal 2 frame memory. The incoming data stream is monitored
and
n
Error counters for code errors
(switchable to "S
i
zeros counter"), frame
errors and CRC4 errors
n
Sub-multiframe assigned CRC Error
indication with possibility of automatic
insertion in Si-bit position of outgoing
multiframe.
n
Simplified data transfer between
SA9101 and controller, supported by
data stacks for receive and transmit
signalling data, selectable interrupt-
sources and DMA facilities.
n
Double frame marker for serial data
extraction support
n
Repeated transmission of signalling
data, if not updated.
n
Three transparent modes for timeslot 0
in transmit direction
n
Transparent mode for receive direction
n
HDB3 error indication
n
Idle channel data insertion selectable
for any timeslot
n
Channel loopback capabilities, test and
diagnostic capabilities
n
Parity checks
SA9101
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Description (Cont.)
status and error conditions are reported through the P interface. In the transmit
direction, Frame (and Multiframe) alignment, signalling data insertion and HDB3 coding
is performed.
If Multiframe format is enabled, CRC4 extraction and checking are carried out in the
receive direction and CRC4 data is inserted in the transmit direction.
Stacks for transmit and receive signalling data with DMA capability as well as maskable
interrupt sources simplify interfacing to microcontrollers.
Alarm simulation capabilities and selectable channel-loopback, support system
diagnostics.
Different transparent modes for timeslot 0 in transmit direction simplify system test and
data transmission through the system.
Advanced algorithms for synchronisation of doubleframe and CRC4 multiframe format
data, and monitoring of frame and doubleframe formats minimise loss of data.
Control Registers allow different control settings through the P interface.
Advanced C-MOS Technology ensures low power consumption and high reliability.
The device is upwards compatible with the Siemens ACFA (PEB 2035 V4.1) in PCM30
mode.
Package: DIP/DIC - 40
Package: PLCC - 44
PIN CONNECTIONS
SA9101
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4/40
Operational Characteristics
T
A
= 25C; V
DD
= 5V 5%; V
SS
= 0V
Limit Values
Parameter
Symbol
Min.
Max.
Unit
Input capacitance
C
IN
10
pF
Output capacitance
C
OUT
15
pF
I/O
C
IO
20
pF
Absolute Maximum Ratings*
Parameters
Symbol
Min
Max
Unit
Supply Voltage
V
DD
- V
SS
-0.3
6
V
Voltage on any I/O pin
V
I
/V
O
-0.3
V
DD
+0.3
V
Current on any I/O pin
I
I
/I
O
20
mA
Storage Temperature
T
STG
-55
+125
C
Operating Temperature
T
OP
-10
+70
C
Package Power Dissipation
P
D
1000
mW
*Stress above those listed under "Absolute Maximum Ratings" may cause permanent damage
to the device. This a stress rating only. Functional operation of the device at these or any other
condition above those indicated in the operational sections of this specification, is not implied.
Exposure to Absolute Maximum Ratings for extended periods may affect device reliability.
DC Operational Characteristics
V
DD
= 5V, T = 10C..+70C
Limit Values
Parameter
Symbol
Min.
Max.
Unit
Remarks
Supply Voltage
V
DD
-V
SS
4.5
5.5
V
Supply Current (dynamic)
I
DD
100
mA
Standby Current
I
DDS
100
A
Inputs
High Voltage
V
IH
2.4
V
Low Voltage
V
IL
0.8
V
Leakage Current
I
LEAK
-5
5
A
V
I
=0..V
DD
Input ACKNQ
Pullup Current
-I
PUP
10
30
A
V
I
=0
Outputs
High Voltage
V
OH
2.8
V
I
OH
=-1mA
Low Voltage
V
OL
0.4
V
I
OL
=2mA
Bidirects
Input High Voltage
V
IH
2.4
V
Input Low Voltage
V
IL
0.8
V
Tristate Current
I
LEAK
-10
10
A
V
I
=0..V
DD
Output High Voltage
V
OH
2.8
V
I
OH
=-1mA
Output Low Voltage
V
OL
0.4
V
I
OL
=2mA
ELECTRICAL CHARACTERISTICS
SA9101
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PIN DESCRIPTION
Pin No.
DIL
PLCC
AINT/DFPY
O
3
5
Alarm interrupt/Double Frame Parity
ACKNLQ
I
32
36
DMA Acknowledge
A[3-0]
I
19-16
21-18
Address Bus
CEQ
I
22
26
Chip Enable
CHPAR/DFM
O
4
6
Receive Channel Parity/
Double Frame Marker
COS
I
23
27
Carrier out of Service
DRA
I
27
31
Receive Data in Plus
DRB
I
26
30
Receive Data in Minus
DRO
O
2
4
Receive Data Out
DXA
O
38
42
Transmit Data Out Plus
DXB
O
39
43
Transmit Data Out Minus
DXI
I
30
34
Transmit Data In
D[7-0]
B
14-7
16-9
Data Bus
OPIN
I
29
33
Receive Optical Interface Data
OPOUT
O
6
8
Transmit Optical Interface Data
RCAS/RREQ
O
35
39
Receive TS16 Signal/Receive DMA
Interrupt Request
RCLK
I
25
29
Receive Route Clock
RDQ
I
20
22
Read Enable
RESQ
I
31
35
Reset
RFSPQ
O
5
7
Receive Frame Synchronisation
Pulse
SCLK
I
24
28
System Clock
SYPQ
I
28
32
Synchronisation Pulse
TCAS/XREQ
O
36
40
Transmit TS16 Signal/Transmit DMA
Interrupt Request
V
DD
S
15
17
+5V Supply
V
SS
S
34
38
0V Ground
WRQ
I
21
25
Write Enable
XCHPAR
O
33
37
Transmit Channel Parity
XRCLK
O
37
41
Transmit Route Clock
XTOM
O
1
3
Test Data Output Minus
XTOP
O
40
44
Test Data Output Plus
Pin Name
Direction
Description
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