ADC1276X

0.18

m 14-BIT 10MSPS ADC

GENERAL DESCRIPTION

The adc1276x is a CMOS 14bit analog-to-digital converter (ADC). It converts the analog input signal into 14bit binary

digital codes at a maximum sampling rate of 10MHz.

The device is a monolithic ADC with an on-chip, high-performance, sample-and-hold Amplifier (SHA) and current

reference and voltage reference. The structure allows both differential and single-ended input.

FEATURES

-- Resolution : 14bit
-- Maximum Conversion Rate : 10MHz
-- Package Type : 48TSSOP
-- Power Supply : 3.3V
-- Power Consumption : 120mW (typical)
-- Reference Voltage : Internal reference
or 2V, 1V (dual reference)
-- Input Range : 0.5V 2.5V (2.0V

P-P

)

-- Differential Linearity Error :

1 LSB (min)

-- Integral Linearity Error :

8 LSB (max)

-- Signal to Noise & Distortion Ratio : 67dB (Typ)
-- Total Harmonic Distortion : 75dB (Typ)
-- Out of Range Indicator
-- Digital Output : CMOS Level
-- Operating Temperature Range : 0

C 70

TYPICAL APPLICATIONS

-- CCD Imaging (Copiers, Scanners, Cameras)
-- Medical Instruments
-- Digital Communication Systems
-- uADSL System

ADC1276X

0.18

m 14-BIT 10MSPS ADC

CORE PIN DESCRIPTION

Name

I/O Type

I/O Pad

Pin Description

REFTOP

phiar10_abb

Reference Top Output/Force (2.0V)

REFBOT

phiar10_abb

Reference Bottom Output/Force (1.0V)

BGR

phiar10_abb

BGR output (1.23V)

CML

phiar10_abb

Internal Bias

CML1

phiar10_abb

Internal Bias

AVDD33A

vdd3t_abb

Analog Power (3.3V)

AVBB33A

vbb3_abb

Analog Sub Bias

AVSS33A

vss3t_abb

Analog Ground

AINT

phiar10_abb

Analog Input +

(Input Range : 1.0V 2.0V)

AINC

phiar10_abb

Analog Input -

(Input Range : 1.0V 2.0V)

ITEST

phia_abb

open=use internal bias point

STBY

phicc_abb

= power saving (standby),

GND = normal

CKIN

phicc_abb

Sampling Clock Input

D[13:0]

phot4_abb

Digital Output

ORI

phot4_abb

Out of Range Indicator

AVBB33D

vbb3_abb

Digital Sub Bias

AVSS33D

vss3t_abb

Digital GND

AVDD33D

vdd3t_abb

Digital Power (3.3V)

I/O Type Abbr.
-- AI: Analog Input
-- DI: Digital Input
-- AO: Analog Output
-- DO: Digital Output
-- AP: Analog Power
-- AG: Analog Ground
-- DP: Digital Power
-- DG: Digital Ground
-- AB: Analog Bi-direction
-- DB: Digital Bi-direction

ADC1276X

0.18

m 14-BIT 10MSPS ADC

ABSOLUTE MAXIMUM RATINGS

Characteristic

Symbol

Value

Unit

Supply Voltage

4.5

Analog Input Voltage

AINT/AINC

to V

Digital Input Voltage

CLK

to V

Storage Temperature Range

Tstg

-40 to 125

Operating Temperature Range

Topr

-0 to 70

NOTES:
1. Absolute maximum rating specifies the values beyond which the device may be damaged permanently. Exposure to

ABSOLUTE MAXIMUM RATING conditions for extended periods may affect reliability. Each condition value is applied
with the other values kept within the following operating conditions and function operation under any of these conditions
is not implied.

2. All voltages are measured with respect to V

unless otherwise specified.

3. 100pF capacitor is discharged through a 1.5K

resistor (Human body model)

RECOMMENDED OPERATING CONDITIONS

Characteristics

Symbol

Min

Typ

Max

Unit

Supply Voltage

AVDD33A

AVDD33D

AVDD33R

3.15

3.3

3.45

Analog Input Voltage

AINT

AINC

0.5

1.5

2.5

Operating Temperature

Toper

NOTE: It is strongly recommended that all the supply pins (AVDD33A, AVDD33D, AVDD33R) be powered from the same

source to avoid power latch-up.

0.18

m 14-BIT 10MSPS ADC

ADC1276X

DC ELECTRICAL CHARACTERISTICS

Characteristics

Symbol

Min

Typ

Max

Unit

Test Conditions

Differential Nonlinearity

DNL

LSB

Internal Voltage Reference

REFTOP=2V

REFBOT=1V

Integral Nonlinearity

INL

LSB

Internal Voltage Reference

REFTOP=2V

REFBOT=1V

Offset Voltage

OFF

REFTOP=2V

REFBOT=1V

(Converter Specifications : AVDD33A=AVDD33D=AVDD33R=3.3V,

AVSS33A=AVSS33D=AVSS33R=0V, Toper=25

REFTOP=2V,

REFBOT=1V

unless

otherwise

specified)

AC ELECTRICAL CHARACTERISTICS

Characteristics

Symbol

Min

Typ

Max

Unit

Test Conditions

Maximum Conversion Rate

MHz

AIN=AINT-AINC

Dynamic Supply Current

IVDD

fc=10MHz

(without system load)

Signal-to-Noise & Distortion

Ratio

SNDR

AIN=1MHz,

Differential Input

Total Harmonic Distortion

THD

AIN=1MHz,

Differential Input

(Conversion

Specifications

AVDD33A=AVDD33D=AVDD33R=3.3V,

AVSS33A=AVSS33D=AVSS33R=0V,

Toper=25

REFTOP=2V,

REFBOT=1V

unless

otherwise

specified)

ADC1276X

0.18

m 14-BIT 10MSPS ADC

I/O

CHART

Index

AINT Input (V)

AINC Input (v)

Digital Output

0.5000 ~ 1.50012

1.5

00 0000 0000 0000

1LSB=0.122mV

0.50012 ~ 1.50024

1.5

00 0000 0000 0001

REFTOP=2.0V

0.5024 ~ 1.50037

1.5

00 0000 0000 0010

REFBOT=1.0V

8197

1.49988 ~ 1.5000

1.5

01 1111 1111 1111

8192

1.50000 ~ 1.50012

1.5

10 0000 0000 0000

8193

1.50012 ~ 1.50024

1.5

10 0000 0000 0001

16381

2.49963 ~ 2.49976

1.5

11 1111 1111 1101

16382

2.49976 ~ 2.49988

1.5

11 1111 1111 1110

16383

2.49988 ~ 2.5000

1.5

11 1111 1111 1111

TIMING DIAGRAM

AINT

Input Sampling Period

CKIN

DO[13:0]

0.18

m 14-BIT 10MSPS ADC

ADC1276X

FUNCTIONAL DESCRIPTION

1. The adc1276x is a CMOS four step pipelined Analog-to-Digital Converter. It contains 5-bit flash /D Converters,

4bit, two 3bit flash A/D converters three multiplying D/A Convertors. The N-bit ADC is composed of 2

-1

latched comparators, and multiplying DAC is composed of 2*(2

+1) capacitors and two fully-differential

amplifiers.

2. The adc1276x operates as follows. During the first "L" cycle of external clock the analog input data is sampled,

and the input is held from the rising edge of the external clock, which is fed to the first 5-bit flash ADC, and the

first multiplying DAC. Multiplying DAC reconstructs a voltage corresponding to the first 5-bit ADC's output, and
finally amplifies a residue voltage by 2

. Thesecond and third flash ADC, and MDAC are worked as same

manner. Finally amplified residue voltage at the third multiplying DAC is fed to the last 3-bit flash ADC decides

final 3-bit digital digital code.

3. adc1276x has the error correction scheme, which handles the output from mismatch in the first, second, third

and fourth flash ADC.

MAIN BLOCK DESCRIPTION

1. SHA
SHA (Sample-and-Hold Amplifier) is the circuit that samples the analog input signal and hold that value until next

sample-time. It is good as small as its different value between analog input signal and output signal. SHA amp

gain is higher than 70dB at 10MHz conversion rate, its settling-time must be shorten than 38ns with less than

1/2 LSB error voltage at 14bit resolution. This SHA is consist of fully differential op amp, switching tr. and

sampling capacitor. The sampling clock is non-overlapping clock (Q1, Q2) and sampling capacitor value is about

4pF. SHA uses independent bias to protect interruption of any other circuit. SHA amp is designed that open-loop

dc gain is higher than 70dB, phase margin is higher than 60 degrees. Its input block is designed to be the rail-to-

rail architecture using complementary different pair.

2. FLASH
The 5-bit flash converters compare analog signal (SAH output) with reference voltage, and that results transfer to

MDAC and digital correction logic block. It is realized fully differential comparators of 31EA. Considering self-

offset, dynamic feed through error, it should distinguish 40mV at least. First, the comparators charge the

reference voltage at the sampling capacitors before transferred SHA output.That operation is performed on the

phase of Q2, and discharging on the phase of Q1. That is, the comparators compare relative different values dual

input voltage with dual reference voltage. Its output during Q1 operation is stored at the pre-latch block by Q1P.

3. MDAC
MDAC is the most important block at this ADC and it decides the characteristics. MDAC is consist of two stage

op amp, selection logic and capacitor array (c_array). c_array's compositions are the capacitors to charge the

analog input and and the reference voltage, switches to control the path. Selection logic controls the c_array

internal switches. If Q1 is high, selection's output are all low, the switches of tsw1 are off, the switches of tsw2

are all on. Therefore the capacitors of c_array can charge analog input values held at SHA.

0.18

m 14-BIT 10MSPS ADC

ADC1276X

PACKAGE CONFIGUATION

1 BGR

REFTOP
REFBOT

CML

CML1

AVDD33A

AVDD33A
AVBB33A
AVSS33A

AVSS33A
AINT

AINC
NC
NC

ITEST

STBY
AVDD33R

AVSS33R
NC

NC
NC

TRIST
RP

AVDD33D

AVSS33D
AVSS33D

AVBB33D

CKIN

DO[13]

DO[12]

DO[9]
DO[8]

DO[7]
DO[6]

DO[5]

DO[4]
DO[3]

DO[2]

DO[1]
DO[0]

ORI

10u

0.1u

10u

0.1u

DO[11]

DO[10]

NOTE: NC denotes "No Connection".

Analog

3
4

5
6

8
9

10
11

13
14

15
16

18
19

21
22

23
24

46
45

44
43

41
40

39
38

36
35

34
33

31
30

28
27

26
25

10u

0.1u

10u

0.1u

10u

0.1u

10u

Digital

adc1276x

10u 0.1u

10u

0.1u

Index Resistor

: 25K

ADC1276X

0.18

m 14-BIT 10MSPS ADC

PACKAGE PIN DESCRIPTION

Pin No.

Pin Name I/O Type

Pin Description

Configurationt

BGR

Reference Voltage Output

REFTOP

Reference Top Output/Force

REFBOT

Reference bottom Output/Force

CML

Internal Bias

CML1

Internal Bias

6, 7

AVDD33A

Analog Power (3.3V)

AVBB33A

Analog Sub Bias

9, 10

AVSS33A

Analog Ground

AINT

Analog Input +

AINC

Analog Input -

ITEST

open=use internal bias circuit

STBY

VDDA=Power saving (Standby),

GNP=Normal

AVDD33R

PAD Power (3.3V)

AVSS33R

PAD Ground

TRIST

Tri-state Buffer Input
VDD=High Impedance,

GND=Normal

ORI

Out of Range Indicator
Normal='Low'

Out of Range='High'

DO[0]

Digital Output (LSB)

28~39

DO[1:12]

Digital Output

DO[13]

Digital Output (MSB)

CKIN

Sampling Clock Input

AVBB33D

Digital Sub Bias

45, 46

AVSS33D

Digital GND

47, 48

AVDD33D

Digital Power (3.3V)

REFTOP

AVBB33A

NC
NC

TRIST

adc1276x

BGR

REFBOT

CML1

AVDD33A

AVSS33A
AVSS33A

AINT

AINC

NC
NC

ITEST

STBY

AVDD33R

AVSS33R

AVDD33D
AVDD33D
AVSS33D

AVSS33D
AVBB33D

CKIN
NC
DO[13]
DO[12]

ORI
NC

CML

48
47
46

45
44
43

42
41
40
39
38
37

36
35
34
33
32
31
30
29
28
27
26
25

1
2
3

4
5
6

7
8
9
10
11
12

13
14
15
16
17
18
19
20
21
22
23
24

DO[9]
DO[8]
DO[7]
DO[6]
DO[5]
DO[4]

DO[3]
DO[2]
DO[1]
DO[0]

DO[11]
DO[10]

0.18

m 14-BIT 10MSPS ADC

ADC1276X

USER GUIDE

1. Input Range

If you want to using the single-ended input, you should use he input range as below.

AINT : 0.5V ~ 2.5V

AINC : 1.5V.

If you want to using the differential input, you should use the input range as below.

AINT : 1.0V ~ 2.0V

AINC : 1.0V ~ 2.0V

AIN : AINT - AINC

If you want to changing input range (AIN span), you can force reference voltages.

AIN span = -REF ~ +REF

REF = REFTOP - REFBOT

2. Power Consumption/Speed Optimization
Yon can optimize the power consumption, as control the ITEST voltage level precisely.

You can optimize the ADC's speed also, as control the ITEST voltage level.

ADC1276X

0.18

m 14-BIT 10MSPS ADC

PHANTOM CELL INFORMATION

Pins of the core can be assigned externally (Package pins) or internally (internal ports) depenging on design

methods.

The term "External" implies that the pins should be assigned externally like power pins.

The term "External/Internal" implies that the applications of these pins depend on the user.

Pin Name

Pin Usage

Pin Layout Guide

AVDD33A

External

- Maintain the large width of lines as far as the pads.

AVSS33A

External

- Place the port positions to minimize the length of power lines.

AVBB33A

External

- Do not merge the analog powers with anoter power from other

AVDD33D

External

blocks.

AVSS33D

External

- Use good power and ground source on board.

AVBB33D

External

AINT

External/Internal

- Do not overlap with digtal lines.

AINC

External/Internal

- Maintain the shotest path to pads.

CKIN

External/Internal

- Separate from all other analog signals

REFTOP

External/Internal

- Maintain the larger width and the shorter length as far as the pads.

REFBOT

External/Internal

- Separate from all other digital lines.

CML

External/Internal

CML1

External/Internal

BGR

External/Internal

ITEST

External/Internal

- Separated from the analog clean signals if possible.

STBY

External/Internal

- Do not exceed the length by 1,000um.

ORI

External/Internal

DO[13]

External/Internal

DO[12]

External/Internal

DO[11]

External/Internal

DO[10]

External/Internal

DO[9]

External/Internal

DO[8]

External/Internal

DO[7]

External/Internal

DO[6]

External/Internal

DO[5]

External/Internal

DO[4]

External/Internal

DO[3]

External/Internal

DO[2]

External/Internal

DO[1]

External/Internal

DO[0]

External/Internal

0.18

m 14-BIT 10MSPS ADC

ADC1276X

FEEDBACK REQUEST

ADC Specification

Parameter

Min

Typ

Max

Unit

Remarks

Supply voltage

Reference Input voltage

Analog Input voltage

Operating temperature

Integral non-linearity error

LSB

Differential non-linearity error

LSB

Offset voltage error (Bottom)

Offset voltage error (Top)

Maximum conversion rate

MSPS

Dynamic supply current

Power dissipation

Signal-to-noise ratio

Digital output format

(Provide detailed description & timing diagram)

What do you want to choose as power supply voltages? For example, the analog V

needs to be 5V.

The digital V

can be 3.3V/5V.

What resolution do you need for ADC?

How about conversion speed (data in

data out)?

How many cycles do exist during the latency of ADC (pipelined delay)?

What's the input range? And then what do you need between single input and differential input?

Can the bus interface be compatible with TTL?

Could you explain external/internal pin configurations as required?

Specially requested function list :

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: adc1276x

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: adc1276x