ADC1295X

0.18

m 8-BIT 800K ADC

GENERAL DESCRIPTION

The adc1295x is a CMOS 8bit A/D converter which combines an auto offset calibration comparator, high resolution

R-string DAC, clock generator, 8bit successive approximation register (SAR), output register, and AINC which

controls analog input selection. The adc1295x provides software-selection power-down mode. The device operates

with a single +3.3V supply and A/D conversion rate is 800KSPS, external clock XP1 is 40MHz. The operating

temperature range is -4085

C for commercial specification.

FEATURES

-- Resolution : 8-bit
-- Maximum Conversion Rate : 800kSPS
-- Power Supply : 3.3V Single (Typ)
-- Differential Linearity

Error :

1.0 LSB

-- Integral Linearity Error :

2.0 LSB

-- Folding, Interpolation and Pipelined Scheme
-- Low Power Consumption

: at operating, 3.3mW(typ)

: at standby, 330nW(typ)

-- Guaranteed Monotonicity
-- No Missing Code
-- Latched Tri-state Output
-- Operating Temperature Range : -40

C 85

TYPICAL APPLICATIONS

-- MICOM
-- Battery Charger
-- Game Pack
-- Digital Still Camera
-- Hand Held Computer & Organizer.
-- Other Low power equipments.

0.18

m 8-BIT 800K ADC

ADC1295X

FUNCTIONAL BLOCK DIAGRAM

cops

ckgens

sar8s

outregs

AIN

REFP

REFN

XP1

STBY

DGET

ADEN

FLAG

DO[7:0]

AVDD33A

AVSS33A

AVBB33A

vrgs

aiscs

AVDD33D

AVSS33D

AVBB33D

Ver 1.2 (Apr. 2002)

No responsibility is assumed by SEC for its use nor for any infringements of patents or other rights of third parties

that may result from its use. The content of this data sheet is subject to change without any notice.

ADC1295X

0.18

m 8-BIT 800K ADC

CORE PIN DESCRIPTION

Name

I/O Type

I/O Pad

Pin Description

REFP

phia_abb

Internal Reference Top Bias. 3.3V

REFN

phia_abb

Internal Reference Bottom Bias. 0V

AVDD33A

vdd3t_abb

Analog Power(3.3V)

AVSS33A

vss3t_abb

Analog Ground

AVBB33A

vbb3_abb

Analog Substrate

AIN

phiar50_abb

Analog Input

XP1

phicc_abb

Main Clock(external)

STBY

phicc_abb

System Power Down(Active High)

ADEN

phicc_abb

A/D Conversion Enable

DO[7:0]

phoa_abb

Digital Outputs

DGET

phicc_abb

DOUTs Read Enable

FLAG

phoa_abb

Test pin for checking the ADC state

AVBB33D

vbb3_abb

Digital Substrate

AVSS33D

vss3t_abb

Digital Ground

AVDD33D

vdd3t_abb

Digital Power(3.3V)

I/O Type Abbr.
-- AI: Analog Input
-- DI: Digital Input
-- AO: Analog Output
-- DO: Digital Output
-- AB: Analog Bi-direction
-- DB: Digital Bi-direction
-- AP: Analog Power
-- AG: Analog Ground
-- DP: Digital Power
-- DG: Digital Ground

ADC1295X

0.18

m 8-BIT 800K ADC

ABSOLUTE MAXIMUM RATINGS

Characteristic

Symbol

Value

Unit

Supply Voltage

4.5

Analog Input Voltage

AIN

to V

Digital Input Voltage

DIN

to V

Digital Output Voltage

OH, VOL

to V

Reference Voltage

REFP/REFN

to V

Storage Temperature Range

Tstg

-55 to 125

Operating Temperature Range

Topr

-40 to 85

NOTES:
1. ABSOLUTE MAXIMUM

RATING

specifies

the

values

beyond

which

the

device

may

damaged

permanently.

Exposure

ABSOLUTE MAXIMUM

RATING

conditions

for

extended

periods

may

affect

reliability.

Each

condition

value

applied

with

the

other

values

kept

within

the

following

operating

conditions

and

function

operation

under

any

these

conditions

not

implied.

2. All voltages

are

measured

with

respect

VSS

unless

otherwise

specified.

3. 100pF

capacitor

discharged

through

1.5k

resistor

(Human

body

model)

RECOMMENDED OPERATING CONDITIONS

Characteristics

Symbol

Min

Typ

Max

Unit

Supply Voltage

AVDD33A

AVDD33D

3.3-5%

3.3

3.3+5%

Supply Voltage Difference

AVDD33A

AVSS33D

-0.1

0.0

0.1

Reference Input Voltage

REFP

REFN

AVDD33A

Analog Input Voltage

AIN

REFN

REFP

Clock High Time

Clock Low Time

Tpwh

Tpwl

19
19

Digital Input 'L' Voltage

Digital Input 'H' Voltage

0.9*AVDD33D

0.1*AVDD33D

AVDD33D

Operating Temperature

Topr

-40

NOTE: It is

strongly

recommended

that

all

the

supply

pins

(AVDD33A,

AVDD33D)

powered

from

the

same

source

avoid power

latch-up.

0.18

m 8-BIT 800K ADC

ADC1295X

DC ELECTRICAL CHARACTERISTICS

Characteristics

Symbol

Min

Typ

Max

Unit

Test Conditions

Resolution

Bits

Differential Linearity Error

DLE

0.5

1.0

LSB

XP1 : 40MHz

Integral Linearity Error

ILE

0.5

2.0

LSB

Offset Voltage Error(top)

EOT

2.0

4.0

LSB

EOT = REFP-AIN(255,256)

Offset Voltage Error(bottom)

EOB

2.0

4.0

LSB

EOB = AIN(0,1)-REFN

NOTES:
1.

Converter

Specifications

(unless

otherwise

specified)

AVDD33A=3.3V

AVDD33D=3.3V

AVSS33A=GND

AVSS33D=GND

AVBB33A=GND AVBB33D=GND
REFP=3.3V REFN=0.0V
Ta=25

TBD

Determined

AC ELECTRICAL CHARACTERISTICS

Characteristics

Symbol

Min

Typ

Max

Unit

Test Conditions

Clock High Time

Tpwh

XP1 : 25MHz (Typ)

Clock Low Time

Tpwl

40MHz (Max)

Conversion Rate

500

800

KSPS

Conversion Time

1.25

Dynamic Supply Current

1.5

Power Load Cap:10uF//0.1uF

Output load cap.=1pF

Isd

0.1

0.5

at Power Down.

Power Dissipation

3.3

5.4

during A/D operation

Pdd

0.33

1.8

at Power Down.

Digital Output Data Delay

Output load cap.=1pF

0.18

m 8-BIT 800K ADC

ADC1295X

FUNCTIONAL DESCRIPTION

1. XP1

The XP1 is the system main clock. If 25MHz clock is applied, 10bit 500KSPS or 8bit 650KSPS outputs are

produced. In case of 10MHz clock, 10bit 200KSPS or 8bit 250KSPS outputs are made.

2. STBY

This pin is used for keeping standby without A/D conversion operation. For A/D operation, its state must be

changed from '1' to '0' after at least one XP1 period. In the timing chart, 3.5-XP1 period is drawn and this state

transition can occur even at rising or falling edges. If not needed, it can be tied to GND.

3. ADEN

This is a A/D conversion enable signal. It is for one XP1 period at falling edge. In a 10bit, at least 45-XP1 periods

are required until the next ADEN, and 37-XP1 periods are delayed until the next ADEN for an 8bit.

4. DO[7:0]

Digital output pins.

5. DGET

Data read signal. If DGET is applied during A/D conversion, selected AIN pin information is produced(refer to

TIMING CHART). It is to check if the right analog input is selected. After A/D operation, the state of the test pin,

FLAG, changes to '1', and A/D converted data are produced by applying DGET signal.

6. AIN

Analog Input

7. FLAG

Test pin. Its state goes LOW during A/D conversion, and goes HIGH after the A/D conversion. If STBY signal is

applied even at A/D conversion mode, its state goes HIGH immediately.

ADC1295X

0.18

m 8-BIT 800K ADC

CORE EVALUATION GUIDE

1. You can test ADC function by the DGET. If you don't use the DGET pin, this ADC function is evaluated by

external check on the bi-directional pads connected to input nodes of HOST DSP back-end circuit.

2. The reference voltages may be biased externally through REFP and REFN pins

Digital

MUX

adc1295x

AIN

DO[7:0]

XPI

STBY

DGET
ADEN

Power Used

: AVDD33A,AVSS33A,AVBB33A

AVDD33D,AVSS33D,AVBB33D

3.3V

GND

REFP

REFN

DO[7:0]

Host

DSP
Core

DO[7:0]

Bidirectional

PAD

(ADC Function Test &

externally forced Digital Input)

: 10

F Electronic Capacitor

Unless otherwise specified
: 0.1

F Ceramic Capacitor

Unless otherwise specified

Flag

0.18

m 8-BIT 800K ADC

ADC1295X

PACKAGE CONFIGUATION

1 NC

REFP
NC

REFN

AVDD33A

NC
AVBB33A
NC

AVSS33A
NC

AIN
NC
NC

STBY
AVDD33D

AVSS33D
XP1

NC
AVBB33D

NC
RP

AVDD33R

AVSS33R

AVBB3R

NC
NC

DO[7]
DO[6]

DO[5]
DO[4]

DO[3]

DO[2]
DO[1]

DO[0]

DGET

ADEN

10u

0.1u

FLAG

3
4

5
6

8
9

10
11

13
14

15
16

18
19

21
22

23
24

46
45

44
43

41
40

39
38

36
35

34
33

31
30

28
27

26
25

10u

0.1u

10u

adc1295x

Digital

Output

10u

0.1u

3.3V

0.1u

10u

0.1u

ADC1295X

0.18

m 8-BIT 800K ADC

PACKAGE PIN DESCRIPTION

Pin Name

Pin No.

I/O Type

I/O PAD

Pin Description

REFP

phia_abb

Internal Reference Top Bias. 3.3V

REFN

phia_abb

Internal Reference Bottom Bias. 0V

AVDD33A

vdd3t_abb

Analog Power(3.3V)

AVBB33A

vbb3_abb

Analog Substrate

AVSS33A

vss3t_abb

Analog Ground

AIN

phiar10_abb

Analog Inputs.
Input Span : REFP REFN

STBY

phicc_abb

System Power Down(Active High)

AVDD33D

vdd3t_abb

Digital Power(3.3V)

AVSS33D

vss3t_abb

Digital Ground

XP1

phicc_abb

Main Clock(external)

AVBB33D

vbb3_abb

Digital Substrate

ADEN

phicc_abb

A/D Conversion Enable

DGET

phicc_abb

Read Enable

DO[7:0]

29~36

phot12_abb

Digital Outputs

FLAG

phot12_abb

Testpin. ADC Operation Checking.

AVBB33R

vbb3_abb

Driver Substrate

AVSS33R

vss3t_abb

Driver Ground

AVDD33R

vdd3t_abb

Driver Power(3.3V)

0.18

m 8-BIT 800K ADC

ADC1295X

USER GUIDE

1. Speed Up
-- The initial target speed(Conversion Rate) of adc1295x was 8bit 500KSPS~ 800KSPS, but it proved to operate

well even at 8bit 900KSPS because of a lot of design margin. It would be realized by speed-up of XP1.

2. Input Range Variation
-- The analog input of this ADC is single input and the range is from REFN to REFP. This AIN voltage follows

reference voltage range fundamentally. Therefore, in order to alter into another input voltage range, change the

voltage value of REFP.

-- You can use the AIN voltage whose minimum range is 2.7V. In this case, the REFP is 2.7V and REFN is 0.0V.

If the range is 3.0V, the REFP is 3.0V and REFN is 0.0V. It is an user selection item. In case of maximum

voltage range, the REFP is the power level(3.3V) and the REFN is the ground level.

3. Note that this ADC has not the sample and hold circuit, therefore during the A/D conversion the analog

input voltage variation should not deviate more than 1 LSB voltage range.

ADC1295X

0.18

m 8-BIT 800K ADC

PHANTOM CELL INFORMATION

-- Pins of the core can be assigned externally (Package pins) or internally (internal ports) depending on design

methods.

The term "External" implies that the pins should be assigned externally like power pins.

The term "External/internal" implies that the applications of these pins depend on the user.

adc1295x

8-BIT 800KSPS ADC

FLAG

DO[3]

DO[4]

DO[5]

REFN

REFP

STBY

AIN

ADEN

XP1

DGET

AVDD33D

AVSS33D

AVBB33D

AVSS33A

AVDD33A

AVBB33A

DO[0]

DO[1]

DO[2]

DO[6]

DO[7]

0.18

m 8-BIT 800K ADC

ADC1295X

Pin Name

Pin Usage

Pin Layout Guide

AVDD33A

External

- Maintain the large width of lines as far as the pads.

AVSS33A

External

- place the port positions to minimize the length of power lines.

AVBB33A

External

- Do not merge the analog powers with anoter power from other

AVDD33D

External

blocks.

AVSS33D

External

- Use good power and ground source on board.

AVBB33D

External

AIN

External/Internal

- Do not overlap with digtal lines.

- Maintain the shotest path to pads.

XP1

External/Internal

- Separate from all other analog signals

REFP

External/Internal

- Maintain the larger width and the shorter length as far as the pads.

REFB

External/Internal

- Separate from all other digital lines.

STBY

External/Internal

ADEN

External/Internal

DGET

External/Internal

FLAG

External/Internal

DO[7]

External/Internal

DO[6]

External/Internal

DO[5]

External/Internal

DO[4]

External/Internal

DO[3]

External/Internal

DO[2]

External/Internal

DO[1]

External/Internal

DO[0]

External/Internal

ADC1295X

0.18

m 8-BIT 800K ADC

FEEDBACK REQUEST

It should be quite helpful to our ADC core development if you specify your system requirements on ADC in the

following characteristic checking table and fill out the additional questions.

We appreciate your interest in our products. Thank you very much.

Characteristic

Min

Typ

Max

Unit

Remarks

Analog Power Supply Voltage

Digital Power Supply Voltage

Bit Resolution

Bit

Reference Input Voltage

Analog Input Voltage

Number of Analog Input Channel
Operating Temperature

Integral Non-linearity Error

LSB

Differential Non-linearity Error

LSB

Bottom Offset Voltage Error

Top Offset Voltage Error

Conversion Rate

KSPS

Conversion Time(ADEN~ADEN)

Dynamic Supply Current

Power Dissipation

Power Dissipation at Power Down

Digital Output Format

(Provide detailed description & timing diagram)

0.18

m 8-BIT 800K ADC

ADC1295X

FEEDBACK REQUEST-2

1. I want to know the detail of the analog input waveform. Which one is adequate for your analog input waveform

among the a, b, and c below. If none of the three is adequate, please describe the analog input waveform to be

used. If your analog input signal is sine-wave as c, please let me know what is your analog input signal's

frequency and how many number of sampling points are required for 1-period?

AIN[n]

AIN[0]

a. (fixed DC input)

b. (ramp DC input)

c. (sine-wave input)

n-channel

Analog MUX

2. Between single input-output and differential input-output configurations, which one is suitable for your system

and why?

3. Please comment on the internal/external pin configurations and draw the timing diagram you want our ADC to

have, if you have any reason to prefer some type of configuration.

4. Freely list those functions you want to be implemented in our ADC, if you have any.

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