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m 10-BIT 500KSPS ADC

ADC1395X

GENERAL DESCRIPTION

The adc1395x is a CMOS 3.3V 10-bit analog-to- digital converter (ADC). It converts the analog input signal into
12-bit binary digital codes at a maximum conversion rate of 500KSPS with 2.5MHz clock.

The device is a recycling type monolithic ADC with an on-chip sample-and-hold function. The ADC has power
down mode.

FEATURES

-- Resolution: 10-bit

-- Maximum conversion rate: 500KSPS

-- Main clock: 2.5MHz

-- Power supply: 3.3V

0.3V

-- Total current: 10uA (Standby Mode)

2mA (Normal Operation)

-- Input range: 0.0V ~ 3.3V (3.3V

P-P

)

-- Differential linearity error:

1.0 LSB (Max)

-- Integral linearity error:

3.0 LSB (Max.)

-- Signal to noise & distortion ratio: 54dB

-- Digital output: CMOS Level

-- Operating temperature range: 40

C ~ 85

TYPICAL APPLICATIONS

-- MICOM Interface

-- Portable equipment

-- Low-voltage low-power application

ADC1395X

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m 10-BIT 500KSPS ADC

FUNCTIONAL BLOCK DIAGRAM

CLOCK

GEN

AINT

VREF

AGND

DO[9:0]

STC

CKIN

STBY

CML
GEN

REF

GEN

MAIN

BIAS

FLASH2

FLASH1

Digital Logic

EOC

MDAC1

MDAC2

Ver 1.0 (April. 2002)
No responsibility is assumed by SEC for its use nor for any infringements of patents or other rights of third parties that may
result from its use. The content of this data sheet is subject to change without any notice.

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m 10-BIT 500KSPS ADC

ADC1395X

CORE PIN DESCRIPTION

Name

I/O Type

I/O Pad

Pin Description

VREF

phia_abb

Reference top (3.3V)

AGND

phia_abb

Reference bottom (0.0V)

AVDD33A1

vdd33th_abb

Analog power (3.3V)

AVBB33A1

vbbh_abb

Analog sub bias (0.0V)

AVSS33A1

vssth_abb

Analog ground (0.0V)

AINT

phiar50_abb

Analog input (input range: 0.0V ~ 3.3V)

STBY

phicc_abb

VDD = Power saving (standby),
GND = Normal

CKIN

phicc_abb

Sampling clock input

D[11:0]

phob4_abb

Digital output

EOC

phob4_abb

End of conversion signal

STC

phicc_bb

Start of conversion signal

AVSS33A2

vssth_abb

Digital GND (0.0V)

AVDD33A2

vdd33th_abb

Digital power (3.3V)

I/O

Type

Abbr.

-- AI: Analog Input

-- DI: Digital Input

-- AO: Analog Output

-- DO: Analog Output

-- AP: Analog Power

-- AG: Analog Ground

-- DP: Digital Power

-- DG: Digital Ground

-- AB: Analog Bi-Direction

-- DB: Digital Bi-Direction

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ADC1395X

ABSOLUTE MAXIMUM RATINGS

Characteristics

Symbol

Value

Unit

Supply voltage

VDD

4.5

Analog input voltage

AINT

VSS to VDD

Digital input voltage

CKIN

VSS to VDD

Reference voltage

VREF / AGND

VSS to VDD

Storage temperature range

Tstg

45 to 150

Operating temperature range

Topr

45 to 80

NOTES:
1.

Absolute maximum rating specifies the values beyond which the device may be damaged permanently. Exposure to
absolute maximum rating conditions for extended periods may affect reliability. Each condition value is applied
with the other values kept within the following operating conditions and function operation under any of these conditions
is not implied.

All voltages are measured with respect to VSS unless otherwise specified.

100pF capacitor is discharged through a 1.5k

resistor (Human body model)

RECOMMENDED OPERATING

CONDITIONS

Characteristics

Symbol

Min

Typ

Max

Unit

Supply voltage

AVDD33A1
AVDD33A2

3.0

3.3

3.6

Reference input voltage

VREF

AGND

2.0
0.0

3.3
0.0

3.6
0.0

Analog input voltage

AINT

0.0

VREF

Operating temperature

Toper

NOTE: It

strongly

recommended

that

all

the

supply

pins

(AVDD33A1,

AVDD33A2)

powered

from

the

same

source

avoid

power

latch-up.

ADC1395X

0.13

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m 10-BIT 500KSPS ADC

DC ELECTRICAL

CHARACTERISTICS

Characteristics

Symbol

Min

Typ

Max

Unit

Test Condition

Differential nonlinearity

DNL

0.8

LSB

VREF = 3.3V
AGND = 0.0V

Integral nonlinearity

INL

1.0

LSB

VREF = 3.3V
AGND = 0.0V

Offset voltage

OFF

LSB

VREF = 3.3V
AGND = 0.0V

NOTE: (Converter

Specifications

AVDD33A1=AVDD33A2=3.3V,

AVSS33A1=AVSS33A2=0V,

Toper=25

VREF=3.3V,

AGND=0.0V

unless

otherwise

specified)

AC ELECTRICAL CHARACTERISTICS

Characteristics

Symbol

Min

Typ

Max

Unit

Test Condition

Maximum conversion rate

500

KSPS

CKIN

= 2.5MHz

Standby supply current

STBY = VDD

Dynamic supply current

IVDD

2.0

CKIN

= 2.5MHz

(without system load)

Reference current

IREF

0.4

0.6

VREF = 3.3V

Total harmonic distortion

THD

CKIN

= 2.5MHz

AINT = 100kHz

Signal-to-noise & distortion
Ratio

SNDR

CKIN

= 2.5MHz

AINT = 100kHz

NOTE: (Converter

Specifications

AVDD33A1=AVDD33A2=3.3V,

AVSS33A1=AVSS33A2=0V,

Toper=25

VREF=3.3V,

AGND=0.0V

unless

otherwise

specified)

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m 10-BIT 500KSPS ADC

ADC1395X

I/O CHART

Index

AINT Input (V)

Digital Output

~ 0.00322

00 0000 0000

1LSB=3.22mV

0.00322 ~ 0.00644

00 0000 0001

VREF=3.3V

0.00644 ~ 0.00967

00 0000 0010

AGND=0.0V

511

1.64678 ~ 1.65000

01 1111 1111

512

1.65000 ~ 1.65322

10 0000 0000

513

1.65322 ~ 1.65644

10 0000 0001

1021

3.29033 ~ 3.29355

11 1111 1101

1022

3.29355 ~ 3.29678

11 1111 1110

1023

3.29678 ~

11 1111 1111

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m 10-BIT 500KSPS ADC

ADC1395X

2. STC & CKIN Condition

10ns

CKIN

STC

3ns

SAFE

The A/D Converter operates data conversion when STC (Start Conversion) signal is just "HIGH". Otherwise,
output data (DO[9:0]) keep the current states. The STC signal should be changed during "T

SAFE

" with the "HIGH"

level of the clock to operation as shown in the main waveform.

ADC External Interface Signal

-- AINT: Analog Input Signal (Input)

Input Range: VREF ~ AGND

-- STBY: Stand-by Signal, Power Save Mode (Input)

-- CKIN: ADC Main Clock, f

CKIN

= 2.5MHz, 1 Clock Period = 400ns (Input)

-- STC: Start of Conversion Signal (Input)

-- EOC: End of Conversion Signal (Output)

-- DO[9:0]: Digital Output Signal (Output)

ADC1395X

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m 10-BIT 500KSPS ADC

CORE EVALUATION GUIDE

ADC function is evaluated by external check on the bi-directional pads connected to input nodes of HOST DSP
back-end circuit.

The reference voltages may be biased internally through resistor divider.

STBY

CKIN

AINT

VREF

AGND

AVDD33A

AVSS33A

AVBB33A

AVDD33D

AVSS33D

[MSB:LSB]

STC

DO[9:0]

EOC

Digital

Mux

HOST

DSP

CORE

Bi-directional

PAD

D[9:0]

(ADC Function Test & Externally

forced Digital Input)

adc1395x

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m 10-BIT 500KSPS ADC

ADC1395X

PACKAGE CONFIGURATION

adc1395x

VREF

AGND

AVDD33A

AVBB33A

AVSS33A

AINT

STBY

VDDR

VSSR

CKIN

AVDD33D

AVSS33D

AVDD33D

STC

EOC

DO[7]

DO[6]

DO[5]

DO[4]

DO[3]

DO[2]

DO[1]

DO[0]

TEST

10u

0.1u

10u

Digital I

Digital II

Analog

0.1u

10u

0.1u

10u

10u 0.1u

DO[9]

DO[8]

NOTE: NC denotes "No Connection".

ADC1395X

0.13

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µ

m 10-BIT 500KSPS ADC

PACKAGE PIN DESCRIPTION

Name

No.

I/O Type

Pin Description

VREF

1, 2

Reference voltage (3.3V)

AGND

3, 4

Analog ground (0.0V)

AVDD33A1

6, 7

Analog power (3.3V)

AVBB33A1

Analog sub bias

AVSS33A1

9, 10

Analog ground

AINT

Analog input

STBY

VDD = Power saving (standby),
GND = Normal

VDDR

PAD power (3.3V)

VSSR

PAD ground

CKIN

Clock input (f

CKIN

= 2.5MHz)

Test pin1

Test pin2

DO[0]

Digital output (LSB)

DO[1:8]

30 ~ 37

Digital output

DO[9]

Digital output (MSB)

EOC

End of conversion signal

STC

Start of conversion signal

AVSS33A2

45, 46

Digital GND

AVSS33A2

47, 48

Digital power (3.3V)

NOTE: I/O

TYPE

and

denote

PAD

Power

and

PAD

Ground

respectively.

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m 10-BIT 500KSPS ADC

ADC1395X

CONFIGURATION

VREF

VBBA

adc1395x

VREF

AGND

VDDA

VSSA

AINT

STBY

VDDR

VSSR

CKIN

VDDD

VSSD

STC

EOC

DO[7]

DO[6]

DO[5]

DO[4]

DO[3]

DO[2]

DO[1]

DO[0]

TEST

AGND

DO[9]

DO[8]

ADC1395X

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m 10-BIT 500KSPS ADC

PHANTOM CELL INFORMATION

Pins of the core can be assigned externally (Package pins) or internally (internal ports) depending on design
methods.

The term "External" implies that the pins should be assigned externally like power pins.

The term "External/internal" implies that the applications of these pins depend on the user.

Pin Name

Pin Usage

Pin Layout Guide

AVDD18A

External

Maintain the large width of lines as far as the pads.

AVSS18A

External

Place the port positions to minimize the length of power lines.

AVBB18A

External

Do not merge the analog powers with anoter power from other
blocks.

AVDD18A

External

Use good power and ground source on board.

AVSS18D

External

AVBB18D

External

AINT

External / Internal

Do not overlap with digital lines.

AINC

External / Internal

Maintain the shotest path to pads.

CKIN

External / Internal

Separate from all other analog signals

REFTOP

External / Internal

Maintain the larger width and the shorter length as far as the
pads.

REFBOT

External / Internal

Separate from all other digital lines.

CML

External / Internal

ITEST

External / Internal

STBY

External / Internal

STC

External / Internal

SPEEDUP

External / Internal

EOC

External / Internal

Separated from the analog clean signals if possible.

DO[9]

External / Internal

Do not exceed the length by 1,000um.

DO[8]

External / Internal

DO[7]

External / Internal

DO[6]

External / Internal

DO[5]

External / Internal

DO[4]

External / Internal

DO[3]

External / Internal

DO[2]

External / Internal

DO[1]

External / Internal

DO[0]

External / Internal

ADC1395X

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m 10-BIT 500KSPS ADC

USER GUIDE

1. Input Range

The analog input is single-ended type and the range is from VREF to AGND. This AINT voltage follows reference
voltage range fundamentally. So, if you want to alter into the another input range, you should change the voltage
value of VREF.

You can use the AINT voltage whose minimum range is 2.0V. In this case, the VREF is 2.0V.

0.13

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m 10-BIT 500KSPS ADC

ADC1395X

FEEDBACK

REQUEST

It should be quite helpful to our ADC core development if you specify your system requirements on ADC in the
following characteristic checking table and fill out the additional questions.

We appreciate your interest in our products. Thank you very much.

Characteristic

Min

Typ

Max

Unit

Remarks

Analog power supply voltage

Digital power supply voltage

Bit resolution

Bit

Reference input voltage

Analog input voltage

Vpp

Operating temperature

Integral non-linearity error

LSB

Differential non-linearity error

LSB

Bottom offset voltage error

Top offset voltage error

Maximum conversion rate

MSPS

Dynamic supply current

Power dissipation

Signal-to-noise ratio

Pipeline delay

CLK

Digital output format
(Provide detailed description &
timing diagram)

1. Between single input-output and differential input-output configurations, which one is suitable for your system
and why?

2. Please comment on the internal/external pin configurations you want our ADC to have, if you have any reason
to prefer some type of configuration.

3. Freely list those functions you want to be implemented in our ADC, if you have any.

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