AEGISADC

12-BIT 500KSPS ADC

GENERAL DESCRIPTION

The AEGISADC is a CMOS 2.5V 12-bit analog-to- digital converter (ADC). It converts the analog input signal
into 12-bit binary digital codes at a maximum conversion rate of 500KSPS with 2.5MHz clock.

The device is a recycling type monolithic ADC with an on-chip sample-and-hold function. The ADC has power
down mode.

FEATURES

-- Resolution:

12 bit

-- Maximum

Conversion

Rate:

500KSPS

-- Main Clock:

2.5MHz

-- Power

Supply:

2.5V

0.2V

-- Total Current: 20

A (Standby Mode)

2.2mA (Normal Operation)

-- Input Range: 0.0V - 2.5V (2.5Vpp)

-- Differential

Linearity

Error:

1.0

LSB

-- Integral

Linearity

Error:

2.0

LSB

-- Signal

Noise

Distortion

Ratio:

62dB

-- Digital

Output:

CMOS

Level

-- Operating

Temperature

Range:

- 70

TYPICAL APPLICATIONS

-- MICOM Interface

-- Portable Equipment

-- Low-Voltage Low-Power Application

12-BIT 500KSPS ADC

AEGISADC

FUNCTIONAL BLOCK DIAGRAM

FLASH1

MDAC1

FLASH2

MDAC2

DIGITAL

LOGIC

AINT

STBY

MAIN

BIAS

REF

GEN

CML
GEN

CLOCK

GEN

VREF

AGND

CKIN

STC

DO[11:0]

EOC

VER 1.2 (Apr. 2002)
This data sheet is a preliminary version. No responsibility is assumed by SEC for its use nor for any infringements of patents
or other rights of third parties that may result from its use. The content of this data sheet is subject to change without any
notice.

AEGISADC

12-BIT 500KSPS ADC

CORE PIN DESCRIPTION

NAME

I/O TYPE

I/O PAD

PIN DESCRIPTION

VREF

pia_abb

Reference Top (2.5V)

AGND

pia_abb

Reference Bottom (0.0V)

AVDD25A1

vdd2t_abb

Analog Power (2.5V)

AVBB25A1

vbb_abb

Analog Sub Bias (0.0V)

AVSS25A1

vss2t_abb

Analog Ground (0.0V)

AINT

piar50_abb

Analog Input
(Input Range: 0.0V-2.5V)

STBY

picc_abb

VDD = power saving (standby),
GND = normal

CKIN

picc_abb

Sampling Clock Input

D[11:0]

poa_abb

Digital Output

EOC

poa_abb

End of Conversion Signal

STC

picc_abb

Start of Conversion Signal

AVSS25A2

vss2t_abb

Digital GND (0.0V)

AVDD25A2

vdd2t_abb

Digital Power (2.5V)

I/O TYPE ABBR.

AI : Analog Input

DI : Digital Input

AO: Analog Output

DO: Digital Output

AP: Analog Power

AG: Analog Ground

DP: Digital Power

DG: Digital Ground

AB: Analog Bidirection

DB: Digital Bidirection

AEGISADC

12-BIT 500KSPS ADC

ABSOLUTE MAXIMUM RATINGS

Characteristics

Symbol

Value

Unit

Supply Voltage

VDD

3.3

Analog Input Voltage

AINT

VSS to VDD

Digital Input Voltage

CKIN

VSS to VDD

Reference Voltage

VREF / AGND

VSS to VDD

Storage Temperature Range

Tstg

-45 to 150

Operating Temperature Range

Topr

0 to 70

NOTES:
1.

ABSOLUTE

MAXIMUM

RATING

specifies

the

values

beyond

which

the

device

may

damaged

permanently.

Exposure

ABSOLUTE

MAXIMUM

RATING

conditions

for

extended

periods

may

affect

reliability.

Each

condition

value

applied

with

the

other

values

kept

within

the

following

operating

conditions

and

function

operation

under

any

these

conditions

not

implied.

All

voltages

are

measured

with

respect

VSS

unless

otherwise

specified.

100pF

capacitor

discharged

through

1.5k

resistor

(Human

body

model)

RECOMMENDED OPERATING CONDITIONS

Characteristics

Symbol

Min

Typ

Max

Unit

Supply Voltage

AVDD25A1
AVDD25A2

2.3

2.5

2.7

Reference Input Voltage

VREF

AGND

2.0
0.0

2.5
0.0

2.7
0.0

Analog Input Voltage

AINT

0.0

VREF

Operating Temperature

Toper

NOTE: It

strongly

recommended

that

all

the

supply

pins

(VDD18A1,

VDD18A2,

VDD18A3)

powered

from

the

same

source

avoid

power

latch-up.

ELECTRICAL

CHARACTERISTICS

Characteristics

Symbol

Min

Typ

Max

Unit

Test Condition

Differential
Non-linearity

DNL

0.8

LSB

VREF = 2.5V

AGND = 0.0V

Integral
Non-linearity

INL

1.0

LSB

VREF = 2.5V

AGND = 0.0V

Offset
Voltage

OFF

LSB

VREF = 2.5V

AGND = 0.0V

(Converter

Specifications

AVDD25A1=AVDD25A2=2.5V,

AVSS25A1=AVSS25A2=0V,

Toper=25

VREF=2.5V,

AGND=0.0V

unless

otherwise

specified)

12-BIT 500KSPS ADC

AEGISADC

AC ELECTRICAL

CHARACTERISTICS

Characteristics

Symbol

Min

Typ

Max

Unit

Test Condition

Maximum
Conversion Rate

500

KSPS

CKIN

= 2.5MHz

Standby Supply
Current

STBY = VDD

Dynamic Supply
Current

IVDD

1.8

2.4

CKIN

= 2.5MHz

(without system
load)

Reference Current

IREF

0.4

0.6

VREF = 2.5V

Total Harmonic
Distortion

THD

-70

-66

CKIN

= 2.5MHz

AINT = 100KHz

Signal-to-Noise &
Distortion Ratio

SNDR

CKIN

= 2.5MHz

AINT = 100KHz

(Converter

Specifications

AVDD25A1=AVDD25A2=2.5V,

AVSS25A1=AVSS25A2=0V, Toper=25 °C, VREF=2.5V,

AGND=0.0V unless otherwise specified)

I/O

CHART

Index

AINT Input (V)

Digital Output

~ 0.00061

0000 0000 0000

0.00061 ~ 0.00122

0000 0000 0001

0.00122 ~ 0.00183

0000 0000 0010

2047

1.64939 ~ 1.25000

0111 1111 1111

1LSB=0.61mV

2048

1.25000 ~ 1.25061

1000 0000 0000

VREF=2.5V

2049

1.25061 ~ 1.25122

1000 0000 0001

AGND=0.0V

4093

2.49817 ~ 2.49872

1111 1111 1101

4094

2.49872 ~ 2.49939

1111 1111 1110

4095

2.49939 ~

1111 1111 1111

AEGISADC

12-BIT 500KSPS ADC

TIMING DIAGRAM

1. MAIN WAVEFORM

CKIN

STBY

AINT

STC

Input Sampling Period

EOC

2. STC & CKIN CONDITION

STC

CKIN

SAFE

3ns

10ns

The A/D Converter operates data conversion when STC (Start Conversion) signal is just "HIGH". Otherwise,
output data (DO[11:0]) keep the current states. The STC signal should be changed during "TSAFE" with the
"HIGH" level of the clock to operation as shown in the main waveform.

·
·

ADC External Interface Signal

-- AINT: Analog Input Signal (Input)

Input Range: VREF ~ AGND

-- STBY: Stand-by Signal, Power Save Mode (Input)

-- CKIN: ADC Main Clock, f

CKIN

= 2.5MHz, 1 Clock Period = 400ns (Input)

-- STC: Start of Conversion Signal (Input)

-- EOC: End of Conversion Signal (Output)

-- DO[11:0]: Digital Output Signal (Output)

12-BIT 500KSPS ADC

AEGISADC

CORE EVALUATION GUIDE

1. ADC function is evaluated by external check on the bi-directional pads connected to input nodes of HOST

DSP back-end circuit.

2. The reference voltages may be biased internally through resistor divider.

HOST

DSP

CORE

(ADC Function Test &

Externally Forced Digital Input)

AINT

aegisadc

VREF

AGND

STC

AVDD25A1

AVSS25A1

AVBB25A1

AVDD25A2

AVSS25A2

Digital Mux

Bidirectional

PAD

D[11:0]

CKIN

STBY

DO[11:0]

EOC

[MSB:LSB]

AEGISADC

12-BIT 500KSPS ADC

USER GUIDE

1. INPUT RANGE

-- The analog input is single-ended type and the range is from VREF to AGND. This AINT voltage follows

reference voltage range fundamentally. So, if you want to alter into the another input range, you should
change the voltage value of VREF.

-- You can use the AINT voltage whose minimum range is 2.0V. In this case, the VREF is 2.0V.You can use the

AINT voltage whose minimum range is 2.0V. In this case, the VREF is 2.0V.You can use the AINT voltage
whose minimum range is 2.0V. In this case, the VREF is 2.0V.

AEGISADC

12-BIT 500KSPS ADC

Name

I/O Type

Pin Usage

Pin Description

AINT

Internal/External

AINT signal should not be crossed by any signals
and should not run next to digital signals to minimize
capacitive coupling between the two signals.

STBY

Internal/External

CKIN

Internal/External

D[11:0]

Internal/External

EOC

Internal/External

STC

Internal/External

VREF

External

Voltage reference lines (VREF and AGND) must be wide
metal

AGND

External

to reduce voltage drop of metal lines.

AVDD25A1

External

1. It is recommended that you use thick analog power metal.

AVBB25A1

External

When connected to PAD, the path should be kept as short

AVSS25A1

External

as possible.

AVSS25A2

External

2. Digital power and analog power are separately used.

AVDD25A2

External

12-BIT 500KSPS ADC

AEGISADC

FEEDBACK REQUEST

ADC SPECIFICATION

Parameter

Min

Typ

Max

Unit

Remarks

Supply voltage

Reference Input Voltage

Analog Input Voltage

Vpp

Operating Temperature

Integral Non-linearity Error

LSB

Differential Non-linearity Error

LSB

Offset Voltage Error (Bottom)

Offset Voltage Error (Top)

Maximum Conversion Rate

MSPS

Dynamic Supply Current

Power Dissipation

Signal-to-noise Ratio

Digital Output Format
(Provide detailed description &
timing diagram)

-- What do you want to choose as power supply voltages? For example, the analog VDD needs to be 5V. the

digital VDD can be 2.5V/5V.

-- What resolution do you need for ADC?

-- How about conversion speed (data in

data out)?

-- How many cycles do exist during the latency of ADC (pipelined delay)?

-- What's the input range? And then what do you need between single input and differential input?

-- Can the bus interface be compatible with TTL?

-- Could you explain external/internal pin configurations as required?

Specially requested function list:

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