AL1208H

10BIT 20MSPS ADC

SEC ASIC

ANALOG

FUNCTIONAL BLOCK DIAGRAM

GENERAL DESCRIPTION

The AL1208H is a CMOS 10-bit A/D converter for
video applications. It is a three-step pipelined A/D
converter which consists of sample & hold, three
multiplying DACs, a 4-bit flash adc and three 3-bit
flash adcs.
The maximum conversion rate of AL1208H is 20MSPS
and supply voltage is 5V single.

TYPICAL APPLICATIONS

- PC or computer based video signal processing such

as multi-media, scanner, etc.

- General Purpose video applications including

camcorder, digital video, broad-casting and studio
equipments.

- Medical electronics such as digital scope, transit

recorder, radar.

FEATURES

- Resolution : 10Bit
- Differential Linearity Error : ±1.0 LSB
- Integral Linearity Error : ±1.0 LSB
- Maximum Conversion Rate : 20MSPS
- Sample & Hold Function Implemented
- Low Power Consumption : 175mW
- Power Supply : 5V Single
- Operation Temperature Range : 0ºC ~70ºC

10BIT 20MSPS ADC

AL1208H

ITEST

STBY

sah

mdac1

mdac2

mdac3

flash1

flash2

flash3

flash4

dclogic

mbias

ckgen

CKIN

REFMID

STCB

EOC

AINT

CML

AINC

REFBOT

REFTOP

LINV

MINV

DO[9:0]
OVF
UDF

Ver 1.1 (Feb. 2000)

No responsibility is assumed by SEC for its use nor for any

infringements of patents or other rights of third parties that may
result from its use. The content of this datasheet is subject to
change without any notice

AL1208H

10BIT 20MSPS ADC

SEC ASIC

ANALOG

CORE PIN DESCRIPTION

NAME

I/O TYPE

I/O PAD

PIN DESCRIPTION

AINT

piar50_bb

Analog Input +
(Input Range : 0V ~ 5V)

AINC

piar50_bb

Analog Input : (DC=2.5V)

REFMID

pia_bb

Reference Mid Point (Test Pin)

REFTOP

pia_bb

Reference Top (3.75V)

REFBOT

pia_bb

Reference Bottom(1.25V)

MINV

picc_bb

high=invert MSB(normally gnd)

LINV

picc_bb

high=invert all LSB(normally gnd)

VDDA

vdda

Analog Power ( 5V )

VSSA

vssa

Analog Ground

ITEST

pia_bb

open=use internal bias point

STBY

picc_bb

high=power saving standby mode
(normally = gnd)

CKIN

picc_bb

Sampling Clock Input

CML

pia_bb

Internal Bias Point(Test Pin)

DO[9:0]

pot2_bb

Digital Output

OVF

pot2_bb

Overflow

UDF

pot2_bb

Underflow

STCB

picc_bb

Start of Conversion(normally high)

EOC

pot2_bb

End of Conversion

VBB

vbba

Sub Bias

VSSD

vssd

Digital Ground

VDDD

vddd

Digital Power

CORE CONFIGURATION

I/O TYPE ABBR.

- AI : Analog Input
- DI : Digital Input
- AO : Analog Output
- DO : Digital Output
- AB : Analog Bidirectional
- DB : Digital Bidirectional

- AP : Analog Power
- DP : Digital Power
- AG : Analog Ground
- DG : Digital Ground

al1208h

AINT

EOC

CML

ITEST

REFMID

AINC

REFTOP
REFBOT

DO[9:0]

CKIN
STBY
STCB
MINV

LINV

UDF

OVF

VDDA

VSSA

VBB VDDD

VSSD

2 / 12

AL1208H

10BIT 20MSPS ADC

SEC ASIC

ANALOG

ABSOLUTE MAXIMUM RATINGS

Characteristic

Symbol

Value

Unit

Supply Voltage

VDD

7.0

Analog Input Voltage

AIN

VSS to VDD

Digital Input Voltage

CLK

VSS to VDD

Digital Output Voltage

, V

VSS to VDD

Reference Voltage

REFTOP/REFBOT 3.75 / 1.25

Storage Temperature Range

Tstg

-45 to 125

ºC

NOTES
1. ABSOLUTE MAXIMUM RATING specifies the values beyond which the device may be damaged permanently.

Exposure to ABSOLUTE MAXIMUM RATING conditions for extended periods may affect reliability. Each
condition value is applied with the other values kept within the following operating conditions and function
operation under any of these conditions is not implied.

2. All voltages are measured with respect to VSS unless otherwise specified.
3. 100pF capacitor is discharged through a 1.5K

resistor (Human body model)

RECOMMENDED OPERATING CONDITIONS

Characteristics

Symbol

Min

Typ

Max

Unit

Supply Voltage

VDDA - VSSA
VDDD - VSSD

4.75

5.0

5.25

Supply Voltage Difference

VDDA - VDDD

-0.1

0.0

0.1

Reference Input Voltage(Internally)

REFTOP

REFBOT

-
-

3.75
1.25

-
-

Analog Input Voltage (+)

AINT

Analog Input Voltage (-)

AINC

2.5

Digital Input 'L' Voltage
Digital Input 'H' Voltage

4.5

-
-

0.5

Operating Temperature

Topr

ºC

NOTES
1. It is strongly recommended that all the supply pins (VDDA, VDDD) be powered from the same source to avoid

power latch-up.

3 / 12

AL1208H

10BIT 20MSPS ADC

SEC ASIC

ANALOG

ELECTRICAL

CHARACTERISTICS

Characteristics

Symbol

Min

Typ

Max

Unit

Conditions

Reference Current

IREF

1.8

Differential Linearity Error

DLE

±1.0

LSB

AINT : 0 ~ 5.0V

(Ramp Input)

Integral Linearity Error

ILE

±1.0

LSB

Fck : 1MHz

Bottom Offset Voltage Error

EOB

LSB

Top Offset Voltage Error

EOT

LSB

NOTES
1. Converter Specifications (unless otherwise specified)

VDDA=5.0V

VDDD=5.0V

VSSA=GND

VSSD=GND

Ta=25ºC

2. TBD : To Be Determined

AC ELECTRICAL CHARACTERISTICS

Characteristics

Symbol

Min

Typ

Max

Unit

Conditions

Maximum Conversion Rate

MSPS

AINT : 1MHz Sine Signal
(source resolution > 12bit)

Dynamic Supply Current

Ivdd

fc=20MHz
(without system load)

Signal - to - Noise, Distortion

Ratio

SNDR

AINT = 1MHz
fc = 20MHz

4 / 12

AL1208H

10BIT 20MSPS ADC

SEC ASIC

ANALOG

FUNCTIONAL DESCRIPTION

1. AL1208H is a four step A/D Converter

comprising a 4-bit flash ADC, three 3-bit flash
ADC and three multiplying DAC. The N-bit
flash

ADC

composed

(n-1)

latching

comparators, and multiplying DAC is composed
of 2*(N+2) capacitors and two fully-differential
amplifier.

2. AL1208H operates as follows. During the first

"L" cycle of external clock the analog input data
is tracked and sampled, and the input is held
from the rising edge of the external clock, which
is fed to the first 4-bit flash ADC, and the first
multiplying DAC. Multiplying DAC reconstructs
a voltage corresponding to the first 4-bit ADC's
output, and finally amplifies a residue voltage by
2

. The second 3-bit flash ADC, and MDAC are

worked as same manner, finally amplifiers a
residue voltage, which is the difference between
first MDAC's output and reconstructed voltage by
2

. The third 3-bit flash ADC, and MDAC are

worked as previous stages. Finally amplified
residue voltage at the third multiplying DAC is
fed to the last 3-bit flash ADC decides final
3-bit digital digital code.

3. AL1208H has the error correction scheme, which

handles the output from mismatch in the first,
second, third and fourth flash ADC.

MAIN BLOCK DESCRIPTION

1. SAH

SAH(track and hold) is the circuit that samples

the analog input signal and hold that value until
next sample-time. It is good as small as its
different value between analog input signal and
output signal. SAH amp gain must be higher
than 66dB at least for less than 1/2LSB of SAH
error voltage at 10bit ADC and its conversion
frequency is 20MHz, its settling-time must be
shorten than 18ns. This SAH is consist of fully
differential op amp, switching tr. and sampling

capacitor.

The

sampling

clock

are

non-overlapping

clocks(Q1,Q2)

and

sampling

capacitor value is 1.2pF. SAH uses independent
bias to protect interruption of any other circuit.
SAH amp is designed that open-loop dc gain is
higher than 70dB, phase margin is higher than
60degree. Its input block is designed to be the
rail-to-rail

architecture

using

complementary

different pair.

2. FLASH

The 4-bit flash converter compare analog signal

(SAH output) with reference voltage, and that
result transfer to MDAC and digital correction
logic block. It is realized fully differential
comparators of 15EA. Considering self-offset,
dynamic feed through error, it should distinguish
40mV at least. First, the comparators charge the
reference voltage at the sampling capacitors
before transferred SAH output. Q2 works this
process

and

discharges

this

sampling

capacitance. That is, the comparators compare
relative different values dual input voltage with
dual reference voltage. Its output during Q1
operation is stored at the pre-latch block by
Q1P.

3. MDAC

MDAC is the most important block at this

ADC and it decides the characteristics. MDAC
is consist of amp1,amp2, selection logic and
capacitor array(c_array). C_array's compositions
are the capacitors to charge the analog input and
and the reference voltage, Switches to control
the path. Selection logic controls the c_array
internal switches. If Q1 is high, selection's
output are all low, the switches of tsw1 are off,
the switches of tsw2 are all on. Therefore the
capacitors of c_array charge analog input values
holded at SAH. If Q2 is high, it is reversed and
final MDAC output voltage is described the
following equation.

Vout = (AIN - Vref)*8-Vref/2

AIN=AINT-2.5V

6 / 12

AL1208H

10BIT 20MSPS ADC

SEC ASIC

ANALOG

PACKAGE CONFIGURATION

NOTES
1. You can test ADC function by checking external bidirectional pad connected to internal signal path.
2. ESD (ElectroStatic Discharge) sensitive device. Although the digital control inputs are diode protected, permanent

damage may occur on devices subjected to high electrostatic discharges. It is recommended that unused devices be
stored in conductive foam or shunts to avoid performance degradation or loss of functionality. The protective foam
should be discharged to the destination socket before devices are inserted.

3. NC denotes "No Connection".

AL1208H

13
14

REFMID

VDDA

VSSA

CML

AINC

MINV

VDDA

VSSA

AINT

LINV

VDDR

VSSR

CKIN

36
35

D<2>

D<3>

D<4>

D<5>

D<6>

D<7>

STCB

OVF

UDF

D<9>

D<8>

EOC

VBB

REFTOP

REFBOT

VSSD

VDDD

ITEST

TRISTATE

D<0>

D<1>

Analog Input

(Input Range:0~5V)

Clock Signal

3.75V

Reference

Top

1.25V

Reference

Bottom

PAD Power

Analog Power

GND

Digital

Power

Digital Output Bits 2 Through 9

Digital Output Bits 0 and 1

: 10uF ELECTROLYTIC CAPACITOR
UNLESS OTHERWISE SPECIFIED
: 0.1uF CERAMIC CAPACITOR
UNLESS OTHERWISE SPECIFIED

NOTES

DC 2.5V

9 / 12

AL1208H

10BIT 20MSPS ADC

SEC ASIC

ANALOG

PACKAGE PIN DESCRIPTION

NAME

PIN NO.

I/O TYPE

PIN DESCRIPTION

REFTOP

External Reference Top Bias.(3.75V)

REFBOT

External Reference Bottom Bias.(1.25V)

REFMID

Reference Mid Point ( Test Pin )

VDDA

7,8

5V Analog Power

VSSA

9,10

Analog Grounf

AINT

Analog Input (+)
Input Range : 0~5V

CML

Internal Bias Point ( Test Pin )

AINC

Analog Input. (-)
DC 2.5V

MINV

high = invert MSB(normally gnd)

LINV

high = invert all LSB(normally gnd)

VDDR

Ouput Driver Power

VSSR

Output Driver Ground

STBY

High = power saving standby mode
(normally gnd)

CKIN

Sampling Clock Input

ITEST

open=use internal bias point

TRISTATE

high = high impedance digital output
(normally gnd)

DO[9:0]

27~36

Digital Output

UDF

Underflow Output Signal

OVF

Overflow Output Signal

STCB

Start of Conversion (normally high)

EOC

End of Conversion

VBB

Substrate Ground

VSSD

45,46

Digital Ground

VDDD

47,48

Digital Power

NOTES
1. I/O TYPE PP and PG denote PAD Power and PAD Ground respectively.

10 / 12

AL1208H

10BIT 20MSPS ADC

SEC ASIC

ANALOG

USER GUIDE

1. Resolution Control.

- Modular structure is the most important feature of AL1208H.

- You can get any resolution you want by combining each primary module (MDAC + FLASH) without major

circuit change.

- It means you don't have to redesign the most difficult analog block for another resolution.

- But this simple resolution control method has a limit up to 10bits, otherwise the internal op-amp must be

redesigned.

2. Speed Up

- The initial target speed of AL1208H was 20MHz, but it proved to operate well at 25MHz or more

due to a lot of design margin.

3. Input Range Variation.

- The default of the input of this ADC is differential -2.5V ~ +2.5V.

- The bias voltage of both AINT and AINC is 1.25V~3.75V, and their offset is 2.5V.

- In order to alter to another input voltage range, change the voltage values of AINT and AINC after setting

Reftop and Refbot to the maximum value of input range.

- If you want single ended input, fix AINC to 2.5V as a ground and the internal input voltage level is

V(aint)-2.5V.

4. Verilog Modeling

- Verilog modeling needs 64bits for only one analog real signal.

ain

sha

mdac1

mdac2

mdac3

flash1

flash2

flash3

flash4

dclogic

10bit

module

11 / 12

AL1208H

10BIT 20MSPS ADC

SEC ASIC

ANALOG

FEEDBACK REQUEST

It should be quite helpful to our ADC core development if you specify your system requirements on

ADC in the following characteristic cheking table and fill out the additional questions.

We appreciate your interest in our products. Thank you very much.

Characteristic

Min

Typ

Max

Unit

Remarks

Analog Power Supply Voltage

Digital Power Supply Voltage

Bit Resolution

Bit

Reference Input Voltage

Analog Input Voltage

Vpp

Operating Temperature

ºC

Integral Non-linearity Error

LSB

Differential Non-linearity Error

LSB

Bottom Offset Voltage Error

Top Offset Voltage Error

Maximum Conversion Rate

MSPS

Dynamic Supply Current

Power Dissipation

Signal-to-noise Ratio

Pipeline Delay

CLK

Digital Output Format
(Provide detailed description &
timing diagram)

1. Between single input-output and differential input-output configurations, which one is suitable for your

system and why?

2. Please comment on the internal/external pin configurations you want our ADC to have, if you have

any reason to prefer some type of configuration.

3. Freely list those functions you want to be implemented in our ADC, if you have any.

12 / 12

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