0.35

µ
µ
µ
µ

m 20MHZ-170MHZ FSPLL

AL2007LA

GENERAL DESCRIPTION

The AL2007LA is a Phase-Locked Loop (PLL) frequency synthesizer constructed in CMOS on single monolithic
structure. The PLL macrofunctions provide frequency multiplication capabilities.
The output clock frequency Fout is related to the reference input clock frequency Fin by the following equation:

Fout = ( m*Fin ) / ( p* 2S)

Where, Fout is the output clock frequency. Fin is the reference input clock frequency. m,p and s are the values for
programmable dividers. AL2007LA consists of a phase/Frequency Detector(PFD), a Charge Pump an External
Loop Filter, a Voltage Controlled Oscillator(VCO), a 6bit Pre-divider, an 8bit Main divider and 2bit Post Scaler as
shown in Figure1.

FEATURES

-- 0.35um CMOS device technology

-- 3.3 Volt Single power supply

-- VCO frequency range: 60~170MHz

-- Output frequency range: 20~170MHz

-- Jitter ±150ps

-- Duty ratio 40% to 60% at 170MHz

-- Frequency changed by programmable divider

-- Power down mode

IMPORTANT NOTICE

Please contact SEC application engineer to confirm the proper selection of M,P,S value.

FUNCTIONAL BLOCK DIAGRAM

Pre Divider

Charge

Pump

PFD

VCO

Main Divider

Post Scaler

Loop

Filter

(External)

Fin

Fout

Figure 1. Phase Lockd Loop Block Diagram

AL2007LA

0.35

µ
µ
µ
µ

m 20MHZ-170MHZ FSPLL

CORE PIN DESCRIPTION

Name

I/O Type

I/O Pad

Pin Description

VDD

vddd

Digital power supply

VSS

vssd

Digital ground

VDDA

vdda

Analog power supply

VSSA

vssa

Analog ground

VBB

AB/DB

vbba

Analog/Digital sub bias Power

FIN

picc_bb

PLL clock input

FILTER

poar50_bb

- Pump out is connected to Filter
- A capacitor is connected between the pin and analog ground

FOUT

pot12_bb

20MHz~170MHz clock output

PWRDN

picc_bb

FSPLL clock power down.
- PWRDN is High, PLL do not operating under this condition.
- If isn't used this pin, tied to VSS.

P[5:0]

picc_bb

The values for 6bit programmable pre-divider.

M[7:0]

picc_bb

The values for 8bit programmable main divider.

S[1:0]

picc_bb

The values for 2bit programmable post scaler.

I/O Type Abbr.

-- AI: Analog Input

-- DI: Digital Input

-- AO: Analog Output

-- DO: Digital Output

-- AB: Analog Bidirectional

-- DB: Digital Bidirectional

-- AP: Analog Power

-- DP: Digital Power

-- AG: Analog Ground

-- DG: Digital Ground

AL2007LA

0.35

µ
µ
µ
µ

m 20MHZ-170MHZ FSPLL

ABSOLUTE MAXIMUM RATINGS

Characteristics

Symbol

Value

Unit

Applicable pin

Supply Voltage

VDD

VDDA

-0.3 to 3.8

VDD,VDDA,VSS,VSSA

Voltage on Any Digital Pin

Vin

Vss-0.3 to Vdd+0.3

P[5:0],M[7:0],S[1:0]

PWRDN

Storage Temperature

Tstg

-45 to 125

°C

NOTES:
1.

ABSOLUTE

MAXIMUM

RATING

specifies

the

values

beyond

which

the

device

may

damaged

permanently.

Exposure

ABSOLUTE

MAXIMUM

RATING

conditions

for

extended

periods

may

affect

reliability.

Each

condition

value

applied

with

the

other

values

kept

within

the

following

operating

conditions

and

function

operation

under

any

these

conditions

not

implied.

All

voltages

are

measured

with

respect

VSS

unless

otherwise

specified.

100pF

capacitor

discharged

through

1.5K

resistor

(Human

body

model)

RECOMMENDED OPERATING CONDITIONS

Characteristics

Symbol

Min

Typ

Max

Unit

Supply Voltage Differential

VDD - VDDA

-0.1

+0.1

External Loop Filter Capacitance

820

Operating Temperature

Topr

°C

NOTE: It is

strongly

recommended

that

all

the

supply

pins

(VDDA,

VDD)

powered

from

the

same

source

avoid

power

latch-up.

0.35

µ
µ
µ
µ

m 20MHZ-170MHZ FSPLL

AL2007LA

DC ELECTRICAL CHARACTERISTICS

Characteristics

Symbol

Min

Typ

Max

Unit

Operating Voltage

VDD/VDDA

3.15

3.3

3.45

Digital Input Voltage High

Vih

2.0

Digital Input Voltage Low

Vil

0.8

Dynamic Current

(CORE Level without I/O Cell)

Idd

3.5

Power Down Current

Ipd

120

AC ELECTRICAL CHARACTERISTICS

Characteristics

Symbol

Min

Typ

Max

Unit

Input Frequency

14.318

MHz

Output Clock Frequency

OUT

170

MHz

VCO Output Clock Frequency

Fvco

170

MHz

Input Clock Duty Cycle

Output Clock Duty Cycle

Locking Time

150

Cycle to Cycle Jitter

JCC

-150

+150

AL2007LA

0.35

µ
µ
µ
µ

m 20MHZ-170MHZ FSPLL

FUNCTION DESCRIPTION

A PLL is the circuit synchronizing an output signal (generated by an VCO) with a reference or input signal in
frequency as well as in phase.

In this application, it includes the following basic blocks.

-- The voltage-controlled oscillator to generate the output frequency

-- The divider P devides the reference frequency by p

-- The divider M devides the VCO output frequency by m

-- The divider S divides the VCO output frequency by s

-- The phase frequency detector detects the phase difference between the reference frequency and the output

frequency (after division) and controls the charge pump voltage.

-- The loop filter removes high frequency components in charge pump voltage and does smooth and clean

control of VCO

The m, p, s values can be programmed by 16bit digital data from the external source. So the PLL can be locked in
the desired frequency.

Fout = m * Fin / p*s

If Fin = 14.318MHz, and m=M+8 , p=P+2, s=2^S

Digital data format:

Main Divider

Pre Divider

Post Scaler

M7,M6,M5,M4,M3,M2,M1,M0

P5,P4,P3,P2,P1,P0

S0,S1

NOTES:
1.

S[1] - S[0]: Output Frequency Scaler

M[7] - M[0]: VCO Frequency Divider

P[5] - P[0]: Reference Frequency Input Divider

0.35

µ
µ
µ
µ

m 20MHZ-170MHZ FSPLL

AL2007LA

OUTPUT FREQUENCY EQUATION & TABLE

OU T

(m+8)

(p+2) x 2

x F

(m+8)

(p+2)

Table 1. Example of Divider Ratio

Frequency Equation :

NOTES:
1. Don't set the P or M as zero, that is 000000 / 00000000
2. The proper range of P and M : 1<=P<=62, 1<=M<=248
3. The P and M must be selected considering stability of PLL and VCO output frequency range
4. Please consult with SEC application engineer to select the proper P, M and S values

AL2007LA

0.35

µ
µ
µ
µ

m 20MHZ-170MHZ FSPLL

CORE EVALUATION GUIDE

For the embedded PLL, we must consider the test circuits for the embedded PLL core inmultiple applications.
Hence the following requirements should be satisfied.

-- The FILTER and FOUT pins must be bypassed for external test.

-- For PLL test (Below 2 examples), it is needed to control the dividers - M[7:0],P[5:0] and S[1:0] -that generate

multiple clocks.
Example #1. Registers can be used for easy control of divider values.
Example #2. N sample bits of 16-bit divider pins can be bypassed for test using MUX.

NOTES

: 10uF ELECTROLYTIC CAPACITOR

UNLESS OTHERWISE SPECIFIED

: 103 CERAMIC CAPACITOR

UNLESS OTHERWISE SPECIFIED

FOUT

FILTER

al2007la

#1.16bit Register Block

PWRDN

P[5:0]

S[1:0]

820pF

M[7:0]

FIN

External Clock Source

VDD VSS

VDDA VSSA

3.3V

Digital

Power

3.3V Analog Power

GND

VSSA

Select Pin

Test Pins of N Sample bits

Internal Divider Signal Line

#2
M
U
X

VBBA

0.35

µ
µ
µ
µ

m 20MHZ-170MHZ FSPLL

AL2007LA

CORE LAYOUT GUIDE

-- The digital power(VDD,VSS) and the analog power(VDA,VSSA) must be dedicated to PLL only and seperated.

If the dedicated VDD and VSS is not allowed that of the least power consuming block is shared with the PLL.

-- The PIA pad is used as a FILTER pad that contains only ESD production diodes without any resistors and

buffers.

-- The FOUT and FILTER pins must be placed far from the internal signals in order to avoid overlapping signal

lines.

-- The blocks having a large digital switching current must be located away from the PLL core.

-- The PLL core must be shielded by guardring.

-- For the FOUT pad, you can use a custom drive buffer or POT12 buffer considering the drive current.

WITHOUT XTAL-DRIVER USERS GUIDE

-- There are two crystal driver cell (XTAL-OSC and PSOSCM2) options for the AL2007LA PLL core.

1. If the crystal component not used , an external clock source is applied to the FIN
*

Please contact an SEC application engineer when using a crystal.

2. If the crystal component not used , an external clock I/O Buffer offered from Samsung's STD90 library is

recommanded for use

When implementing an embedded PLL block, the following pins must be bypassed externally for testing
the PLL locking function:

Without Xtal-driver : FIN,FILTER,FOUT,VDDA,VSSA,VDD and VSS.

AL2007LA

0.35

µ
µ
µ
µ

m 20MHZ-170MHZ FSPLL

VDD

VSSA

MUX

FOUT

FILTER

Divider

PFD

&CP

VCO

Divider

VSS

VDDA

Glue Logic

FIN

PWRDN

Scaler

Used PICC_BB PAD

S[1:0]

M[7:0]

P[5:0]

VBBA

* Optional Test Pins

* Divider Bus

Figure 1. The example of PLL block without crystal component (Normal Case)

0.35

µ
µ
µ
µ

m 20MHZ-170MHZ FSPLL

AL2007LA

PACKAGE CONFIGURATION

VDDA

FIN

FILTER

FOUT

al2007la

10uF

103

820pF

6bit Pre Divider Input

Dummy Test Block Control pins

3.3V Digital PAD Power

3.3V Analog Power

2bit Post Scaler

8bit Main Divider

PWRDN

VBBA

3.3V I/O Power

External Clock Source

VBBA

NOTES:
1.

TSEL0,TSEL1 pins are internal dummy block test pins.

NC is Noconnection pin

AL2007LA

0.35

µ
µ
µ
µ

m 20MHZ-170MHZ FSPLL

PACKAGE PIN DESCRIPTION

Name

Pin No

I/O Type

Pin Description

VDDD

35,36

Digital power supply

VSSD

33,34

Digital ground

PWRDN

FSPLL clock power down
-PWRDN is High, PLL do not operating under this
condition.
- If isn't used this pin, tied to VSS.

P[0]~P[5]

1,2,45~48

Pre-Divider Input(LSB)

VDDA

13,14

Analog power supply

VSSA

11,12

Analog ground

VBBA

19,20

AB/DB

Analog / Digtal Sub Bias Power

FIN

Crystal input or external F

REF input

FOUT

20MHZ~170MHz clock output

FILTER

Pump out is connected to the FILTER.
A 820pF Capcitor is connected between the pin and
analog pin

TSEL0

FOUT divide control pins.
-End users used not this pins, tied to VDD or VSS

TSEL1

FOUT divide control pins.
-End users used not this pins, tied to VDD or VSS

S[0]~S[1]

31,32

Post scaler input

M[0]~M[7]

37~44

8bit main divider input

VDDO

I/O PAD Power

VSSO

I/O PAD Ground

NOTE: I/O TYPE PP and PG denote PAD power and PAD ground respectively.

0.35

µ
µ
µ
µ

m 20MHZ-170MHZ FSPLL

AL2007LA

DESIGN CONSIDERATIONS

The following design consideratios apply:

Phase tolerance and jitter are independent of the PLL frequency.

Jitter is affected by the noise frequency in the power(VDD/VSS,VDDA/VSSA). It increases when the noise
level increases.

A CMOS-level input reference clock is recommend for signal compatibility with the PLL circuit. Other levels
such as TTL may degrade the tolerances.

The use of two, or more PLLs requires special design considerations. Please consult your application engineer
for more information.

The following apply to the noise level, which can be minimized by using good analog power and ground
isolation techniques in the system:

- Use wide PCB traces for POWER(VDD/VSS, VDDA/VSSA) connections to the PLL core.

Seperate the traces from the chip's VDD/VSS,VDDA/VSSA supplies.

- Use proper VDD/VSS,VDDA/VSSA de-coupling.

- Use good power and ground sources on the board.

- Use Power VBB for minimize substrate noise

The PLL core should be placed as close as possible to the dedicated loop filter and analog Power and ground
pins.

It is inadvisable to locate noise-generating signals, such as data buses and high-current outputs, near the PLL
I/O cells.

Other related I/O signals should be placed near the PLL I/O but do not have any pre-defined placement
restriction

AL2007LA

0.35

µ
µ
µ
µ

m 20MHZ-170MHZ FSPLL

FEEDBACK REQUEST

Thank you for having an interest in our products. Please fill out this form, especially the items which you want to
request.

Parameter

Customer

SEC

Unit

Process

Supply voltage (VDD)

Input frequency (FIN)

Output frequency (FOUT)

Cycle to cycle jitter (TJCC)

100M ~ 200M

200M ~ 300M

300M ~ 400M

400M ~ 500M

Period jitter (TJP)

100M ~ 200M

200M ~ 300M

300M ~ 400M

400M ~ 500M

Output duty ratio (TOD)

Lock up time (TLT)

Dynamic current

Stand by current

Filter capacitor

-- How many PLLs are embedded in your system ?

-- Do you need synchronization between input clock and output clock ?

-- Do you need another spec of jitter ?

Parameter

Customer

Unit

Long-term jitter (TJLT)

psec (pk-pk)

Tracking Jitter (TJT)

psec (pk-pk)

If you have another special request, please describe below.

0.35

µ
µ
µ
µ

m 20MHZ-170MHZ FSPLL

AL2007LA

JITTER DEFINITION

Period Jitter

Period jitter is the maximum deviation of output clock's transition from its ideal position.

TJP

Fout

Ideal Cycle

Cycle-to-Cycle Jitter

Cycle-to-cycle jitter is the maximum deviation of output clock's transition from its corresponding position of the
previous cycle.

i-1

i+1

Fout

TJCC = max (T

i+1

- T

)

Long-Term Jitter

Long-term jitter is the maximum deviation of output clock' transition from its ideal position, after many cycles. The
term "many" depends on the application and the frequency.

TJLP

Cycle 0

Cycle N

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: al2007la

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: al2007la