COD0408X_R1.PDF

COD0408X_R1

0.25

µ
µ

m VOICE SIGNAL INTERFACE CODEC

DESCRIPTION

This IP Core has been developing for (Analog-front-end) function of Voice Signal with 14bit 8KHz Voice Codec.
The Core consists of 14bit linear monolithic PCM CODEC/transmit and receive band-pass filters utilizing the
Sigma-Delta A/D and D/A conversion Architecture. It offers a number of programmable functions accessed
through a serial control channel that easily interfaces to classical micro controller. This IP Core is suitable digital
mobile phones, as cellular and cordless , or any battery powered equipment.

FEATURES

-- Analog 2.5Volt / Digital 1.8Volt Operation

-- Linear 14bit Codec

-- 3 Mic Inputs (2 Differential and 1 Single)

-- 3 Analog Ouputs 32ohm Driver (2 Differential and 1 Single)

-- Mic Volume 0dB ~ 22.5dB & 20dB Gain On/Off

-- Speaker Volume 0dB ~ -30dB

-- Sidetone -12.5dB ~ -27.5dB

-- Serial Data Input, Output Format

-- Control Register Interface for

-Controller

APPLICATIONS

-- Digital mobile phones

-- Cellular and cordless phone

0.25

µ
µ

m VOICE SIGNAL INTERFACE CODEC

COD0408X_R1

BLOCK DIAGRAM

MICIN

U
X

MICIP

MIC2P
MIC2N
MIC3

AOUT1P

AOUT1N

AOUT2P

AOUT2N

AOUT3N

VREF

IREF
(Test Pin)

Reference

ISS[1:0]

Signal

I/F

PGA

ADC

DAC

Control

PLL

X10

TGN[3:0]

OSS[1:0]

RGN[3:0]

SGN[3:0]

SIDETONE AMP
from-12.5dB to -27.5dB
-1dB Step

STEN

SOUT
SIN

IMCLK
IFSYNC
CLKDIR

OMCLK
OFSYNC

A[8:0]

RDB

WRB

CSB

RSTB

D[7:0]

PLLMCK
FILTER

VDD25A1

VSSA1

VDD25A2

VSSA2

VDD18A3

VSSA3

SPEAKER VOLUME
0dB~30dB
-2.dB Step

MIC VOLUME
0dB~22.5dB
1.5dB Step

20dB

On/Off

Ver 1.0 (Jun 1999)
This data sheet is a preliminary version. No responsibility is assumed by SEC for its use nor for any infringements of patents
or other rights of third parties that may result from its use. The content of this data sheet is subject to change without any
notice.

COD0408X_R1

0.25

µ
µ

m VOICE SIGNAL INTERFACE CODEC

CORE PIN DESCRIPTION

NAME

I/O TYPE

PIN DESCRIPTION

Power pins

VDD25A1

Analog power supply 1 (2.5V)

VSSA1

Analog Ground 1

VDD25A2

Analog Power Supply 2 (2.5V)

VSSA2

Analog Ground 2

VDD18A3

Digital Power Supply 3 (1.8V)

VSSA3

Digital Ground 3

Analog Pins

MIC1P

Mic Input 1 Positive

MIC1N

Mic Input 1 Negative

MIC2P

Mic Input 2 Positive

MIC2N

Mic Input 2 Negative

MIC3

Mic Input 3 (Single Input)

AOUT1P

Differential Output 1 Positive

AOUT1N

Differential Output 1 Negative

AOUT2P

Differential Output 2 Positive

AOUT2N

Differential Output 2 Negative

AOUT3

Single Output

VREF

Reference Output

IREF

Analog Current Control

FILTER

PLL Loop Filter Control

Digital Pins

SOUT

ADC Serial Data Output

SIN

DAC Serial Data Input

IMCLK

Master Clock Input
( If CLKDIR="L", IMCLK="L". If CLKDIR="H", IMCLK is
Active (=2.048MHz) )

IFSYNC

Frame Sync Pulse Input
( If CLKDIR="L", IFSYNC="L". If CLKDIR="H", IFSYNC
is Active )

CLKDIR

Master Clock /Frame Sync Pulse Active Direction Control
Clock
( If CLKDIR="L", OMCLK / OFSYNC is Active State.
If CLKDIR="H", IMCLK / IFSYNC is Active State)

0.25

µ
µ

m VOICE SIGNAL INTERFACE CODEC

COD0408X_R1

CORE PIN DESCRIPTION (Continued)

OMCLK

Master Clock Output
( If CLKDIR="L", OMCLK is Active.(=2.048MHz) If
CLKDIR="H", OMCLK="L" )

OFSYNC

Frame Sync Pulse Output
( If CLKDIR="L", OFSYNC is Active. If CLKDIR="H",
OFSYNC="L" )

RSTB

Power-On-Reset and Reset Control Input (Low Active)

CSB

Chip Select (Low Active)

WRB

Write Enable (Low Active)

RDB

Read Enable (Low Active)

A[8:0]

Control Register Address

D[7:0]

Control Register Data Input (WR is Enabled)
Control Register Data Output (RD is Enabled)

PLLMCLK

PLL Input Clock (=10MHz)

I/O TYPE ABBR.

-- AI: Analog Input

-- DI: Digital Input

-- AO: Analog Output

-- DO: Digital Output

-- AB: Analog Bi-directional

-- DB: Digital Bi-directional

-- AP: Analog Power

-- DP: Digital Power

-- AG: Analog Ground

-- DG: Digital Ground

COD0408X_R1

0.25

µ
µ

m VOICE SIGNAL INTERFACE CODEC

CORE CONFIGURATION

cod0408x_r1

MICIP

MICIN

MIC2P

MIC2N

MIC3

SIN

CLKDIR

IMCLK

IFSYNC

RSTB

CSB

WRB

RDB

A[8:0]

PLLMCK

AOUT1P

AOUT1N

AOUT2P

AOUT2N

AOUT3

SOUT

OMCLK

OFSYNC

FILTER

VREF

D[7:0]

IREF

VDD25A1

VSSA1

VDD25A2

VSSA3

VDD18A3

VSSA2

0.25

µ
µ

m VOICE SIGNAL INTERFACE CODEC

COD0408X_R1

ABSOLUTE MAXIMUM RATINGS

Characteristic

Symbol

Value

Unit

Supply Voltage

VDD25A1
VDD25A2
VDD18A3

3.3V
3.3V
2.5V

Analog Input Voltage

VSSA1 to VDD25A1
VSSA2 to VDD25A2

Digital Input Voltage

VSSA3 to VDD25A3

Digital Output Voltage

VSSA3 to VDD25A3

Storage Temperature Range

Tstg

-45 to 125

NOTES:
1.

ABSOLUTE

MAXIMUM

RATING

specifies

the

values

beyond

which

the

device

may

damaged

permanently.

Exposure

ABSOLUTE

MAXIMUM

RATING

conditions

for

extended

periods

may

affect

reliability.

Each

condition

value

applied

with

the

other

values

kept

within

the

following

operating

conditions

and

function

operation

under

any

these

conditions

not

implied.

All

voltages

are

measured

with

respect

VSS

unless

otherwise

specified.

100pF

capacitor

discharged

through

1.5K

resistor

(Human

body

model)

RECOMMENDED OPERATING CONDITIONS

Characteristics

Symbol

Min

Typ

Max

Unit

Supply Voltage

VDD25A1, VDD25A2

VDD18A3

2.25
1.62

2.5
1.8

2.75
1.98

V
V

Supply Voltage Difference

VDD25A1, VDD25A2

VDD18A3

-0.1

0.0

0.1

Digital Input Voltage

1.62

1.8

1.98

Analog Input Voltage

1.6

Vp-p

Operating Temperature

Topr

NOTE: It

strongly

recommended

that

all

the

supply

pins

(VDD25A1,

VDD25A2)

powered

from

the

same

source

avoid

power

latch-up.

COD0408X_R1

0.25

µ
µ

m VOICE SIGNAL INTERFACE CODEC

AC ELECTRICAL CHARACTERISTICS

(Measurement Bandwidth is 20Hz

4kHz. Full scale input sine wave 1kHz, FS = 8kHz, @VDD25A1 = 2.5V,

VDD25A2 = 2.5V, VDD18A3 = 1.8V, Ta = 25

C, Unless otherwise specified.)

Characteristics

Symbol

Min

Typ

Max

Unit

Conditions

Resolution

Bits

Sampling rate

kHz

ADC Characteristics

Signal to distortion ratio

0dB input: Linear

Offset error

Input noltage range

1.6

Vpp

DAC Characteristics

Signal to distortion ratio

0dB input: Linear

Offset error

Output voltage range

1.6
3.2

-
-

Vpp
Vpp

Differential

PLL Characteristics

Cycle jitter

100

Duty ratio

45:55

Lock time

150

Power Supply

Power consumption
(Operating mode analog
digital)

6.5
0.5

-
-

mA
mA

No load

Power consumption
(Power down mode)

0.25

µ
µ

m VOICE SIGNAL INTERFACE CODEC

COD0408X_R1

TRANSMISSION CHARACTERISTICS

(Measurement

Bandwidth

60Hz

4kHz.

Full

scale,

FS=8kHz,

@VDD25A1=2.5V,

VDD25A2=2.5V,

VDD18A3=1.8V

Ta=25

C, Unless

otherwise

specified.)

Characteristics

Conditions

Min

Typ

Max

Unit

Transmit gain variation with
frequency

Relative to 1000Hz
f = 60Hz
f = 200Hz
f = 300Hz
f = 400Hz~3000Hz
f = 3400Hz
f = 4000Hz
f = 8000Hz

-
-
-
-
-
-
-

-7.9
-1.5
-0.6
-0.2
-1.1

-17.8
-62.8

dB
dB
dB
dB
dB
dB
dB

Receive gain variation with
frequency

Relative to 1000Hz
f = 60Hz
f = 200Hz
f = 300Hz
f = 400Hz~3000Hz
f = 3400Hz
f = 4000Hz

-
-
-

0.6

-
-

-
-
-
-
-
-

-8.2
-1.4
-0.6
-0.2
-0.7

-17.8

dB
dB
dB
dB
dB
dB

Transmit delay

f = 60Hz~3000Hz

750

Receive delay

f = 60Hz~3000Hz

750

COD0408X_R1

0.25

µ
µ

m VOICE SIGNAL INTERFACE CODEC

CONTROL CLOCKS CHARACTERISTICS

Characteristics

Symbol

Min

Typ

Max

Unit

OMCLK Frequency

Fomclk

2.048

MHz

OMCLK Duty Cycle (H/L)

OMcDuty

50:50

OFSYNC Frequency

Fosync

kHz

OFSYNC High Period

Tosynch

488

IMCLK Frequency

Fimclk

2.048

MHz

IMCLK Duty Cycle (H/L)

IMcDuty

50:50

IFSYNC Frequency

Fisync

kHz

IFSYNC High Period

Tisynch

244

488

OMCLK Falling and OFSYNC SetUp

Tsuo

OMCLK Falling and OFSYNC Hold

Thdo

OMCLK Rising and SDOUT Delay

Tdsdout

OMCLK Falling and SIN SetUp

Tsusin

OMCLK Falling and SIN Hold

Thdsin

IMCLK Falling and OFSYNC SetUp

Tsui

IMCLK Falling and OFSYNC Hold

Thdi

IMCLK Rising and SDOUT Delay

Tdsdout

IMCLK Falling and SIN SetUp

Tsusin

IMCLK Falling and SIN Hold

Thdsin

WR Rising and A[8:0] SetUp

Tsuwra

WR Rising and A[8:0] Hold

Thdwra

WR Rising and DATA[7:0] SetUp

Tsuwrd

WR Rising and DATA[7:0] Hold

Thdwrd

RD Falling and A[8:0] SetUp

Tsurda

RD Rising and A[8:0] Hold

Thdrda

RD Falling and DATA[8:0] Delay

Tdrdf

RD Rising and DATA[8:0] Delay

Tdrdr

0.25

µ
µ

m VOICE SIGNAL INTERFACE CODEC

COD0408X_R1

TIMING DIAGRAM

SERIAL DATA INTERFACE

OFSYNC

OMCLK

Tsuo

Thdo

omclk

"H"

"L"

OMcDuty

MSBit

LSBit

Tsusin

SDOUT

Scom to CODEC Timing (When CLKDIR = "L")

Thdsin

OFSYNC

OMCLK

Tsuo

Thdo

omclk

"H"

"L"

OMcDuty

MSBit

LSBit

Tdsdout

SDOUT

CODEC to Scom Timing (When CLKDIR = "L")

COD0408X_R1

0.25

µ
µ

m VOICE SIGNAL INTERFACE CODEC

IFSYNC

IMCLK

Tsui

Thdi

omclk

"H"

"L"

OMcDuty

MSBit

LSBit

Tsusin

SIN

Scom to CODEC Timing (When CLKDIR = "H")

Thdsin

IFSYNC

IMCLK

Tsui

Thdi

imclk

"H"

"L"

IMcDuty

MSBit

LSBit

Tdsdout

SDOUT

CODEC to Scom Timing (When CLKDIR = "H")

OFSYNC

IFSYNC

Tosynch
/Tisynch

Fosync/Fisync

CODEC to Scom Timing (When CLKDIR = "H")

CONTROL REGISTER INTERFACE

Thdwra

A[8:0]

DATA[7:0]

Tsuwra

Thdrda

Tsurda

Thdwrd

Tsuwrd

Don't care

Address

Don't care

Address

Don't care

Write

Don't care

Read

Don't care

Write

Tdrdf

Don't care

Tdrdr

0.25

µ
µ

m VOICE SIGNAL INTERFACE CODEC

COD0408X_R1

PROGRAMMABLE FUNCTIONS

Control Register Mapping Table

ADDRESS

Function

DATA[7:0]

A[8:0]

0D0h

Status

PLOCK

INIT

0D1h

Power
management

PW[2]

PW[1]

PW[0]

0D2h

Path Select

ISS[1]

ISS[0]

STEN

OSS[1]

OSS[0]

0D3h

Mic volume

TGN[3]

TGN[2]

TGN[1]

TGN[0]

0D4h

Speaker volume

RGN[3]

RGN[2]

RGN[1]

RGN[0]

0D5h

Sidetone volume

SGN[3]

SGN[2]

SGN[1]

SGN[0]

0D6h

Miscellaneous

CALDIS

DLB

0D7h

Test path

TLBM

DIBYP

MOBYP

AMOPI

ABYP

ALBM

DLBM

Status Register (0D0H); Read only

Function

PLOCK

INIT

Under initializing
Initialize done

0
1

Not lock
PLL lock detected

0
1

Power Management (0D1H)

Function

PW[2]

PW[1]

PW[0]

All power down
Standby mode
Rx power up, Tx power down
Tx power up, Rx power down
All power up

0
0
0
0
1

0
0
1
1
x

0
1
0
1
x

COD0408X_R1

0.25

µ
µ

m VOICE SIGNAL INTERFACE CODEC

Path Selection (0D2H)

Function

ISS[1]

ISS[0]

STEN

OSS[1] OSS[0]

REN

All muted
MIC1P, MIC1N selected
M1C2P, MICT2N selected
MIC3 selected

0
0
1
1

0
1
0
1

Side tone disabled
Side tone enabled

0
1

All muted
AOUT1P, AOUT1N selected
AOUT2P, AOUT2N selected
AOUT3 selected

0
0
1
1

0
1
0
1

Rx path disabled
Rx path enabled

0
1

Mic Volume Register (0D3H)

Function

T20DB

TGN[3] TGN[2] TGN[1] TGN[0]

0dB selected
20dB selected

0
1

0dB selected
1.5dB selected
-
22.5dB selected

0
0

0
1

Speaker Volume Control Register (0D4H)

Function

RGN[3]

RGN[2]

RGN[1]

RGN[0]

0dB selected
-2dB selected
-
-30dB selected

0
0

0
1

Sidetone Volume Control Register (0D5H)

Function

SGN[3]

SGN[2]

SGN[1]

SGN[0]

-12.5dB selected
-13.5dB selected
-
-27.5dB selected

0
0

0
1

0.25

µ
µ

m VOICE SIGNAL INTERFACE CODEC

COD0408X_R1

Miscellaneous Control Register (0D6H)

Function

CALDIS

DBYP

Calibration function enabled
Calibration function disabled

0
1

Serial data loop back disabled
Serial data loop back enabled

0
1

Test Mode Control Register (0D7H)

Function

TLBM

DIBYP MOBYP

AMOPI

ABYP

ALBM

DLBM

ADC/DAC Loop Mode disabled (*)
ADC/DAC Loop Mode enabled

0
1

Digital decimator filter input bypass
disabled
Digital decimator filter input bypass
enabled

Modulator Output Bypass Disabled (*)
Digital Modulator Ourput Bypass

0
1

Moulator Output / Postfilter Input
Bypass Disabled (*)
Analog Moulator Output / Postfilter
Bypass Enabled (*)

Bypass Disabled (*)
Analog Bypass Enabled

0
1

Loop Back Disabled (*)
Analog Loop Back Enabled

0
1

Loop Back Disabled (*)
Digital Loop Back Enabled

0
1

COD0408X_R1

0.25

µ
µ

m VOICE SIGNAL INTERFACE CODEC

DOWN/UP MANGEMENT GUIDE

COD0408X_R1 is capable of operating at required power when no activity is required. The State of power
down/up is controlled by the Power Management Register(0D1H).

Normal Operation

(All Power Up)

Standby Mode

Rx Power Up

Tx Power Down

Tx Power Up

Rx power Down

All Power Down

The above figure illustrates one example procedure a complete power down/up of COD0408X_R1. From normal
operation sequential writes to the Power Management Register are preformed to power down/up COD0408X_R1
a piece at a time.

0.25

µ
µ

m VOICE SIGNAL INTERFACE CODEC

COD0408X_R1

MIC1P

MIC1M

0.47uF

MIC2P

MIC2M

0.47uF

MIC3

0.47uF

MIC

AOUT1P

AOUT1N

AOUT2P

AOUT2N

AOUT3

SPEAKER

CORE EVALUATION GUIDE

VREF

FILTER

IREF

200pF

10uF

0.1uF

VDD25A1

VDD25A2

10uF

0.1uF

10uF

0.1uF

VSSA1

VSSA2

Analog Ground Plane

Digital Ground Plane

VSSA3

VDD18A3

COD0408X_R1

0.25

µ
µ

m VOICE SIGNAL INTERFACE CODEC

PHANTOM CELL

cod0408x

VREFPR

VREFMR

VASSAC

IREF

VADDAC

VCOMDR

VASSDR

VREF

AVDD25D

AVSS25D

VABB

VADDCR

VABB

VASSCR

14-bit 8K

Voice Codec

VADDO

VASSO

AOUT2P

AOUT2N

AOUT1P

AOUTIN

AOUT3

VCOMR

VCOMMR

MIC3

MIC2P

MIC1P

MIC1N

MIC2N

VADDP

VASSP

VCOMDT

VASSDT

VADDDT

VADDDR

VREFPT

VREFMT

VCOMT

VABB

VASSL

PLLMCK

IMCLK

FILTER

VASSP

VADDP

VADD

VASS

VADD25

VASS25

VADDL

VADDCT

VASSCT

VADDCT

VABB

VASSCT

CSB

A[8:0]

WRB

RDB

DIN[7:0]

DOUT[7:0]

RSTB

SIN

SOUT

OFSYNC

OMCLK

CLKDIR

IFSYNC

COD0408X_R1

0.25

µ
µ

m VOICE SIGNAL INTERFACE CODEC

Pin Name

Pin Usage

Pin Layout Guide

VDD25A1

External

- Maintain the large width of lines as far as the pads.

VSSA1

External

- Place the port positions to minimize the length of power lines.

VDD25A2

External

- Do not merge the analog powers with another power from other
blocks.

VSSA2

External

- Use good power and ground source on board.

VDD18A3

External

VSSA3

External

MIC1P

External

- Do not overlap with digital lines.

MIC2P

External

- Maintain the shortest path to pads.

MIC2N

External

MIC3

External

AOUT1P

External

AOUT1N

External

AOUT2P

External

AOUT2N

External

AOUT3

External

VREF

External

- Maintain the larger width and the shorter length as far as the pads.

IREF

External

- Separate from all other digital lines.

FILTER

External

SOUT

External/Internal

SIN

External/Internal

IMCLK

External/Internal

- Separate from all other analog signals.

IFSYNC

External/Internal

CLKDIR

External/Internal

OMCLK

External/Internal

- Separate from all other analog signals.

OFSYNC

External/Internal

RSTB

External/Internal

CSB

External/Internal

WRB

External/Internal

RDB

External/Internal

A[8:0]

External/Internal

D[7:0]

External/Internal

PLLMCLK

External

COD0408X_R1

0.25

µ
µ

m VOICE SIGNAL INTERFACE CODEC

LAYOUT GUIDE

-- VDD25A1: VADDCT, VADDCR, VADDDT, VADDDR, VADDAC, VADDP, VADD25, VADDL

(All analog power are tied to VDD25A1)

-- VSSA1: VASSCT, VASSCR, VASSDT, VASSDR, VASSP, VASS25, VASSL, VABB

(All analog ground are tied to VSSA1)

-- VDD25A2 = VADDO, VSSA2 = VASSO

-- VADD connect to CDMA power, VASS connect to CDMA ground

-- VCOMR, VCOMMR, VREFPR, VCOMDR, VCOMDT, VREFPT, VCOMT are tied to VREF

-- VREFMR, VREFMT are tied to Analog Ground VSSA1

COD0408X_R1

0.25

µ
µ

m VOICE SIGNAL INTERFACE CODEC

FEEDBACK REQUEST

It should be quite helpful to our CODEC core development if you specify your system requirements on CODEC in
the following characteristic checking table and fill out the additional questions.

We appreciate your interest in our products. Thank you very much.

Could you explain external/internal pin configurations as required?

Specially requested function list:

1. What is your signal band to use, 3.6kHz? 4kHz? or 4.8kHz?

2. What is your analog in/output signal voltage swing? and what kind of format do your want as analog signal

in/output: single or differential format? If you can, Please let us know, what is your exact in/output signal
spec.

3. What is your minimum S/N+D spec?

4. Do you want linear phase characteristic or you don't care on digital filter spec?

Could you give us exact design spec of speech codec? (For example, A-law, m-law and so on.)

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: cod0408x_r1

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: cod0408x_r1