DAC1243X-SR

0.25

µ
µ

m 10-BIT 30MSPS SINGLE CHANNEL DAC

GENERAL DESCRIPTION

This core is a CMOS single-channel 10bit 30MSPS D/A converter for general & video applications. The
dac1243x_sr core is implemented in the Samsung 0.25um 2.5V CMOS process. Digital inputs are coded with
straight binary. This DAC includes independent power down control and the ability to sense output load. An
external(optional) or internal 0.7V reference voltage(VBIAS) and a single external resister define the full-scale
output current together. It uses the two architecture of current-segment and binary-weighted.

FEATURES

-- Maximum conversion rate is 40MSPS

-- +2.5V CMOS monolithic construction

0.75LSB differential linearity (typical)

1.0LSB integral linearity (typical)

-- External or internal voltage reference (Including Band Gap Reference Block)

-- Single Channel DAC

-- 10-Bit parallel Straight Binary Digital input

-- DAC auto-load detection circuitry

-- Temperature : 0 ~ 70

-- Just analog switch power_down enable

TYPICAL APPLICATIONS

-- High Definition Television(HDTV)

-- High Resolution Color Graphics

-- Hard Disk Driver (HDD)

-- CAE/CAD/CAM

-- Image Processing

-- Instrumentation

0.25

µ
µ

m 10-BIT 30MSPS SINGLE CHANNEL DAC

DAC1243X-SR

FUNCTIONAL BLOCK DIAGRAM

Digital
Decode

Segmented

MSBs

Segmented

MSBs

D1[9:0]

PDAC

Auto-load

Detect

Bias_gen

DTOUT

PRE

SEL

ALLPD

IREF

VBIAS

CCOMP

IO1

VDD25AA1,VDD25AD1

VSS25AA1,VSS25AD1

Ver 1.2 (Sep. 2000)

This data sheet is a preliminary version. No responsibility is assumed by SEC for its use nor for any
infringements of patents or other rights of third parties that may result from its use. The content of this data sheet
is subject to change without any notice.

DAC1243X-SR

0.25

µ
µ

m 10-BIT 30MSPS SINGLE CHANNEL DAC

PIN CONFIGURATION

Name

I/O Type

I/O Pad

Pin Description

PDAC

piar50_abb

Power down control just for Analog Switch Block When
activated(high) all current switches are disabled.

CLK

picc_abb

DAC master clock. Input data is latched into the DACs on
the rising edge of CLK.

PRE

piar50_abb

Control strobe for the DAC auto-load detection comparator.
When PRE transitions high-to-low, the auto-load detect
circuit evaluates its analog input. Appropriate settling time
must be allowed before the comparator output (DTOUT) is
used. When not used, PRE should be left high.

D[9:0]

picc_abb

10-bit straight binary, parallel digital input

SEL

picc_abb

Selection control for this DAC output as an input of auto
load-detection function. Enable of load detection for the
DAC is SEL=Low.

ALLPD

piar50_abb

Power down control for Bandgap and all blocks. A high level
disables all analog switches and digital blocks plus the band
gap reference regardless of the states of PDAC

DTOUT

pot8_abb

Comparator output for detection of resistive load at DAC
output. A low at the detect output indicates that the output
voltage of the current selected DAC is above 0.53V and
therefore that no load is attached.

CCOMP

poa_abb

Internal DAC compensation node. Connect external 0.1uF
cap to VDD25AA1.

IRSET

poa_abb

External resistor from this node to VSS25AA1 defines the
full scale output current for the DACs.

VBIAS

poa_abb

External reference voltage output.

VDD25AA1

vdd2t_abb

Analog

Power

(2 pads for this node is recommended.)

VSS25AA1

vss2t_abb

Analog

Ground (2 pads for this node is recommended)

VDD25AD1

vdd2t_abb

Digital

Power

VSS25AD1

vss2t_abb

Digital

Ground

VABB

vbb_abb

Substrate

Bias(the same with ground level)

poa_abb

Analog

Current

Output

I/O TYPE ABBR.

-- AI: Analog Input

-- DI: Digital Input

-- AO: Analog Output

-- DO: Digital Output

-- AB: Analog Bidirectional

-- DB: Digital Bidirectional

-- AP: Analog Power

-- DP: Digital Power

-- AG: Analog Ground

-- DG: Digital Ground

DAC1243X-SR

0.25

µ
µ

m 10-BIT 30MSPS SINGLE CHANNEL DAC

ABSOLUTE MAXIMUM RATINGS

Characteristic

Symbol

Value

Unit

Supply Voltage

VDD25AA1 - VSS25AA1

VDD25AD1 - VSS25AD1

2.5

Voltage on Any Digital Pin

CLK

VSS25AD1-0.25 to

VDD25AD1+0.25

Storage Temperature Range

stg

-45 ~ 125

NOTES:
1. ABSOLUTE MAXIMUM RATING specifies the values beyond which the device may be damaged permanently. Exposure

to ABSOLUTE MAXIMUM RATING conditions for extended periods may affect reliability. Each condition value is applied
with the other values kept within the following operating conditions and function operation under any of these conditions

not implied.

All voltages are measured with respect to GND unless otherwise specified

3. Applied voltage must be limited to specified range.

RECOMMENDED OPERATING CONDITIONS

Characteristics

Symbol

Min

Typ

Max

Unit

Operating Supply Voltage

VDD25AD1,VDD25AA1

2.25

2.5

2.75

Digital Input Voltage High

1.75

2.5

Digital Input Voltage Low

0.0

0.75

Operating Temperature
Range

Topr

Output Load(effective)

37.5

Reference Load(effective)
Resistor

Rset

658

Reference Voltage

BIAS

0.7

Data Input Setup Time

Data Input Hold Time

Clock Cycle Time

CLK

Clock Pulse Width High

PWH

Clock Pulse Width Low

PWL

Zero_level Voltage

-10

-5

+10

IRSET Current

REF

0.9

1.06

1.1

NOTE: It is strongly recommended that all the supply pins (VDD25AA1,VDD25AD2) be powered from the same source and

all the ground pins(VSS25AA1,VSS25AD1,VABB) avoid power latch-up.

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