GENERAL DESCRIPTION
The DAC1252X_JVC is a CMOS 8BIT D/A converter
for general application. This digital to analog converter
has a R2R structure.
Its settling time is 500ns (Typical value).
TYPICAL APPLICATIONS
Hard Disk Drive (HDD)
Battery Operated Instruments
Motor Control Systems
General Applications
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Resolution : 8BIT
Differential Linearity Error : 1.0 LSB
Integral Linearity Error : 1.0 LSB
Settling Time : 500ns
Low Power Consumption : 890uA
Power Down Mode
Operation Temperature Range : 0C ~ 70C
Power Supply : 2.5V Single and 1.8V single
2.5V 8BIT 2MSPS DAC
DAC1252X_JVC
SAMSUNG ELECTRONICS Co. LTD
Ver 1.0 (June 2000)
This datasheet is a preliminary version. No responsibility is
assumed by SEC for its use nor for any infringements of patents
or other rights of third parties that may result from its use. The
content of this datasheet is subject to change without any notice.
D[7:0]
R2R
VRB
VRT
VOUT
AVDD25A
AVSS25A
AVDD25D
AVSS25D
AVBB25A
AMP
_
+
PD
AVDD18D
Level Shifter
SEC ASIC
DAC1252X_JVC
2.5V 8BIT 2MSPS DAC
ANALOG
CORE PIN DESCRIPTION
NAME
I/O
TYPE
I/O PAD
PIN DESCRIPTION
D[7:0]
DI
picc_abb
Digital Input Data (8BIT)
D[7] : MSB , D[0] : LSB
PD
DI
picc_abb
Power Down (Active Low)
VRT
AB
pia_abb
Voltage Reference Top
VRB
AB
pia_abb
Voltage Reference Bottom
VOUT
AO
poa_abb
Analog Voltage Output
AVDD25A
AP
vdd2t_abb
Analog Power (+2.5V)
AVSS25A
AG
vdd2t_abb
Analog Ground (0.0V)
AVDD25D
DP
vdd2t_abb
Digital Power (+2.5V)
AVSS25D
DG
vss2t_abb
Digital Ground (0.0V)
AVDD18D
DP
vss1t_abb
Digital power (+1.8V)
AVBB25A
AG
vbb_abb
Analog Sub Bias (0.0V)
CORE CONFIGURATION
I/O TYPE ABBR.
AI : Analog Input
DI : Digital Input
AO : Analog Output
DO : Digital Output
AB : Analog Bidirectional
DB : Digital Bidirectional
AP : Analog Power
DP : Digital Power
AG : Analog Ground
DG : Digital Ground
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VRT
VRB
D[7:0]
VOUT
AVDD25A
AVSS25A
AVDD25D
AVSS25D
AVBB25A
PD
dac1252X_jvc
AVDD18D
SEC ASIC
DAC1252X_JVC
2.5V 8BIT 2MSPS DAC
ANALOG
ABSOLUTE MAXIMUM RATINGS
Characteristics
Symbol
Value
Unit
Supply Voltage
VDD (AVDD25A,AVDD25D)
3.3
V
Analog Output Voltage
VOUT
AVSS25A to AVDD25A
V
Digital Input Voltage
D[7:0]
VSS25D to AVDD18D
V
Reference Voltage
VRT
VRB
AVDD25A
AVSS25A
V
Operating Temperature Range
Topr
0 to 70
C
NOTES :
1. ABSOLUTE MAXIMUM RATING specifies the values beyond which the device may be damaged permanently.
Exposure to ABSOLUTE MAXIMUM RATING conditions for extended periods may affect reliability. Each condition
value is applied with the other values kept within the following operating conditions and function operation under any
of these conditions is not implied.
2. All voltages are measured with respect to VSS(AVSS25A or VSS25AD0 or AVBB25A) unless otherwise specified.
3. 100pF capacitor is discharged through a 1.5k
resistor (Human body model)
RECOMMENDED OPERATING CONDITIONS
Characteristics
Symbol
Min
Typ
Max
Unit
Supply Voltage
AVDD25A - AVSS25A
AVDD25D - VSS25AD0
2.375
2.5
2.625
V
Supply Voltage Difference
AVDD25A - AVDD25D
-0.1
0.0
0.1
V
Reference Voltage
VRT
VRB
-
0.0
-
-
2.5
-
V
Digital Input 'Low' Voltage
Digital Input 'High' Voltage
VIL
VIH
-
0.7
AVDD18D
-
-
0.3
VDD18D
-
V
Operating Temperature
Topr
0
-
70
C
NOTE :
It is strongly recommended that to avoid power latch-up all the supply pins(AVDD25A,AVDD25D)
be driven from the same source.
3 / 10
SEC ASIC
DAC1252X_JVC
2.5V 8BIT 2MSPS DAC
ANALOG
DC ELECTRICAL CHARACTERISTICS
(Converter Specifications : AVDD25A=AVDD25D=2.5V, AVSS25A=VSS25AD0=AVBB25A=0V,
PD=High, Top=25C, VRT=2.5V, VRB=0.0V unless otherwise specified.)
Characteristics
Symbol
Min
Typ
Max
Unit
Conditions
Resolution
Bit
-
8
-
Bits
-
Differential Linearity Error
DLE
-
1.0
-
LSB
-
Integral Linearity Error
ILE
-
1.0
-
LSB
-
Zero Scale Error
1
V
ZSE
-
5
-
mV
VRT=2.5V , VRB=0.0V
Full Scale Voltage Error
2
V
FSE
-
5
-
mV
Maximum Output Voltage
Vo
MAX
-
2.499
-
V
Vo
MAX
= VOUT(D[7:0]=High)
V
LSB
= Vo
MAX
/ 256
LSB Size
V
LSB
-
0.61
-
mV
NOTE 1 : V
ZSE
=VOUT(D[7:0]=Low) - VRB
2 : V
FSE
=VOUT(D[7:0]=High) - {(VRT-VRB)
255/256 + VRB}
AC ELECTRICAL CHARACTERISTICS
(Converter Specifications : AVDD25A=AVDD25D=2.5V, AVSS25A=VSS25AD0=AVBB25A=0V, load cap=25pF
Top=25C, PD=High, VRT=2.45V, VRB=0.05V unless otherwise specified.)
Characteristics
Symbol
Min
Typ
Max
Unit
Conditions
Supply Current
Ivdd1
-
0.89
-
mA
Ivdd1 = I
VDD28AA0
+ I
AVDD25D
VRT=2.5V , VRB = 0.0V
Data Input : All Low or All High
Ivdd2
-
1.22
-
mA
Ivdd2 = I
AVDD25A
+ I
AVDD25D
Data Input : All Low or All High
Supply Current
(Power Down Mode)
Ivdd3
-
-
10
uA
Ivdd3 = I
AVDD25A
+ I
AVDD25D
Data Rate = 2MHz
Load cap = 25pF , PWDN=LOW
Short Circuit Current
I
SC
-
12
-
mA
VOUT : AVSS25A or AVDD25A
Data Input : All High or All Low
Analog Output Delay
Td
-
65
-
ns
Data Rate = 2MHz
Data : All LOW
All HIGH
Analog Output Rise Time
Tr
-
100
-
ns
Data Rate = 2MHz
Data : All LOW
All HIGH
Analog Output Fall Time
Tf
-
100
-
ns
Data Rate = 2MHz
Data : All HIGH
All LOW
Analog Output
Settling Time
Ts
-
500
-
ns
Data Rate = 2MHz
Data : All LOW
All HIGH
Power Down Off Time
Ton
-
500
-
ns
PD : HIGH
LOW
Power Down On Time
Toff
-
500
-
ns
PD : LOW
HIGH
4 / 10
SEC ASIC
DAC1252X_JVC
2.5V 8BIT 2MSPS DAC
ANALOG
TIMING DIAGRAM
1. Output delay measured from the 50% point of the rising edge of input data to the full scale transition.
2. Settling time measured from the 50% point of full scale transition to the output remaining within 1/2 LSB.
3. Output rise/fall time measured between the 10% and 90% points of full scale transition.
FUNCTIONAL DESCRIPTION
1. The DAC1252X_JVC has a 8BIT R-2R block, two decoders, two OP amps, and control block.
2. The digital outputs of two decoders decide the voltage level of R2R block.
V
VRT VRB
2
(
* Dn)
Rstring
8
n
n 0
8
2
=
-
=
3. Normal Conditions : VRT=2.45V , VRB=0.05V, PD=High
You can change the voltages of VRT and VRB to 2.5V and 0.0V , but the performance of DAC1252X_JVC
will be degraded.
DATA
VOUT
Td
00000000
11111111
50%
50%
VOUT
00000000
11111111
00000000
10%
90%
DATA
Tr
Tf
VOUT
00000000
11111111
00000000
50%
0.5LSB
DATA
Ts
PD
VOUT
Ton
50%
Toff
50%
0.5LSB
0.5LSB
0.0V
5 / 10
SEC ASIC
DAC1252X_JVC
2.5V 8BIT 2MSPS DAC
ANALOG
CORE EVALUATION GUIDE
TESTABILITY
Whether you use MUX or the internal logic for testability, it is required to be able to select
the values of digital inputs ( D[7:0] ).
See above figure. Only if it is, you can check the main functon. ( Linearity )
Normal Test Condition : VRT=2.45V , VRB=0.05V , PD=High
LOCATION
DESCRIPTION
Ct
10uF TANTALUM CAPACITOR
Cc
0.1uF CERAMIC CAPACITOR
6 / 10
HOST
DSP
CORE
MUX
TEST PATH
8
8
8
Cc
Ct
AVDD25A
AVSS25A
AVDD25D
AVSS25D
AVBB25A
2.5V
GND
2.5V
GND
Ct
Cc
Ct
Cc
2.45
V
GND
0.05
V
GND
D[11:0]
PD
VRT
VRB
VOUT
Dac1252x_
jvc
VOUT
AVDD18D
Cc
Ct
1.8V
Cc
Ct
SEC ASIC
DAC1252X_JVC
2.5V 8BIT 2MSPS DAC
ANALOG
CORE LAYOUT GUIDE
1. It is recommended that you use thick analog power metal. when connecting to PAD, the path should
be kept as short as possible.
2. Digital power and analog power are separately used.
3. When the core block is connected to other blocks, it must be double guard-ring using N-well and P+
active to remove the substrate and coupling noise.
In that case, the power metal should be connected to PAD directly.
4. The Bulk power is used to reduce the influence of substrate noise.
5. Digital input signal lines must be same length to reduce the difference of delay.
7 / 10
P+ Guardring
NWELL Guardring
VOUT
PD
VRT
VRB
D[7:0]
AVDD25A
AVSS25A
AVBB25A
AVSS25D
R2R Ladder
&
Level Shifter
OPAMP
AVDD18D
SEC ASIC
DAC1252X_JVC
2.5V 8BIT 2MSPS DAC
ANALOG
PC BOARD LAYOUT CONSIDERATION
1. PC Board Considerations
To minimize noise on the power lines and the ground lines, the digital inputs
need to be shielded and decoupled. This trace length between groups
of VDD (AVDD25A,AVDD25D) and VSS (AVSS25A,VSS25AD0) pins should be as short as possible
so as to minimize inductive ringing.
2. Supply Decoupling and Planes
For the decoupling capacitor between the power line and the ground line, 0.1uF
ceramic capacitor is used in parallel with a 10uF tantalum capacitor.
The digital power plane(AVDD25D) and analog power plane(AVDD25A) are connected
through a ferrite bead, and also the digital ground plane(VSS25AD0) and the analog
ground plane(AVSS25A). This ferrite bead should be located within 3inches of
the DAC1252X_JVC. The analog power plane supplies power to the DAC1252X_JVC of
the analog output pin and related devices.
8 / 10
SEC ASIC
DAC1252X_JVC
2.5V 8BIT 2MSPS DAC
ANALOG
FEEDBACK REQUEST
We appreciate your interest in out products.
If you have further questions, please specify in the attached form.
Thank you very much.
DC / AC ELECTRICAL CHARACTERISTIC
Characteristics
Min
Typ
Max
Unit
Remarks
Supply Voltage
V
Power dissipation
mW
Resolution
Bits
Analog Output Voltage
V
Operating Temperature
C
Output Load Capacitor
pF
Output Load Resistor
C
Integral Non-Linearity Error
LSB
Differential Non-Linearity Error
LSB
Maximum Conversion Rate
MHz
VOLTAGE OUTPUT DAC
Reference Voltage TOP
BOTTOM
V
Analog Output Voltage Range
V
Digital Input Format
Binary Code or 2's Complement Code
CURRENT OUTPUT DAC
Analog Output Maximum Current
mA
Analog Output Maximum Signal Frequency
kHz
Reference Voltage
V
External Resistor for Current Setting(RSET)
W
Pipeline Delay
sec
- Do you want to Power down mode?
- Do you want to Interal Reference Voltage(BGR)?
- Which do you want to Serial Input TYPE or parallel Input TYPE?
- Do you need 3.3V and 5V power supply in your system?
9 / 10
SEC ASIC
DAC1252X_JVC
2.5V 8BIT 2MSPS DAC
ANALOG
HISTORY CARD
Version
Date
Modified Items
Comments
1.0
Jun.00
New generate dac1252x_jvc
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