Revision 1.0
April 2005
K1B3216BDD
- 1 -
UtRAM
Document Title
2Mx16 bit Synchronous Burst Uni-Transistor Random Access Memory
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.
Revision History
Revision No.
0.0
0.1
1.0
Remark
Preliminary
Preliminary
Final
History
Initial Draft
- Design target
Revised
- Corrected the name of 9th row of balls on the pakage to 'J' from 'I'
on page.2 and page.42
Finalize
Draft Date
September 02, 2004
November 01, 2004
April 06, 2005
Revision 1.0
April 2005
K1B3216BDD
- 2 -
UtRAM
2M x 16 bit Synchronous Burst Uni-Transistor CMOS RAM
FEATURES
Process Technology: CMOS
Organization: 2M x16 bit
Power Supply Voltage: 1.7~2.0V
Three State Outputs
Supports MRS (Mode Register Set)
MRS control - Software Control
Supports Driver Strength Optimization for system environment
Supports Async. 4-Page Read
/
Async. Write Mode
Supports Sync. Burst Read / Async. Write Mode
(Address Latch Type and Low ADV Type)
Supports Sync. Burst Read / Sync. Burst Write Mode
- Supports 4 word / 8 word / 16 word burst Length
- Supports Linear(Wrap) Burst type
- Latency support : Latency 5 @ 66MHz(tCD 10ns)
Latency 4 @ 54MHz(tCD 10ns)
- Supports Burst Read Suspend
- Supports Burst Write Data Masking by /UB & /LB control
- Supports WAIT function to indicate data availability.
Max. Burst Clock Frequency : 66MHz
Package Type : 54 FBGA 6.00 x 8.00
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice
.
Fig.1 PIN DESCRIPTION
Table 1. PRODUCT FAMILY
Product Family
Operating Temp.
Vcc Range
Clock Freq.
(Max)
Async. Speed
(tAA)
Power Dissipation
PKG Type
Standby
(I
SB1
, Max.)
Operating
(I
CC2
, Max.)
K1B3216BDD-I Industrial(-40~85
C)
1.7~2.0V
66MHz
70ns
100uA
35mA
54 FBGA
6.00 x 8.00
* PS must be tied to V
CC.
Name
Function
Name
Function
CLK
Clock Input
V
CC
Power Supply
ADV
Address Input Valid
V
CCQ
I/O Power Supply
PS*
Power Save
V
SS
Ground
CS
Chip Select
V
SSQ
I/O Ground
OE
Output Enable Input
UB
Upper Byte(I/O
9
~
16
)
WE
Write Enable Input
LB
Lower Byte(I/O
1
~
8
)
A
0
~A
20
Address Inputs
WAIT
Data Availability
I/O
1
~I/O
16
Data Inputs/Outputs
DNU
Do Not Use
Table 2. PIN DESCRIPTION
GENERAL DESCRIPTION
The world is moving into the mobile multi-media era and there-
fore the mobile handsets need much bigger memory capacity to
handle the multi-media data. SAMSUNG's UtRAM products are
designed to meet all the request from the various customers
who want to cope with the fast growing mobile market. UtRAM is
the perfect solution for the mobile market with its low cost, high
density and high performance feature. K1B3216BDD is fabri-
cated by SAMSUNG
s advanced CMOS technology using one
transistor memory cell. The device supports the traditional
SRAM like asynchronous bus operation (asynchronous page
read and asynchronous write), the NOR flash like synchronous
bus operation (synchronous burst read and asynchronous write)
and the fully synchronous bus operation (synchronous burst
read and synchronous burst write). These three bus operation
modes are defined through the mode register setting. The opti-
mization of output driver strength is possible through the mode
register setting to adjust for the different data loadings. Through
this driver strength optimization, the device can minimize the
noise generated on the data bus during read operation.
LB
OE
A0
A1
A2
PS
I/O9
UB
A3
A4
CS
I/O1
I/O10
I/O11
A5
A6
I/O2
I/O3
Vssq
I/O12
A17
A7
I/O4
Vcc
Vccq
I/O13
DNU
A16
I/O5
Vss
I/O15
I/O14
A14
A15
I/O6
I/O7
I/O16
A19
A12
A13
WE
I/O8
A18
A8
A9
A10
A11
A20
WAIT
CLK
ADV
DNU
DNU
DNU
54-FBGA - 6.00 x 8.00 Top View (Ball Down)
1
2
3
4
5
6
A
B
C
D
E
F
G
H
J
Revision 1.0
April 2005
K1B3216BDD
- 3 -
UtRAM
CONTENTS
Revision History
Features and General Description
Power Up Sequence
Functional Description
Mode Register Setting Operation
Mode Register Setting Timing
Asynchronous Operation
Asynchronous 4 Page Read Operation
Asynchronous Write Operation
Asynchronous Write Operation in Synchronous Mode
Synchronous Burst Operation
Synchronous Burst Read Operation
Synchronous Burst Write Operation
Synchronous Burst Operation Terminology
Clock
Latency Count
Burst Length
Burst Stop
WAIT Control
Burst Type
Product List
Absolute Maximum Ratings
Recommended DC Operating Conditions
Capacitance
DC and Operating Characteristics
Asynchronous AC Characteristics
Asynchronous Timing Waveforms
Synchronous AC Characteristics
Synchronous Timing Waveforms
Transition Timing Waveforms
Package Dimension
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2
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Page
Revision 1.0
April 2005
K1B3216BDD
- 4 -
UtRAM
LIST of TABLES
Table 1. Product Family
Table 2. Pin Description
Table 3. Asynchronous 4 Page Read & Asynchronous Write Mode Truth Table
Table 4. Synchronous Burst Read & Asynchronous Write Mode Truth Table
Table 5. Synchronous Burst Read & Synchronous Burst Write Mode Truth Table
Table 6. Mode Register Setting according to Field of Function
Table 7. Mode Register Set.
Table 8. Latency Count Support
Table 9. Number of Clocks for 1st Data
Table 10. Burst Sequence
Table 11. Product List
Table 12. Absolute Maximum Ratings
Table 13. Recommended DC Operating Conditions
Table 14. Capacitance
Table 15. DC and Operating Characteristics
Table 16. Asynchronous AC Characteristics
Table 17. Asynchronous Read AC Characteristics
Table 18. Asynchronous Page Read AC Characteristics
Table 19. Asynchronous Write AC Characteristics(WE Controlled)
Table 20. Asynchronous Write AC Characteristics(UB & LB Controlled)
Table 21. Asynch. Write in Synch. Mode AC Characteristics(Address Latch Type, WE Controlled)
Table 22. Asynch. Write in Synch. Mode AC Characteristics(Address Latch Type, UB & LB Controlled)
Table 23. Asynch. Write in Synch. Mode AC Characteristics(Low ADV Type, WE Controlled)
Table 24. Asynch. Write in Synch. Mode AC Characteristics(Low ADV Type, UB & LB Controlled)
Table 25. Asynch. Write in Synch. Mode AC Characteristics(Low ADV Type Multiple Write, WE Controlled)
Table 26. Synchronous AC Characteristics
Table 27. Burst Operation AC Characteristics
Table 28. Burst Read AC Characteristics(CS Toggling Consecutive Burst)
Table 29. Burst Read AC Characteristics(CS Low Holding Consecutive Burst)
Table 30. Burst Read AC Characteristics(Last Data Sustaining)
Table 31. Burst Write AC Characteristics(CS Toggling Consecutive Burst)
Table 32. Burst Write AC Characteristics(CS Low Holding Consecutive Burst)
Table 33. Burst Read Stop AC Characteristics
Table 34. Burst Write Stop AC Characteristics
Table 35. Burst Read Suspend AC Characteristics
Table 36. Burst Read to Asynch. Write(Address Latch Type) AC Characteristics
Table 37. Burst Read to Asynch. Write(Low ADV Type) AC Characteristics
Table 38. Asynch. Write(Address Latch Type) to Burst Read AC Characteristics
Table 39. Asynch. Write(Low ADV Type) to Burst Read AC Characteristics
Table 40. Burst Read to Burst Write AC Characteristics
Table 41. Burst Write to Burst Read AC Characteristics
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2
8
8
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10
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Page
Revision 1.0
April 2005
K1B3216BDD
- 5 -
UtRAM
LIST of FIGURES
Figure 1. Pin Description
Figure 2. Functional Block Diagram
Figure 3. Power Up Timing
Figure 4. Standby Mode State Machine
Figure 5. Mode Register Setting Timing
Figure 6. Asynchronous 4-Page Read
Figure 7. Asynchronous Write
Figure 8. Synchronous Burst Read
Figure 9. Synchronous Burst Write
Figure 10. Latency Configuration(Read)
Figure 11. WAIT Control and Read/Write Latency Control
Figure 12. AC Output Load Circuit(Asynchronous)
Figure 13. Timing Waveform of Asynchronous Read Cycle
Figure 14. Timing Waveform of Page Read Cycle
Figure 15. Timing Waveform of Write Cycle(Asynchronous, WE Controlled)
Figure 16. Timing Waveform of Write Cycle(Asynchronous, UB & LB Controlled)
Figure 17. Timing Waveform of Write Cycle(Asynchronous, Address Latch Type, WE Controlled)
Figure 18. Timing Waveform of Write Cycle(Asynchronous, Address Latch Type, UB & LB Controlled)
Figure 19. Timing Waveform of Write Cycle(Asynchronous, Low ADV Type, WE Controlled)
Figure 20. Timing Waveform of Write Cycle(Asynchronous, Low ADV Type, UB & LB Controlled)
Figure 21. Timing Waveform of Multiple Write Cycle(Asynchronous, Low ADV Type, WE Controlled )
Figure 22. AC Output Load Circuit(Synchronous)
Figure 23. Timing Waveform of Basic Burst Operation
Figure 24. Timing Waveform of Burst Read Cycle(CS Toggling Consecutive Burst Read)
Figure 25. Timing Waveform of Burst Read Cycle(CS Low Holding Consecutive Burst Read)
Figure 26. Timing Waveform of Burst Read Cycle(Last Data Sustaining)
Figure 27. Timing Waveform of Burst Write Cycle(CS Toggling Consecutive Burst Write)
Figure 28. Timing Waveform of Burst Write Cycle(CS Low Holding Consecutive Burst Write)
Figure 29. Timing Waveform of Burst Read Stop by CS
Figure 30. Timing Waveform of Burst Write Stop by CS
Figure 31. Timing Waveform of Burst Read Suspend Cycle
Figure 32. Synch. Burst Read to Asynch. Write(Address Latch Type) Timing Waveform
Figure 33. Synch. Burst Read to Asynch. Write(Low ADV Type) Timing Waveform
Figure 34. Asynch. Write(Address Latch Type) to Synch. Burst Read Timing Waveform
Figure 35. Asynch. Write(Low ADV Type) to Synch. Burst Read Timing Waveform
Figure 36. Synch. Burst Read to Synch. Burst Write Timing Waveform
Figure 37. Synch. Burst Write to Synch. Burst Read Timing Waveform
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7
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