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Revision 1.0
April 2005
K1S6416BCC
- 1 -
UtRAM
Document Title
4Mx16 bit Page Mode Uni-Transistor Random Access Memory
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.
Revision History
Revision No.
0.0
1.0
Remark
Preliminary
Final
History
Initial Draft
- Design Target
Finalize
Draft Date
November 3, 2004
April 06, 2005
Revision 1.0
April 2005
K1S6416BCC
- 2 -
UtRAM
PRODUCT FAMILY
Product Family
Operating Temp.
Vcc Range
Speed
(t
RC
)
Power Dissipation
PKG Type
Standby
(I
SB1
, Max.)
Operating
(I
CC2
, Max.)
K1S6416BCC-I
Industrial(-40~85
C)
1.7~2.0V
70ns
120
A(< 40
C)
40mA
TBD
180
A(< 85
C)
4M x 16 bit Page Mode Uni-Transistor CMOS RAM
GENERAL DESCRIPTION
The K1S6416BCC is fabricated by SAMSUNG
s advanced
CMOS technology using one transistor memory cell. The device
supports 4 page read operation and Industrial temperature
range. The device supports dual chip selection for user inter-
face. The device also supports internal Temperature Compen-
sated Self Refresh mode for the standby power saving at room
temperature range.
FEATURES
Process Technology: CMOS
Organization: 4M x16 bit
Power Supply Voltage: 1.7~2.0V
Three State Outputs
Compatible with Low Power SRAM
Support 4 page read mode
Package Type: TBD
PIN DESCRIPTION
1) Reserved for future use
2) V
CC
and V
CCQ
should be the same level
Name
Function
Name
Function
CS1,CS2 Chip Select Inputs
Vcc/V
CCQ
2)
Power Supply(core / I/O)
OE
Output Enable Input
Vss
Ground
WE
Write Enable Input
UB
Upper Byte(I/O
9
~
16
)
A
0
~A
21
Address Inputs
LB
Lower Byte(I/O
1
~
8
)
I/O
1
~I/O
16
Data Inputs/Outputs
NC
No Connection
1)
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice
.
FUNCTIONAL BLOCK DIAGRAM
Clk gen.
Row
select
I/O
1
~I/O
8
Data
cont
Data
cont
Data
cont
I/O
9
~I/O
16
V
CC
V
SS
Precharge circuit.
Memory array
I/O Circuit
Column select
WE
OE
UB
CS1
LB
Control Logic
CS2
Row
Addresses
Column Addresses
TBD
V
CCQ
Revision 1.0
April 2005
K1S6416BCC
- 3 -
UtRAM
POWER UP SEQUENCE
1. Apply power.
2. Maintain stable power(Vcc min. and V
CCQ
min.=1.7V) for a minimum 200
s with CS1=high.or CS2=low.
Min. 200
s
TIMING WAVEFORM OF POWER UP(1)
(CS
1
controlled)
TIMING WAVEFORM OF POWER UP(2)
(CS
2
controlled)
POWER UP(2)
1. After V
CC
reaches V
CC
(Min.) and V
CCQ
(Min.), wait 200
s with CS
2
low. Then the device gets into the normal operation.
V
CC
CS
1
CS
2
V
CC(Min)
POWER UP(1)
1. After V
CC
reaches V
CC
(Min.) and V
CCQ
(Min.), wait 200
s with CS
1
high. Then the device gets into the normal operation.
Min. 200
s
V
CC
CS
1
CS
2
V
CC(Min)
Normal Operation
Power Up Mode
Normal Operation
Power Up Mode
V
CCQ
V
CCQ(Min)
V
CCQ
V
CCQ(Min)
Revision 1.0
April 2005
K1S6416BCC
- 4 -
UtRAM
ABSOLUTE MAXIMUM RATINGS
1)
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be
restricted to be used under recommended operating condition. Exposure to absolute maximum rating conditions longer than 1 second may affect reli-
ability.
Item
Symbol
Ratings
Unit
Voltage on any pin relative to Vss
V
IN
, V
OUT
-0.2 to V
CCQ
+0.3V
V
Voltage on Vcc supply relative to Vss
V
CC
-0.2 to 2.5V
V
Power Dissipation
P
D
1.0
W
Storage temperature
T
STG
-65 to 150
C
Operating Temperature
T
A
-40 to 85
C
FUNCTIONAL DESCRIPTION
1. X means don
t care.(Must be low or high state)
CS1
CS2
OE
WE
LB
UB
I/O
1~8
I/O
9~16
Mode
Power
H
X
1)
X
1)
X
1)
X
1)
X
1)
High-Z
High-Z
Deselected
Standby
X
1)
L
X
1)
X
1)
X
1)
X
1)
High-Z
High-Z
Deselected
Standby
X
1)
X
1)
X
1)
X
1)
H
H
High-Z
High-Z
Deselected
Standby
L
H
H
H
L
X
1)
High-Z
High-Z
Output Disabled
Active
L
H
H
H
X
1)
L
High-Z
High-Z
Output Disabled
Active
L
H
L
H
L
H
Dout
High-Z
Lower Byte Read
Active
L
H
L
H
H
L
High-Z
Dout
Upper Byte Read
Active
L
H
L
H
L
L
Dout
Dout
Word Read
Active
L
H
X
1)
L
L
H
Din
High-Z
Lower Byte Write
Active
L
H
X
1)
L
H
L
High-Z
Din
Upper Byte Write
Active
L
H
X
1)
L
L
L
Din
Din
Word Write
Active
Revision 1.0
April 2005
K1S6416BCC
- 5 -
UtRAM
DC AND OPERATING CHARACTERISTICS
1. Standby mode is supposed to be set up after at least one active operation.after power up.
I
SB1
is measured after 60ms from the time when standby mode is set up.
Item
Symbol
Test Conditions
Min
Typ
Max
Unit
Input leakage current
I
LI
V
IN
=Vss to V
CCQ
-1
-
1
A
Output leakage current
I
LO
CS
1
=V
IH
or CS
2
=V
IL
or OE=V
IH
or WE=V
IL
or LB=UB=V
IH
,
V
IO
=Vss to V
CCQ
-1
-
1
A
Average operating current
I
CC2
Cycle time=t
RC
+3t
PC
, I
IO
=0mA, 100% duty, CS
1
=V
IL,
CS
2
=
V
IH
, LB=V
IL
or/and UB=V
IL
, V
IN
=V
IH
or V
IL
-
-
40
mA
Output low voltage
V
OL
I
OL
=0.1mA
-
-
0.2
V
Output high voltage
V
OH
I
OH
=-0.1mA
1.4
-
-
V
Standby Current(CMOS)
I
SB11)
Other inputs=0~V
CCQ
1) CS
1
V
CCQ
-0.2V
,
CS
2
V
CCQ
-
0.2V(CS
1
controlled) or
2) 0V
CS
2
0.2V(CS
2
controlled)
< 40
C
-
-
120
A
< 85
C
-
-
180
A
RECOMMENDED DC OPERATING CONDITIONS
1)
1. T
A
=-40 to 85
C, otherwise specified.
2. Overshoot: V
CCQ
+1.0V in case of pulse width
20ns.
3. Undershoot: -1.0V in case of pulse width
20ns.
4. Overshoot and undershoot are sampled, not 100% tested.
Item
Symbol
Min
Typ
Max
Unit
Supply voltage
Vcc
1.7
1.85
2.0
V
Ground
Vss
0
0
0
V
Input high voltage
V
IH
0.8 x V
CCQ
-
V
CCQ
+0.2
2)
V
Input low voltage
V
IL
-0.2
3)
-
0.4
V
CAPACITANCE
1)
(f=1MHz, T
A
=25
C)
1. Capacitance is sampled, not 100% tested.
Item
Symbol
Test Condition
Min
Max
Unit
Input capacitance
C
IN
V
IN
=0V
-
8
pF
Input/Output capacitance
C
IO
V
IO
=0V
-
10
pF
PRODUCT LIST
Industrial Temperature Product(-40~85
C)
Part Name
Function
K1S6416BCC
70ns, 1.85V
Revision 1.0
April 2005
K1S6416BCC
- 6 -
UtRAM
AC OPERATING CONDITIONS
TEST CONDITIONS
(Test Load and Test Input/Output Reference)
Input pulse level: 0.2 to V
CCQ
-0.2V
Input rising and falling time: 3ns
Input and output reference voltage: 0.5 x V
CCQ
Output load (See right): C
L
=30pF
AC CHARACTERISTICS
(Vcc=V
CCQ
=1.7~2.0V, T
A
=-40 to 85
C)
1. t
WP
(min)=70ns for continuous write operation over 50 times.
Parameter List
Symbol
Speed Bins
Units
70ns
Min
Max
Common CS High Pulse Width
t
CSHP
10
-
ns
Read
Address Access Time
t
AA
-
70
ns
Chip Select to Output
t
CO
-
70
ns
Output Enable to Valid Output
t
OE
-
35
ns
UB, LB Access Time
t
BA
-
70
ns
Chip Select to Low-Z Output
t
LZ
10
-
ns
UB, LB Enable to Low-Z Output
t
BLZ
10
-
ns
Output Enable to Low-Z Output
t
OLZ
5
-
ns
Chip Disable to High-Z Output
t
HZ
0
25
ns
UB, LB Disable to High-Z Output
t
BHZ
0
25
ns
Output Disable to High-Z Output
t
OHZ
0
25
ns
Output Hold from Address Change
t
OH
3
-
ns
Page Cycle
t
PC
25
-
ns
Page Access Time
t
PA
-
20
ns
Write
Write Cycle Time
t
WC
70
-
ns
Chip Select to End of Write
t
CW
60
-
ns
Address Set-up Time
t
AS
0
-
ns
Address Valid to End of Write
t
AW
60
-
ns
UB, LB Valid to End of Write
t
BW
60
-
ns
Write Pulse Width
t
WP
55
1)
-
ns
WE High Pulse Width
t
WHP
5
-
ns
Write Recovery Time
t
WR
0
-
ns
Write to Output High-Z
t
WHZ
0
25
ns
Data to Write Time Overlap
t
DW
30
-
ns
Data Hold from Write Time
t
DH
0
-
ns
End Write to Output Low-Z
t
OW
5
-
ns
Vt=0.5 x V
CCQ
50
Dout
30pF
Z0=50
AC Output Load Circuit
Revision 1.0
April 2005
K1S6416BCC
- 7 -
UtRAM
Address
Data Out
Previous Data Valid
Data Valid
TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1)
(Address Controlled
,
CS1=OE=V
IL
, CS2=WE=V
IH
, UB or/and LB=V
IL
)
TIMING WAVEFORM OF READ CYCLE(2)
(WE=V
IH
)
t
AA
t
RC
t
OH
(READ CYCLE)
1.
t
HZ
and
t
OHZ
are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage
levels.
2. At any given temperature and voltage condition,
t
HZ
(Max.) is less than
t
LZ
(Min.) both for a given device and from device to device
interconnection.
3. t
OE
(max) is met only when OE becomes enabled after t
AA
(max).
4. If invalid address signals shorter than min. t
RC
are continuously repeated for over 4us, the device needs a normal read timing(t
RC
) or
needs to sustain standby state for min. t
RC
at least once in every 4us.
TIMING WAVEFORM OF PAGE CYCLE(READ ONLY)
Data
Valid
Data
Valid
Data
Valid
Data
Valid
Valid
Address
Valid
Address
Valid
Address
Valid
Address
Valid
Address
t
PC
t
PA
High Z
A21~A2
A1~A0
DQ15~DQ0
OE
t
OE
t
CO
t
AA
CS
1
CS
2
t
OHZ
t
HZ
Data Valid
High-Z
t
RC
t
OH
t
AA
t
BA
t
OE
t
OLZ
t
BLZ
t
LZ
t
OHZ
t
BHZ
t
CHZ
t
CO
Address
CS1
UB, LB
OE
Data out
t
CSHP
CS2
Revision 1.0
April 2005
K1S6416BCC
- 8 -
UtRAM
TIMING WAVEFORM OF WRITE CYCLE(2)
(CS
1
Controlled)
Address
Data Valid
UB, LB
WE
Data in
Data out
High-Z
t
WC
t
CW
t
AW
t
BW
t
WP
t
DH
t
DW
t
WR
t
AS
CS
1
CS
2
TIMING WAVEFORM OF WRITE CYCLE(1)
(WE Controlled)
Address
Data Valid
UB, LB
WE
Data in
t
WC
t
CW
t
BW
t
WP
t
DH
t
DW
t
WR
t
AW
t
AS
CS1
Data out
t
WC
t
AS
t
WR
Data Valid
t
DH
t
DW
t
WHP
t
WP
t
CW
t
AW
t
BW
t
CSHP
Data Undefined
t
WHZ
Data Undefined
t
OW
t
WHZ
t
OW
Data Undefined
CS2
Revision 1.0
April 2005
K1S6416BCC
- 9 -
UtRAM
Address
Data Valid
UB, LB
WE
Data in
Data out
High-Z
TIMING WAVEFORM OF WRITE CYCLE(4)
(UB, LB Controlled)
NOTES
(WRITE CYCLE)
1. A wri
t
e occurs during the overlap(t
WP
) of low CS
1
and low WE. A write begins when CS
1
goes low and WE goes low with asserting
UB or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest tran-
sition when CS
1
goes high and WE goes high. The
t
WP
is measured from the beginning of write to the end of write.
2.
t
CW
is measured from the CS
1
going low to the end of write.
3. t
AS
is measured from the address valid to the beginning of write.
4.
t
WR
is measured from the end of write to the address change.
t
WR
is applied in case a write ends with CS
1
or WE going high.
t
WC
t
CW
t
BW
t
WP
t
DH
t
DW
t
WR
t
AW
t
AS
CS
1
CS
2
TIMING WAVEFORM OF WRITE CYCLE(3)
(CS
2
Controlled)
Address
Data Valid
UB, LB
WE
Data in
Data out
High-Z
t
WC
t
CW
t
AW
t
BW
t
WP(1)
t
DH
t
DW
t
WR
t
AS
CS
1
CS
2
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