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K3N3V(U)3000D-D(G)C
CMOS MASK ROM
Pin Name
Pin Function
A
0
- A
18
Address Inputs
Q
0
- Q
7
Data Outputs
CE
Chip Enable
OE
Output Enable
V
CC
Power
V
SS
Ground
N.C
No Connection
4M-Bit (512Kx8) CMOS MASK ROM
The K3N3V(U)3000D-D(G)C is a fully static mask programma-
ble ROM organized 524,288 x 8 bit. It is fabricated using silicon
gate CMOS process technology.
This device operates with 3.0V or 3.3V power supply, and all
inputs and outputs are TTL compatible.
Because of its asynchronous operation, it requires no external
clock assuring extremely easy operation.
It is suitable for use in program memory of microprocessor, and
data memory, character generator.
The K3N3V(U)3000D-DC is packaged in a 32-DIP and the
K3N3V(U)3000D-GC in a 32-SOP.
GENERAL DESCRIPTION
FEATURES
524,288 x 8 bit organization
Fast access time
3.3V Operation : 100ns(Max.)
3.0V Operation : 120ns(Max.)
Supply voltage : single +3.0V/ single +3.3V
Current consumption
Operating : 25mA(Max.)
Standby : 30
A(Max.)
Fully static operation
All inputs and outputs TTL compatible
Three state outputs
Package
-. K3N3V(U)3000D-DC : 32-DIP-600
-. K3N3V(U)3000D-GC : 32-SOP-525
A
18
X
AND
DECODER
BUFFERS
A
0
Y
AND
DECODER
BUFFERS
MEMORY CELL
SENSE AMP.
CONTROL
LOGIC
MATRIX
(524,288x8)
BUFFERS
CE
OE
.
.
.
.
.
.
.
.
Q
0
Q
7
. . .
PIN CONFIGURATION
N.C
A
16
A
15
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
CE
OE
Q
0
Q
1
Q
4
Q
5
Q
6
Q
7
A
9
A
10
A
11
DIP
K3N3V(U)3000D-D(G)C
FUNCTIONAL BLOCK DIAGRAM
1
2
3
4
5
6
7
8
32
31
9
10
30
29
11
12
28
27
13
14
26
25
15
16
24
23
21
21
20
19
18
17
Q
2
V
SS
V
CC
A
18
A
17
A
14
A
13
A
8
Q
3
&
SOP
A
0
K3N3V(U)3000D-D(G)C
CMOS MASK ROM
ABSOLUTE MAXIMUM RATINGS
NOTE : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to the
conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.
Item
Symbol
Rating
Unit
Voltage on Any Pin Relative to V
SS
V
IN
-0.3 to +4.5
V
Temperature Under Bias
T
BIAS
-10 to +85
C
Storage Temperature
T
STG
-55 to +150
C
RECOMMENDED OPERATING CONDITIONS
(Voltage reference to V
SS
, T
A
=0 to 70
C)
Item
Symbol
Min
Typ
Max
Unit
Supply Voltage
V
CC
2.7/3.0
3.0/3.3
3.3/3.6
V
Supply Voltage
V
SS
0
0
0
V
MODE SELECTION
CE
OE
Mode
Data
Power
H
X
Standby
High-Z
Standby
L
H
Operating
High-Z
Active
L
Operating
Dout
Active
CAPACITANCE
(T
A
=25
C, f=1.0MHz)
NOTE : Capacitance is periodically sampled and not 100% tested.
Item
Symbol
Test Conditions
Min
Max
Unit
Output Capacitance
C
OUT
V
OUT
=0V
-
10
pF
Input Capacitance
C
IN
V
IN
=0V
-
10
pF
DC CHARACTERISTICS
NOTE : Minimum DC Voltage(V
IL
) is -0.3V an input pins. During transitions, this level may undershoot to -2.0V for periods <20ns.
Maximum DC voltage on input pins(V
IH
) is V
CC
+0.3V which, during transitions, may overshoot to V
CC
+2.0V for periods <20ns.
Parameter
Symbol
Test Conditions
Min
Max
Unit
Operating Current
I
CC
Cycle=5MHz, all outputs open, CE=OE=V
IL
,
V
IN
=0.45V to 2.4V (AC Test Condition)
V
CC
=3.3
0.3V
-
25
mA
V
CC
=3.0
0.3V
-
20
mA
Standby Current(TTL)
I
SB1
CE=V
IH
, all outputs open
-
500
A
Standby Current(CMOS)
I
SB2
CE=V
CC
, all outputs open
-
30
A
Input Leakage Current
I
LI
V
IN
=0 to V
CC
-
10
A
Output Leakage Current
I
LO
V
OUT
=0 to V
CC
-
10
A
Input High Voltage, All Inputs
V
IH
2.0
V
CC
+0.3
V
Input Low Voltage, All Inputs
V
IL
-0.3
0.6
V
Output High Voltage Level
V
OH
I
OH
=-400
A
2.4
-
V
Output Low Voltage Level
V
OL
I
OL
=2.1mA
-
0.4
V
K3N3V(U)3000D-D(G)C
CMOS MASK ROM
TEST CONDITIONS
Item
Value
Input Pulse Levels
0.45V to 2.4V
Input Rise and Fall Times
10ns
Input and Output timing Levels
1.5V
Output Loads
1 TTL Gate and C
L
=100pF
AC CHARACTERISTICS
(T
A
=0
C to+70
C, V
CC
=3.3V/3.0V
0.3V, unless otherwise noted.)
READ CYCLE
Item
Symbol
V
CC
=3.3V
0.3V
V
CC
=3.0V
0.3V
Unit
Min
Max
Min
Max
Read Cycle Time
t
RC
100
120
ns
Chip Enable Access Time
t
ACE
100
120
ns
Address Access Time
t
AA
100
120
ns
Output Enable Access Time
t
OE
50
60
ns
Output or Chip Disable to
Output High-Z
t
DF
20
20
ns
Output Hold from Address Change
t
OH
0
0
ns
TIMING DIAGRAM
READ
ADD
CE
OE
D
OUT
ADD1
ADD2
VALID DATA
VALID DATA
t
OH
t
DF(Note)
t
RC
t
ACE
t
OE
t
AA
NOTE : t
DF
is defined as the time at which the outputs achieve the open circuit condition and is not referenced to V
OH
or V
OL
level.