K3N4C(V,U)1000E-C/W
MASK ROM DIE
Revision 0.0
September 2002
1
FEATURES
Single 5.0V/3.3V/3.0V power supply
Fast Access Time : 100ns (min) for 5.0V/ 3.3V
120ns (min) for 3.0V
x16 or x8 configurable with BHE-pin
8M-Bit(1Mx8/ 512Kx16) CMOS Mask ROM
GENERAL PHYSICAL SPECIFICATIONS
Backside die surface of polished bare silicon
Typical Die Thickness = 320um
Typical top-level metalization :
- 99.3% AI + 0.2% Si + 0.5% Cu
- 6K Angstroms thickness
Topside Passivation :
- 1.5K Angstroms PEOX
- 3K Angstroms SiN
- 10K Angstroms Polymide
Typical Pad Size : 100um x 100um
Die Size : 3640um x 3640um including scribe line
DIE OUTLINE (Top View)
2
1
including 140um x 140um scribe line
3
4
6
9
10
11
12
14 15
17
16
18
19 20 21 22 23
47 46 45 44 43
42
41
40
37
36
35
39
38
33
34
32
31
30
29
27
26
25
24
28
49 48
51 50
Y
X
(0,0)
5
7
8
13
52
57
53
54
55
56
58
3640um x 3640um
K3N4C(V,U)1000E-C/W
A bare die is tested for only DC parameters and functional items. Please refer to the packaged product data sheet for functional and
parametric specifications. For bare die, these specifications are provided for reference only and SAMSUNG makes no guarantees or
warranties on bare die.
Wafer probe consists of various functional and parametric tests of each die. Test patterns, timing, voltage margins, limits, and test
sequence are determined by individual product yields and reliability data.
SAMSUNG retains a wafer map of each wafer as part of the probe records along with a lot summary of wafer yields for each lot
probed. SAMSUNG reserves the right to change the probe program at any time to improve the reliability, packaged device yield, or
performance of the product.
The 8Mb Mask ROM E-die has total 58pads. Refer to the bond pad location and identification table for a complete list of bond pads
and X, Y coordinates. SAMSUNG recommends using a bond wire on each Vcc and Vss bond pad for improved noise immunity.
SAMSUNG recommends the die should be stored in a controlled environment with filtered nitrogen. The carrier must be opened at
ESD safe environment at inspection and assembly.
FUNCTIONAL SPECIFICATIONS
STANDARD PROBE TESTING
BONDING INSTRUCTIONS
STORAGE AND HANDLING
K3N4C(V,U)1000E-C/W
MASK ROM DIE
Revision 0.0
September 2002
2
PAD#
FUNCTION
X
Y
1
A3
0.00
0.00
2
A2
0.00
-165.00
3
A1
0.00
-330.00
4
A0
0.00
-495.00
5
/CE
0.00
-645.00
6
DNU
0.00
-1099.10
7
DNU
0.00
-1249.10
8
VSS
-74.00
-1538.10
9
VSS
66.00
-1773.10
10
/OE
0.00
-2048.55
11
Q0
-74.00
-2307.10
12
Q8
-74.00
-2571.10
13
Q1
-74.00
-2863.90
14
Q9
209.25
-2912.50
15
Q2
426.50
-2912.50
16
Q10
643.75
-2912.50
17
Q3
861.00
-2912.50
18
Q11
1078.25
-2912.50
19
DNU
1406.00
-2912.50
20
DNU
1556.00
-2912.50
21
VCC
1706.00
-2912.50
22
VCC
1856.00
-2912.50
23
Q4
2070.50
-2912.50
24
Q12
2287.75
-2912.50
25
Q5
2505.00
-2912.50
26
Q13
2722.25
-2912.50
27
Q6
2939.50
-2912.50
28
Q14
3186.00
-2863.90
BOND PAD LOCATION AND IDENTIFICATION TABLE
PAD#
FUNCTION
X
Y
29
Q 7
3186.00
-2571.10
30
Q15/A-1
3186.00
-2307.10
31
DNU
3112.00
-2085.70
32
DNU
3112.00
-1920.70
33
VSS
3186.00
-1749.65
34
VSS
3046.00
-1514.65
35
DNU
3114.25
-1218.16
36
DNU
3112.00
-1000.10
37
DNU
3112.00
-844.70
38
BHE
3112.00
-645.00
39
A16
3112.00
-495.00
40
A15
3112.00
-330.00
41
A14
3112.00
-165.00
42
A13
3112.00
0.0000
43
A12
3031.58
206.00
44
A11
2866.58
206.00
45
A10
2701.58
206.00
46
A9
2536.58
206.00
47
A8
2731.58
206.00
48
DNU
2208.88
206.00
49
DNU
2058.88
206.00
50
DNU
1908.88
206.00
51
DNU
1758.88
206.00
52
T(Tie-Bar)
1568.88
206.00
53
A18
934.48
206.00
54
A17
769.48
206.00
55
A7
604.48
206.00
56
A6
439.48
206.00
57
A5
274.48
206.00
58
A4
109.48
206.00
1. DNU stands for Do Not use
2. Referenced to the center of each pad from center of Bond Pad #1
3. All units are in um
4. T means bonding to Tie-Bar of leadframe
PACKING
Tray Packing for Chip :
A 2-inch square waffle style carrier for die with separate compartments for each die. Each tray has a cavity size selected for the
device that allows for easy loading and unloading and prevents rotation. The tray itself is made of conductive material to reduce the
danger of damage to the die from electrostatic discharge.
The chip carriers will be labeled with the following information :
- SAMSUNG wafer lot number, SAMSUNG part number, Quantity
Jar Packing for Wafer :
Jar Packing is made by Samsung Electronics and used by
many customers that we deliver the requested die as wafer.
The pack consists of clean paper to wrap the wafer,
high cushioned sponge between wafer and hardly fragile
plastic box with sponge. Each pack has typically 25 wafers
and then several packs are put into larger box depending
on amounts of wafers.
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