K3N6V(U)1000D-YC(E)/K3N6S1000D-YC(E)
CMOS MASK ROM
32M-Bit (4Mx8 /2Mx16) CMOS MASK ROM
The K3N6V(U)1000D-YC(E) and K3N6S1000D-YC(E) are fully
static mask programmable ROM fabricated using silicon gate
CMOS process technology, and is organized either as
4,194,304 x8 bit(byte mode) or as 2,097,152x16 bit(word
mode) depending on BHE voltage level.(See mode selection
table)
This device operates with low power supply, and all inputs and
outputs are TTL compatible.
Because of its asynchronous operation, it requires no external
clock assuring extremely easy operation.
It is suitable for use in program memory of microprocessor, and
data memory, character generator.
The K3N6V(U)1000D-YC(E) and K3N6S1000D-YC(E) are
packaged in a 48-TSOP1.
GENERAL DESCRIPTION
FEATURES
Switchable organization
4,194,304x8(byte mode)
2,097,152x16(word mode)
Fast access time
Random Access Time
3.3V/3.0V Operation : 100ns(Max.)
2.5V Operation : 150ns(Max.)
Supply voltage
K3N6V(U)1000D-YC(E) : single +3.0V/ single +3.3V
K3N6S1000D-YC(E) : single +2.5V
Current consumption
Operating : 40mA(Max.)
Standby : 30
A(Max.)
Fully static operation
All inputs and outputs TTL compatible
Three state outputs
Package
-. K3N6V(U)1000D-YC(E)/K3N6S1000D-YC(E)
: 48-TSOP1-1218
A
20
X
AND
DECODER
BUFFERS
A
0
Y
AND
DECODER
BUFFERS
MEMORY CELL
SENSE AMP.
CONTROL
LOGIC
MATRIX
(2,097,152x16/
4,194,304x8)
DATA OUT
BUFFERS
A
-1
CE
OE
BHE
.
.
.
.
.
.
.
.
Q
0
/Q
8
Q
7
/Q
15
. . .
FUNCTIONAL BLOCK DIAGRAM
Pin Name
Pin Function
A
0
- A
20
Address Inputs
Q
0
- Q
14
Data Outputs
Q
15
/A
-1
Output 15(Word mode)/
LSB Address(Byte mode)
BHE
Word/Byte selection
CE
Chip Enable
OE
Output Enable
V
CC
Power
V
SS
Ground
K3N6V(U)1000D-YC(E)/K3N6S1000D-YC(E)
CMOS MASK ROM
PIN CONFIGURATION
Product
Operating
Temp Range
V
CC
Range
(Typical)
Speed
(ns)
K3N6V(U)1000D-YC
0
C ~ 70
C
3.3V/3.0V
100
K3N6S1000D-YC
2.5V
150
K3N6V(U)1000D-YE
-20
C ~ 85
C
3.3V/3.0V
100
K3N6S1000D-YE
2.5V
150
ABSOLUTE MAXIMUM RATINGS
NOTE : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to the
conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.
Item
Symbol
Rating
Unit
Remark
Voltage on Any Pin Relative to
V
IN
-0.3 to +4.5
V
-
Temperature Under Bias
T
BIAS
-10 to +85
C
-
Storage Temperature
T
STG
-55 to +150
C
-
Operating Temperature
T
A
0 to +70
C
K3N6V(U)1000D-YC
K3N6S1000D-YC
-20 to +85
C
K3N6V(U)1000D-YE
K3N6S1000D-YE
PRODUCT INFORMATION
K3N6V(U)1000D-YC(E)
K3N6S1000D-YC(E)
26
25
48
47
46
45
44
43
42
41
39
38
36
40
37
35
34
33
32
31
30
29
28
27
23
24
1
2
3
4
5
6
7
8
10
11
13
9
12
14
15
16
17
18
19
20
21
22
BHE
A
16
A
15
A
14
A
13
A
12
A
11
A
9
A
8
A
10
V
SS
A
20
A
18
A
17
A
7
A
6
A
5
A
4
A
3
A
1
A
0
CE
A
2
A
19
TSOP I
Q
4
Q
0
Q
8
Q
1
Q
3
Q
9
Q
2
Q
10
Q
15/
A-
1
Q
7
Q
14
Q
6
Q
13
Q
5
Q
12
Q
11
V
SS
V
SS
V
SS
V
CC
V
CC
V
SS
V
SS
OE
K3N6V(U)1000D-YC(E)/K3N6S1000D-YC(E)
CMOS MASK ROM
RECOMMENDED OPERATING CONDITIONS
(Voltage reference to V
SS
)
Item
Symbol
Min
Typ
Max
Unit
Supply Voltage
V
CC
2.7/3.0
3.0/3.3
3.3/3.6
V
2.3
2.5
2.7
V
Supply Voltage
V
SS
0
0
0
V
MODE SELECTION
CE
OE
BHE
Q
15
/A
-1
Mode
Data
Power
H
X
X
X
Standby
High-Z
Standby
L
H
X
X
Operating
High-Z
Active
L
L
H
Output
Operating
Q
0
~Q
15
: Dout
Active
L
Input
Operating
Q
0
~Q
7
: Dout
Q
8
~Q
14
: Hi-Z
Active
CAPACITANCE
(T
A
=25
C, f=1.0MHz)
NOTE : Capacitance is periodically sampled and not 100% tested.
Item
Symbol
Test Conditions
Min
Max
Unit
Output Capacitance
C
OUT
V
OUT
=0V
-
12
pF
Input Capacitance
C
IN
V
IN
=0V
-
12
pF
DC CHARACTERISTICS
NOTE : Minimum DC Voltage(V
IL
) is -0.3V an input pins. During transitions, this level may undershoot to -2.0V for periods <20ns.
Maximum DC voltage on input pins(V
IH
) is V
CC
+0.3V which, during transitions, may overshoot to V
CC
+2.0V for periods <20ns.
Parameter
Symbol
Test Conditions
Min
Max
Unit
Operating Current
I
CC
CE=OE=V
IL
,
all outputs open
V
CC
=3.3V
0.3V
-
40
mA
V
CC
=3.0V
0.3V
-
35
mA
V
CC
=2.5V
0.2V
-
30
mA
Standby Current(TTL)
I
SB1
K3N6V(U)1000D-YC(E)
CE=V
IH
, all outputs open
-
500
A
K3N6S1000D-YC(E)
-
100
A
Standby Current(CMOS)
I
SB2
K3N6V(U)1000D-YC(E)
CE=V
CC
, all outputs open
-
30
A
K3N6S1000D-YC(E)
-
5
A
Input Leakage Current
I
LI
V
IN
=0 to V
CC
-
10
A
Output Leakage Current
I
LO
V
OUT
=0 to V
CC
-
10
A
Input High Voltage, All Inputs
V
IH
2.0
V
CC
+0.3
V
Input Low Voltage, All Inputs
V
IL
K3N6V(U)1000D-YC(E)
-0.3
0.6
V
K3N6S1000D-YC(E)
-0.3
0.4
V
Output High Voltage Level
V
OH
K3N6V(U)1000D-YC(E) I
OH
=-400
A
2.4
-
V
K3N6S1000D-YC(E)
I
OH
=-400
A
2.0
-
V
Output Low Voltage Level
V
OL
I
OL
=2.1mA
-
0.4
V
K3N6V(U)1000D-YC(E)/K3N6S1000D-YC(E)
CMOS MASK ROM
TEST CONDITIONS
Item
Value
Input Pulse Levels
0.45V to 2.4V(at V
CC
=3.3V/3.0V)
0.4V to 2.2V (at V
CC
=2.5V)
Input Rise and Fall Times
10ns
Input and Output timing Levels
1.5V (at V
CC
=3.3V/3.0V)
1.1V (at V
CC
=2.5V)
Output Loads
1 TTL Gate and C
L
=100pF
AC CHARACTERISTICS
(V
CC
=3.3V/3.0V
0.3V, V
CC
=2.5V
0.2V, unless otherwise noted.)
READ CYCLE
Item
Symbol
V
CC
=3.3V/3.0V
0.3V
V
CC
=2.5V
0.2V
Unit
Min
Max
Min
Max
Read Cycle Time
t
RC
100
150
ns
Chip Enable Access Time
t
ACE
100
150
ns
Address Access Time
t
AA
100
150
ns
Output Enable Access Time
t
OE
50
70
ns
Output or Chip Disable to
Output High-Z
t
DF
20
30
ns
Output Hold from Address Change
t
OH
0
0
ns
TIMING DIAGRAM
READ
ADD
CE
OE
D
OUT
A
0
~A
20
A
-1(*1)
D
0
~D
7
D
8
~D
15(*2)
ADD1
ADD2
VALID DATA
VALID DATA
t
OH
t
DF(*3)
t
RC
t
ACE
t
OE
t
AA
NOTES :
*1. Byte Mode only. A
-1
is Least Significant Bit Address.(BHE = V
IL
)
*2. Word Mode only.(BHE = V
IH
)
*3. t
DF
is defined as the time at which the outputs achieve the open circuit condition and is not referenced to V
OH
or V
OL
level.
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