K3N7V(U)4000C-DC
CMOS MASK ROM
Pin Name
Pin Function
A
0
- A
21
Address Inputs
Q
0
- Q
15
Data Outputs
OE
Output Enable
V
CC
Power
V
SS
Ground
64M-Bit (4Mx16) CMOS MASK ROM
The K3N7V(U)4000C-DC is a fully static mask programmable
ROM organized 4,194,304x16 bit. It is fabricated using silicon-
gate CMOS process technology.
This device operates with a low power supply, and all inputs
and outputs are TTL compatible.
Because of its asynchronous operation, it requires no external
clock assuring extremely easy operation.
It is suitable for use in program memory of microprocessor, and
data memory, character generator.
The K3N7V(U)4000C-DC is packaged in a 42-DIP.
GENERAL DESCRIPTION
FEATURES
Switchable organization
4,194,304 x 16(word mode)
Fast access time
3.3V Operation : 100ns(Max.)@C
L
=50pF,
120ns(Max.)@C
L
=100pF
3.0V Operation : 120ns(Max.)@C
L
=100pF
Supply voltage : single +3.3V/ single +3.0V
Current consumption
Operating : 40mA(Max.)
Fully static operation
All inputs and outputs TTL compatible
Three state outputs
Package
-. K3N7V(U)4000C-DC: 42-DIP-600
A
21
X
AND
DECODER
BUFFERS
A
0
Y
AND
DECODER
BUFFERS
MEMORY CELL
SENSE AMP.
CONTROL
LOGIC
MATRIX
(4,194,304x16)
BUFFERS
OE
.
.
.
.
.
.
.
.
Q
0
Q
15
. . .
PIN CONFIGURATION
FUNCTIONAL BLOCK DIAGRAM
A
18
A
17
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
A
21
V
SS
OE
Q
0
Q
8
Q
1
Q
9
Q
4
Q
12
Q
5
Q
13
Q
6
V
SS
Q
14
Q
7
Q
15
DIP
K3N7V(U)4000C-DC
1
2
3
4
42
41
5
6
40
39
7
8
38
37
9
10
36
35
11
12
34
33
13
14
32
31
15
16
30
29
17
18
27
28
19
20
25
24
21
23
22
Q
2
Q
10
Q
3
Q
11
A
19
A
8
A
9
A
10
A
11
A
12
A
13
A
14
A
15
A
16
A
20
V
CC
26
K3N7V(U)4000C-DC
CMOS MASK ROM
ABSOLUTE MAXIMUM RATINGS
NOTE : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to the con-
ditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.
Item
Symbol
Rating
Unit
Voltage on Any Pin Relative to V
SS
V
IN
-0.3 to +4.5
V
Temperature Under Bias
T
BIAS
-10 to +85
C
Storage Temperature
T
STG
-55 to +150
C
RECOMMENDED OPERATING CONDITIONS
(Voltage reference to V
SS
, T
A
=0 to 70
C)
Item
Symbol
Min
Typ
Max
Unit
Supply Voltage
V
CC
2.7/3.0
3.0/3.3
3.3/3.6
V
Supply Voltage
V
SS
0
0
0
V
DC CHARACTERISTICS
NOTE : Minimum DC Voltage(V
IL
) is -0.3V an input pins. During transitions, this level may undershoot to -2.0V for periods <20ns.
Maximum DC voltage on input pins(V
IH
) is V
CC
+0.3V which, during transitions, may overshoot to V
CC
+2.0V for periods <20ns.
Parameter
Symbol
Test Conditions
Min
Max
Unit
Operating Current
I
CC
Cycle=5MHz, all outputs open,
CE=OE=V
IL
,
V
IN
=0.45V to 2.4V (AC Test Condition)
Vcc=3.3V
0.3V
-
40
mA
Vcc=3.0V
0.3V
-
35
mA
Input Leakage Current
I
LI
V
IN
=0 to V
CC
-
10
A
Output Leakage Current
I
LO
V
OUT
=0 to V
CC
-
10
A
Input High Voltage, All Inputs
V
IH
2.0
V
CC
+0.3
V
Input Low Voltage, All Inputs
V
IL
-0.3
0.6
V
Output High Voltage Level
V
OH
I
OH
=-400
A
2.4
-
V
Output Low Voltage Level
V
OL
I
OL
=2.1mA
-
0.4
V
MODE SELECTION
OE
Mode
Data
Power
H
Operating
High-Z
Active
L
Operating
Q
0
~Q
15
: Dout
Active
CAPACITANCE
(T
A
=25
C, f=1.0MHz)
NOTE : Capacitance is periodically sampled and not 100% tested.
Item
Symbol
Test Conditions
Min
Max
Unit
Output Capacitance
C
OUT
V
OUT
=0V
-
12
pF
Input Capacitance
C
IN
V
IN
=0V
-
12
pF
K3N7V(U)4000C-DC
CMOS MASK ROM
TEST CONDITIONS
Item
Value
Input Pulse Levels
0.45V to 2.4V
Input Rise and Fall Times
10ns
Input and Output timing Levels
1.5V
Output Loads
1 TTL Gate and C
L
=50pF or 100pF
AC CHARACTERISTICS
(T
A
=0
C to +70
C, V
CC
=3.3V/3.0V
0.3V, unless otherwise noted.)
READ CYCLE
Item
Symbol
K3N7V4000C-DC10
(C
L
=50pF)
K3N7V4000C-DC12
(C
L
=100pF)
K3N7U4000C-DC12
(C
L
=100pF)
Unit
Min
Max
Min
Max
Min
Max
Read Cycle Time
t
RC
100
120
120
ns
Address Access Time
t
AA
100
120
120
ns
Output Enable Access Time
t
OE
50
60
60
ns
Output or Chip Disable to Output High-Z
t
DF
20
20
20
ns
Output Hold from Address Change
t
OH
0
0
0
ns
TIMING DIAGRAM
READ
ADD
OE
D
OUT
A
0
~A
21
D
0
~D
15
ADD1
ADD2
VALID DATA
VALID DATA
t
OH
t
DF(*1)
t
RC
t
OE
t
AA
NOTES :
*1. t
DF
is defined as the time at which the outputs achieve the open circuit condition and is not referenced to V
OH
or V
OL
level.
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