K3P5V(U)2000D-SC
CMOS MASK ROM
Pin Name
Pin Function
A
0
- A
1
Page Address Inputs
A
2
- A
18
Address Inputs
Q
0
- Q
30
Data Outputs
Q
31
/A
-1
Output 31(Double word mode)/
LSB Address(Word mode)
WORD
Double word/Word mode selection
CE
Chip Enable
OE
Output Enable
V
CC
Power
V
SS
Ground
N.C
No Connection
16M-Bit (1Mx16 /512Kx32) CMOS MASK ROM
The K3P5V(U)2000D-SC is a fully static mask programmable
ROM fabricated using silicon gate CMOS process technology,
and is organized either as 1,048,576 x 16 bit(word mode) or as
524,288 x 32 bit(double word mode) depending on WORD volt-
age level.(See mode selection table)
This device includes page read mode function, page read mode
allows 4 double words (or 8 words) of data to read fast in the
same page, CE and A
2
~ A
18
should not be changed.
This device operates with 3.0V or 3.3V power supply, and all
inputs and outputs are TTL compatible.
Because of its asynchronous operation, it requires no external
clock assuring extremely easy operation.
It is suitable for use in program memory of microprocessor, and
data memory, character generator.
The K3P5V(U)2000D-SC is packaged in a 70-SSOP.
GENERAL DESCRIPTION
FEATURES
Switchable organization
1,048,576 x 16(word mode)
524,288 x 32(double word mode)
Fast access time
Random Access : 100ns(Max.)
Page Access : 30ns(Max.)
4 double Words / 8 Words page access
Supply voltage : single +3.0V/ single +3.3V
Current consumption
Operating : 60mA(Max.)
Standby : 30
A(Max.)
Fully static operation
All inputs and outputs TTL compatible
Three state outputs
Package
-. K3P5V(U)2000D-SC : 70-SSOP-500
A
18
X
A
0
,A
1
AND
DECODER
BUFFERS
A
2
Y
AND
DECODER
BUFFERS
MEMORY CELL
SENSE AMP.
CONTROL
LOGIC
MATRIX
(524,288x32/
1,048,576x16)
DATA OUT
BUFFERS
A
-1
CE
OE
WORD
.
.
.
.
.
.
.
.
Q
0
/Q
16
Q
15
/Q
31
. . .
PIN CONFIGURATION
A
0
A
1
A
2
A
3
A
4
A
5
V
CC
Q
0
Q
16
Q
1
Q
17
V
SS
V
CC
Q
2
Q
18
Q
3
Q
19
Q
4
Q
20
Q
5
Q
21
V
SS
V
CC
Q
6
Q
22
Q
7
Q
23
V
SS
A
6
A
7
A
8
A
9
A
10
A
11
A
12
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
A
13
A
14
A
15
A
16
A
17
A
18
N.C
V
CC
Q
8
Q
24
Q
9
Q
25
V
CC
V
SS
Q
10
Q
26
Q
11
Q
27
Q
12
Q
28
Q
13
Q
29
V
CC
V
SS
Q
14
Q
30
Q
15
Q
31
/A
-1
V
SS
CE
OE
WORD
N.C
N.C
N.C
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
SSOP
K3P5V(U)2000D-SC
FUNCTIONAL BLOCK DIAGRAM
K3P5V(U)2000D-SC
CMOS MASK ROM
ABSOLUTE MAXIMUM RATINGS
NOTE : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to the con-
ditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.
Item
Symbol
Rating
Unit
Voltage on Any Pin Relative to V
SS
V
IN
-0.3 to +4.5
V
Temperature Under Bias
T
BIAS
-10 to +85
C
Storage Temperature
T
STG
-55 to +150
C
RECOMMENDED OPERATING CONDITIONS
(Voltage reference to V
SS
, T
A
=0 to 70
C)
Item
Symbol
Min
Typ
Max
Unit
Supply Voltage
V
CC
2.7/3.0
3.0/3.3
3.3/3.6
V
Supply Voltage
V
SS
0
0
0
V
MODE SELECTION
CE
OE
WORD
Q
31
/A
-1
Mode
Data
Power
H
X
X
X
Standby
High-Z
Standby
L
H
X
X
Operating
High-Z
Active
L
L
H
Output
Operating
Q
0
~Q
31
:Dout
Active
L
Input
Operating
Q
0
~Q
15
: Dout
Q
16
~Q
30
: Hi-Z
Active
CAPACITANCE
(T
A
=25
C, f=1.0MHz)
NOTE : Capacitance is periodically sampled and not 100% tested.
Item
Symbol
Test Conditions
Min
Max
Unit
Output Capacitance
C
OUT
V
OUT
=0V
-
12
pF
Input Capacitance
C
IN
V
IN
=0V
-
12
pF
DC CHARACTERISTICS
NOTE : Minimum DC Voltage(V
IL
) is -0.3V an input pins. During transitions, this level may undershoot to -2.0V for periods <20ns.
Maximum DC voltage on input pins(V
IH
) is V
CC
+0.3V which, during transitions, may overshoot to V
CC
+2.0V for periods <20ns.
Parameter
Symbol
Test Conditions
Min
Max
Unit
Operating Current
I
CC
CE=OE=V
IL
,
all outputs open
V
CC
=3.3V
0.3V
-
60
mA
V
CC
=3.0V
0.3V
50
mA
Standby Current(TTL)
I
SB1
CE=V
IH
, all outputs open
500
A
Standby Current(CMOS)
I
SB2
CE=V
CC
, all outputs open
30
A
Input Leakage Current
I
LI
V
IN
=0 to V
CC
-
10
A
Output Leakage Current
I
LO
V
OUT
=0 to V
CC
-
10
A
Input High Voltage, All Inputs
V
IH
2.0
V
CC
+0.3
V
Input Low Voltage, All Inputs
V
IL
-0.3
0.6
V
Output High Voltage Level
V
OH
I
OH
=-400
A
2.4
-
V
Output Low Voltage Level
V
OL
I
OL
=2.1mA
-
0.4
V
K3P5V(U)2000D-SC
CMOS MASK ROM
TEST CONDITIONS
Item
Value
Input Pulse Levels
0.45V to 2.4V
Input Rise and Fall Times
10ns
Input and Output timing Levels
1.5V
Output Loads
1 TTL Gate and C
L
=100pF
AC CHARACTERISTICS
(T
A
=0
C
to 70
C
, V
CC
=3.3V/3.0V
0.3V, unless otherwise noted.)
READ CYCLE
NOTE : Page Address is determined as below.
Double Word mode (WORD=V
IH
) : A
0
, A
1
Word mode (WORD=V
IL
) : A
-1
, A
0
, A
1
Item
Symbol
K3P5V(U)2000D-SC10
K3P5V(U)2000D-SC12
Unit
Min
Max
Min
Max
Read Cycle Time
t
RC
100
120
ns
Chip Enable Access Time
t
ACE
100
120
ns
Address Access Time
t
AA
100
120
ns
Page Address Access Time
t
PA
30
50
ns
Output Enable Access Time
t
OE
30
50
ns
Output or Chip Disable to
Output High-Z
t
DF
20
20
ns
Output Hold from Address Change
t
OH
0
0
ns
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