K3S6V2000M-TC

Synch. MROM

JEDEC standard 3.3V power supply

LVTTL compatible with multiplexed address

Switchable organization

2,097,152 x 16(word mode) /

1,048,576 x 32(double word mode)

All inputs are sampled at the rising edge of the system clock

Read Performance from memory point of view

4-1-1-1 @33MHz (RAS Latency=1, CAS Latency=3)

5-1-1-1 @50MHz (RAS Latency=1, CAS Latency=4)

7-1-1-1 @66MHz (RAS Latency=2, CAS Latency=5)

SAC

: 10ns(Targetting 9ns)

MRS cycle with address key programs

-. RAS Latency(1 & 2)

-. CAS Latency(2 ~ 6)

-. Burst Length : 4, 8

-. Burst Type : Sequential & Interleaved

DQM for data-out masking

Package :86TSOP2 - 400

GENERAL DESCRIPTION

FEATURES

1M x32 Synchronous MASKROM

ORDERING INFORMATION

Part NO.

MAX Freq.

Interface

Package

K3S6V2000M-TC15

66MHz

LVTTL

86TSOP2

K3S6V2000M-TC20

50MHz

K3S6V2000M-TC30

33MHz

The K3S6V2000M-TC is a synchronous high bandwidth mask

programmable ROM fabricated with SAMSUNG

s high perfor-

mance CMOS process technology and is organized either as

2,097,152 x16bit(word mode) or as 1,048,576 x32bit(double

word mode) depending on polarity of WORD pin.(see pin func-

tion description). Synchronous design allows precise cycle con-

trol, with the use of system clock, I/O transactions are possible

on every clock cycle. Range of operating frequencies, program-

mable burst length and programmable latencies allow the same

device to be useful for a variety of high bandwidth, high perfor-

mance memory system applications.

FUNCTIONAL BLOCK DIAGRAM

* Samsung Electronics reserves the right to

change products or specification without notice.

Timing Register

1M x 32

Column Decoder

Latency & Burst Length

Programming Register

r
e

i
s

t
e

f
f
e

l
.

B

f
f
e

LCKE

LRAS

LMR

CLK

CKE

RAS

CAS

CLK

ADD

LCAS

Output Buffer

. . .

Q16

Q15

Q31

Cell Array

DQM

K3S6V2000M-TC

Synch. MROM

PIN CONFIGURATION (TOP VIEW)

86TSOPII - 400

(0.5 mm Pin Pitch)

Q16

VssQ

Q17

Q18

Q19

MR#

DQM

VssQ

CAS#

RAS#

CS#

A12

A11

A10

WORD#

VssQ

Q20

Q21

VssQ

Q22

Q23

Vss

Q31

VssQ

Q15

Q30

Q14

Q29

VssQ

Q13

Q28

Q12

Vss

CLK

CKE

Vss

Q27

Q11

Q26

VssQ

Q10

Q25

Q24

VssQ

Vss

K3S6V2000M-TC

Synch. MROM

PIN FUNCTION DESCRIPTION

Note1. V

and V

Q is same voltage.

PIN

NAME

INPUT FUNCTION

CLK

System Clock

Active on the rising edge to sample all inputs.

Chip Select

Disables or enables device operation by masking or enabling all inputs except
CLK and CKE.

CKE

Clock Enable

Masks system clock to freeze operation from the next clock cycle. CKE should be
enabled at least one cycle prior to new command. Disables input buffers for power down
in standby mode.

~ A

Address

Row / column addresses are multiplexed on the same pins.
Row address: RA

~ RA

, column address: CA

~ CA

(x32): CA

~ CA

(x16)

RAS

Row Address Strobe

Latches row addresses on the rising edge of the CLK with RAS low.
Enables row access

CAS

Column Address Strobe

Latches column addresses on the rising edge of the CLK with CAS low.
Enables column access.

Mode Register Set

Enables mode register set with MR low. (Simultaneously CS,RAS and CAS are low)

~ Q

Data Output

Power Supply/Ground

Power and ground for the input buffers and the core logic.

Data Output Power/
Ground

Power and ground for the output buffers.

WORD

x32/x16 Mode Selection

Double word mode/word mode, depending on polarity of WORD pin.
Should be set before CAS enabling.

DQM

Data-out Masking

It works similar to OE during read operation.

N.C

No Connection

This pin is recommended to be left No Connection on the device.

K3S6V2000M-TC

Synch. MROM

ABSOLUTE MAXIMUM RATINGS

Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.

Functional operation should be restricted to recommended operating condition.

Parameter

Symbol

Min

Max

Unit

Voltage on V

Relative to Vss

, V

-0.5

4.6

Voltage on Any Pin Relative to Vss

, V

OUT

-0.5

+ 0.5

4.6

Operating Temperature

Storage Temperature

STG

-55

125

Short circuit current

Power Dissipation

DC OPERATING CONDITIONS

Recommended operating conditions(Voltage referenced to V

, T

=0 to 70

Parameter

Symbol

Min

Typ

Max

Unit

Supply Voltage

, V

3.0

3.3

3.6

Supply Voltage(Ground)

SS,

DC CHARACTERISTICS

Note : 1. V

(Max)=4.6V for pulse width

10ns acceptable, pulse width measured at 50% of pulse amplitude.

2. V

(Min)=-1.5V for pulse width

10ns acceptable, pulse width measured at 50% of pulse amplitude.

3. The condition is the same as Self Refresh Mode of SDRAM, that is, in this case CS,RAS,CAS have to be set to Low, MR has to be set to High.

Parameter

Symbol

Min

Max

Unit

Test Condition

Standby Current ( Note3)

CC3P

150

CKE

(Max), t

=Min

CC3PS

150

CKE=0, t

=Min

Active Standby Current

CC3N

(Min), t

=Min,

All Outputs Open

Burst Mode Operating Current

CC4

150

=Min, All Outputs Open

Input Leakage Current

-10

+ 0.3V

Pins not under test=0V

Output Leakage Current (Dout Disabled)

-10

(0V

OUT

Max)

Q# in High-Z

Input High Voltage, All Inputs

2.0

+ 0.3

(Note1)

Input Low Voltage, All Inputs

-0.3

0.8

(Note2)

Output High Voltage Level (Logic 1)

2.4

=-2mA

Output Low Voltage Level (Logic 0)

0.4

=2mA

K3S6V2000M-TC

Synch. MROM

AC OPERATING TEST CONDITIONS

= 0 to 70

C, V

= 3.3V

0.3V, unless otherwise noted.)

Note : If CLK transition time is longer than 1ns, timing parameters should be compensated. Add [(tr+tf)/2-1]ns for transition time longer than 1ns. Transi-

tion time is measured between V

(Max) and V

(Min).

Parameter

Value

Timing Reference Levels of Input/Output Signals

1.4V

Input Signal Levels

=2.4V/0.4V

Transition Time (Rise & Fall) of Input Signals

tr/tf=1ns/1ns

Output Load

LVTTL

3.3V

1200

870

Output

50pF

(DC)=2.4V, I

=-2mA

(DC)=0.4V, I

=2mA

Vtt=1.4V

Output

50pF

=50

(Fig. 2) AC Output Load Circuit

(Fig. 1) DC Output Load Circuit

(AC operating conditions unless otherwise noted)

Note :
1. These t

values are for BL=8. For BL=4, t

=6 clks for up to 66MHz, t

=5 clks for up to 50MHz, and t

=5 clks for up to 33MHz. RAS latency

increase means, a simultaneous t

increase in the same number of cycles.

( If RAS latency is 3 clks, t

is 12 clks for BL=8.) Refer to attached technical note for gapless operation.

2. These

VCVC

values are for BL=8. For BL=4,

VCVC

=4clks for up to 66MHz,

VCVC

=3clks for up to 50MHz, and

VCVC

=2clks for up to 33MHz. Refer to

attached technical note for gapless operation.

Parameter

Symbol

up to 66MHz

up to 50 Mhz

up to 33MHz

Unit

Notes

Min

Max

Min

Max

Min

Max

CLK Cycle Time

CLK to Valid Output Delay

SAC

Data Output Hold Time

CLK High Pulse Width

6.5

11.5

CLK Low Pulse Width

6.5

11.5

Row-active to Row-active

clks

Input Setup Time

Input Hold Time

CLK to Output in Low-Z

SLZ

CLK to Output in High-Z

SHZ

Transition Time

0.1

Valid CAS Enable to Valid CAS Enable

VCVC

clks

OPERATING AC PARAMETERS

K3S6V2000M-TC

Synch. MROM

CAPACITANCE

=25

C, f=1MHz)

Parameter

Symbol

Min

Max

Unit

Input Capacitance

Output Capacitance

OUT

FUNCTION TRUTH TABLE

(V=Valid, X=Don't Care, H=Logic High, L=Logic Low)
Abbreviations (RA: Row Address, CA: Column Address, NOP: No Operation Command, DWM: Double Word Mode, WM: Word Mode)
Notes :
1. A

~ A

: Program keys (@MRS). After power up, mode register set, can be set before issuing other input command. After the mode register set com-

mand is completed, no new commands can be issued for 3 CLK Cycles, and CS or MR state must be defined "H" within 3 CLK cycles. Refer to the
Mode Register Field Table

2. In the case CKE is low, two standby modes are possible. Those are stand-by mode in power-down.

Power Down: CKE="L" (at all the parts except the range of Row Active, Read & Data out)
Clock Suspend: CKE="L" (at the range of Row Active, Read & Data Out)

3. DQM sampled at rising edge of a CLK makes a Hi-Z state the data-out state, delayed by 2CLK cycles.
4. Precharge command on Synch.DRAM can be used for Burst Stop operation during burst read operation only.
5. Mode selection control is decided simultaneously with column access start, and according to the polarity of WORD pin, "H" state is DWM,

"L" state is WM.

Command

CKEn

-1

CKEn

RAS

CAS

DQM

Add.

WORD

Notes

Mode Register Set

Code

Row Active
Row Access& Latch

Row Access & Latch

Read

Column Access & Latch

Burst Stop

(Burst Stop on Synch.DRAM)

(Precharge on Synch.DRAM)

Power Down &
Clock Suspend

Two Standby Mode

Entry

Exit

DQM

Illegal

(Write on Synch.DRAM)

(Refresh on Synch.DRAM)

No Operation Command

Organization Control

K3S6V2000M-TC

Synch. MROM

Register Programmed with MRS

Address

Function

RAS Latency

CAS Latency

Burst Type

Burst Length

Length

Reserved

Burst Type

Type

Sequential

Interleave

CAS Latency

Length

Reserved

RAS

Type

Notes :
-. After power up, when user wants to change mode register set, user must exit from power down mode
and start mode register set before entering normal operation mode.

MODE REGISTER FIELD TABLE TO PROGRAM MODES

(3) Each address is arranged as follows

for X32 operation

for X16 operation,
when CA7 is set to Low, data belonging to 0~15th registers are output to Q0~Q15 pins, and when CA7 is set to High, data belonging
to16~31th registers are output to Q0~Q15 pins.

Address Register

AR19

AR18

AR17

...

AR8

AR7

AR6

...

AR3

AR2

AR1

AR0

Address

RA12

RA11

RA10

...

RA1

RA0

CA6

...

CA3

CA2

CA1

CA0

(1) WORD = "H" : x32 Organization

Note : Column Address MSB (at x32 organization) (X=Don't Care)

Function

Row Address

Column Address

Note

(2) WORD="L" : x16 Organization

Note : Column Address MSB (at x16 organization) (X=Don't Care)

Function

Row Address

Column Address

Note

ADDRESSING MAP

* Initial Address
- BL=4(CA0,CA1)
- BL=8(CA0,CA1,CA2)

BL=8

BL=4

MSB

LSB

K3S6V2000M-TC

Synch. MROM

BURST SEQUENCE(BURST LENGTH = 4)

Initial address

Sequential

Interleave

x32 operation (double word mode)

Column Address

D15 ~ D0 (Hexadecimal)

D31 ~ D16 (Hexadecimal)

CA6

CA5

CA4

CA3

CA2

CA1

CA0

x16 operation (word mode)

Column Address

Data Out (Hexadecimal)

Comment

CA7

CA6

CA5

CA4

CA3

CA2

CA1

CA0

D15 ~ D0

D31 ~ D16

BURST SEQUENCE(BURST LENGTH = 8)

Initial address

Sequential

Interleave

K3S6V2000M-TC

Synch. MROM

CLOCK (CLK)

The clock input is used as a reference for SMROM operation. A square wave signal(CLK) must be applied externally at cycle time
t

CC.

All operations are synchronized to the rising edge of the clock. The clock transitions must be monotonic between V

and V

During operation with CKE high, all inputs are assumed to be in valid state (low or high) for the duration of set-up and hold time
around the positive edge of the clock for proper functionality and I

specifications.

CLOCK ENABLE (CKE)

The clock enable(CKE) gates the clock into the SMROM and is asserted high during all cycles, except for power down, stand-by and
clock suspend mode. If CKE goes low synchronously with clock (set-up and hold time same as other inputs), the internal clock is sus-
pended from the next clock cycle and the state of output and burst address is frozen for as long as the CKE remains low. All other
inputs are ignored from the next clock cycle after CKE goes low. The SMROM remains in the power down mode ignoring other inputs
for as long as CKE remains low. The power down exit is synchronous as the internal clock is suspended. When CKE goes high at
least "1 CLK + t

" before the rising edge of the clock, then the SMROM becomes active from the same clock edge accepting all the

input commands.

NOP and DEVICE DESELECT

When RAS, CAS and MR are high, the SMROM performs no operation (NOP). NOP does not initiate any new operation. Device
deselect is also a NOP and is entered by asserting CS high. CS high disables the command decoder so that RAS, CAS, MR and all
the address inputs are ignored. In addition, entering a mode register set command in the middle of a normal operation, results in an
illegal state in SMROM.

POWER-UP

The following power-up sequence is recommended.

1. Apply power and start clock, Attempt to maintain MR, CKE and DQM inputs to pull them high and the other pins are NOP condition

at the inputs before or along with V

(and V

Q) supply.

2. Maintain stable power, stable clock and NOP input condition for a minimum of 20us.

3. When user wants to change the default mode register set values, perform a MODE REGISTER SET cycle to program the RAS

latency, CAS latency, burst length and burst type.

4. At the end of three clock cycles after the mode register set cycle, the device is ready for operation. When the above sequence is

used for power-up, all outputs will be in high impedance state. The high impedance of outputs is not guaranteed in any other
power-up sequence.

MODE SELECTION CONTROL

Mode selection control is decided simultaneously with column access, and according to WORD pin voltage level. High level signifies
double word mode(x32) and low level signifies word mode(x16).

ADDRESS DECODING

The address bits required to decode one of the available cell locations out of the total depth are multiplexed onto the address select
pins and latched by externally applying two commands. The first command, RAS asserted low, latches the row address into the
device. A second command, CAS asserted low, subsequently latches the column address.

DEVICE OPERATIONS

K3S6V2000M-TC

Synch. MROM

MODE REGISTER SET (MRS)

The mode register stores the data for controlling the various operating modes of SMROM. It programs the RAS latency, CAS latency,
burst length, burst type. The default value of the mode register is defined as RAS latency=2, CAS latency=5, Burst length=4,
Sequential Burst Type. When and if the user wants to change its values, the user must exit from power down mode and start mode
register set before entering normal operation mode. The mode register is reprogrammed by asserting low on CS, RAS, CAS and MR
(The SMROM should be in active mode with CKE already high prior to writing the mode register). The state of address pins A

~ A

in the same cycle as CS, RAS, CAS and MR going low is the data written in the mode register. Three clock cycles are required to
complete the program in the mode register, therefore after mode register set command is completed, no new commands can be
issued for 3 clock cycles and CS or MR must be fixed to high within 3 clock cycles. The mode register is divided into various fields
depending on functionality. The burst length field uses A

~ A

, burst type uses A

, CAS latency (read latency from column address)

uses A

~ A

RAS latency uses

(RAS to CAS delay). Refer to the table for specific codes for various burst length, burst type, CAS

latencies and RAS latencies.

LATENCY

There are latencies between the issuance of a Row active command and when data is available on the I/O buffers. The RAS to CAS
delay is defined as the RAS latency. The CAS to data out delay is the CAS latency. The CAS and RAS latencies are programmable
through the mode register. RAS latencies of 1 and 2, and CAS latencies of 2 through 6 are supported. It is understood that some
RAS and CAS latency values are reserved for future use, and may not be available in the first generation for SMROM. The followings
are the supported minimum values in the first generation. RAS latency=2, and CAS latency=5 for 66MHz operation, and RAS
latency=1, and CAS latenecy=4 for 50MHz operation, and RAS latency=1, and CAS latenecy=3 for 33MHz operation.

DQM OPERATION

The DQM is used to mask output operations when a complete burst read is not required. It works similar to OE during a read opera-
tion. The read latency is two cycles from DQM, which means DQM masking occurs two cycles later in the read cycle. DQM operation
is synchronous with the clock. The masking occurs for a complete cycle. (Also refer to the DQM timing diagram)

BURST READ

The burst read command is used to access a burst of data on consecutive clock cycles from an active row state. The burst read com-
mand is issued by asserting low CS and CAS with MR being high on the rising edge of the clock. The first output appears in CAS
latency number of clock cycles after the issuance of the burst read command. The burst length, burst sequence and latency from the
burst read command are determined by the mode register which is already programmed. Burst read can be initiated on any column
address of the active row. The output goes into high-impedance at the end of the burst, unless a new burst read is initiated to keep
the data output gapless. The burst read can be terminated by issuing another burst read.

DEVICE OPERATIONS

K3S6V2000M-TC

Synch. MROM

Internal

CLK

Internal

CLK

CKE

Internal

CLK

Note :

1. After mode register set command is completed, no new commands can be issued for 3 clock cycles, and MR or CS should be fixed "H"

within a minimum of 3 clock cycles.

BASIC FEATURE AND FUNCTION DESCRIPTIONS

1. MRS

Mode Register Set

CLK

CMD

MRS

ACT

Note 1

3CLK

2. CLOCK Suspend

Clock Suspended During Burst Read (BL=4)

Masked by CKE

Suspended Dout

CLK

CMD

CKE

Data

3. Clock Suspend Exit & power Down Exit

1) Clock Suspend Exit

CLK

CKE

CMD

2) Power Down Exit

CLK

CMD

NOP

ACT

: This command do not be activated.

K3S6V2000M-TC

Synch. MROM

Read Interrupted by Precharge Command & Burst Read Stop Cycle @Burst Length=8

*Note :
1. The burst stop command is valid at every page burst length.

The data bus goes to High-Z after the CAS latency from the burst stop command is issued.

2. The interval between read command (column address presented) and burst stop command is 1 cycle(min).

HIGH

CL=3

ADDR

CAS

RAS

CKE

CLK

DQM

Qa0 Qa1 Qa2

Qa4

Qb0 Qb1 Qb2 Qb3 Qb4 Qb5

RAa

CAa

CAb

Row Active

Precharge

Burst Stop

Read

Don't Care

Note1

CL=2

Data

Qa0 Qa1 Qa2

Qa4

Qb0 Qb1 Qb2 Qb3 Qb4 Qb5

Qa3

*Note1, 2

Note1

Note2

K3S6V2000M-TC

Synch. MROM

Power Down & Clock Suspend Cycle :

CKE

RAS

CAS

ADDR

Data

Power Down

Read

Clock Suspend

CAa

RAa

@RAS Latency = 2, CAS Latency=5, Burst Length=4

Qa1

Qa2

Qa0

Qa3

Row Active

(High)

Data Hi-Z State

CLK

(internal)

NOP

Power-down

Clock Suspend

Entry

Power-down

Exit

Clock Suspend

Exit

Note :
1. From next clock after CKE goes low, clock suspend and power down begins.

2. After power down exit, NOP should be issued and new command can be issued after 1clock.

Don't Care

*Note 2

*Note 1

K3S6V2000M-TC

Synch. MROM

Mode Register Set:

CKE

RAS

CAS

ADDR

Data

HIGH

Code

RAa

Note :
1. After the mode register set is completed, no new commands can be issued for 3CLK cycles.

2. After power up, necessarily mode register set should be completed at least one time and CS or MR must be fixed "H" within

3clock cycles, and when user wants to change mode register set, user must exit from power down mode and start mode reg-

ister set before chip enters normal operation mode.

RAS

Latency

Data Hi-Z State

MRS

Row Active

Don't Care

CAa

Qa0 Qa1 Qa2 Qa3

@RAS Latency = 2, CAS Latency=5, Burst Length=4

CLK

K3S6V2000M-TC

Synch. MROM

FUNCTION TRUTH TABLE

* : After the power up, when user wants to change MR set, user must exit from power down mode and start MR set before chip enters normal operation

mode.

Current

State

Input Signal

Next State Operation

CKE

RAS

CAS

Add.

After

Power Up*

-. Power Down

-. Row Active ; latch RA

Code

-. Mode Register Set

Row Active

-. If consecutive row access is issued within
t

RCmin.

without CAS enabling, only the final

RA is valid.

-. Begin READ ; latch CA

Code

Illegal *

-. Clock Suspend

READ

-. Row Access in Read State,
within the tRC, previous read is ignored and
new row is activated.
beyond the tRC, previous read is completed
and new read begins.

-. Consecutive Column Access,
within the t

VCVC

, only the final CA is valid

and the previous burst read is ignored.
Beyond the t

VCVC

, the previous read is

completed and new read begins.

-. NOP (After Burst Read) / Read Interrupt

Code

Illegal *

-. Clock Suspend / Power Down

Any State

-. Low Power Consumption Mode

Any State

NOP

Any State

Illegal

K3S6V2000M-TC

Synch. MROM

K3S6V2000M-TC15

Burst Length

RAS Latency

CAS Latency

tRCmin.

tVCVCmin.

Technical Notes

( unit : number of clock )

K3S6V2000M-TC20

Burst Length

RAS Latency

CAS Latency

tRCmin.

tVCVCmin.

3/ 4*

7/ 8*

( unit : number of clock )

K3S6V2000M-TC30

Note :
Above tables are not specifications values, rather actual values.
There are no gapless operations for CAS latency 6,7 and 8.
* : Minimum clocks for Gapless Operation.

Burst Length

RAS Latency

CAS Latency

tRCmin.

tVCVCmin.

2/ 4*

( unit : number of clock )

1. Frequency vs. AC Parameter Relationship Table

K3S6V2000M-TC

Synch. MROM

PRE

3. Read interrupt operation by issuing the precharge or Burst Stop Command

CLK

CMD

CLK

CMD

Note 2

Data(CL2)

Data(CL3)

Data(CL4)

*Note :
1. By " Interrupt", It is meant to stop burst read by external command before the end of burst.

By "CAS Interrupt", to stop burst read by CAS access.

2. CAS to CAS delay. (=1CLK)

2. CAS Interrupt

Read interrupted by Read (BL=4)

Note 1

CLK

CMD

ADD

CASE I ) Issued read Interrupt command during burst read operation period.

PRE

Note 2

STOP

CLK

CMD

CLK

CMD

CASE II ) Issued read Interrupt command between read command and data out.

*Note :
1. The data bus goes to High-Z after CAS Latency from the burst stop (or precharge) command.
2. Valid output data will last up to CL-1 clock cycle from PRE command.

Note 2

Note 1

Technical Notes

(Continuous)

Data(CL2)

Data(CL3)

Data(CL4)

Data(CL2)

Data(CL3)

Data(CL4)

Data(CL2)

Data(CL3)

Data(CL4)

Data(CL2)

Data(CL3)

Data(CL4)

STOP

K3S6V2000M-TC

Synch. MROM

RDa

4. Read cycle depending on t

@ RL = 2, CL = 5, BL = 4 ; 66MHz

tRC(min)=6

ACT

tCC=15ns

RDb

ACT

RDb

High-Z

CASE I )

RDb

ACT

CASE II )

CASE III )

ACT

@ RL = 1, CL = 4, BL = 4 ; 50MHz

tRC(min)=4

ACT

tCC=20ns

ACT

CASE I )

ACT

CASE II)

CASE III)

ACT

@ RL = 1, CL = 3, BL = 4 ; 33MHz

tRC(min)=3

ACT

tCC=30ns

ACT

CASE I)

ACT

CASE II)

CASE III)

ACT

: Invalid Data

CLK

CMD

CASE I )

CASE II )

CASE III )

CLK

CMD

CASE I )

CASE II )

CASE III )

CLK

CMD

CASE I )

CASE II )

CASE III )

RDa

RDb

RDa

RDb

(Gapless Operation)

K3S6V2000M-TC

Synch. MROM

5. Read cycle depending on tVCVC

@ RL = 2, CL = 5, BL = 4 ; 66MHz

tVCVC=4

ACT

CASE I)

CASE II)

CASE III)

CLK

CMD

CASE I )

CASE II )

CASE III )

@ RL = 1, CL = 4, BL = 4 ; 50MHz

tVCVC=3

ACT

CASE I)

CASE II)

CASE III)

CLK

CMD

CASE I )

CASE II )

CASE III )

@ RL = 1, CL = 3, BL = 4 ; 33MHz

tVCVC=2

ACT

CASE I)

CASE II)

CASE III)

CLK

CMD

CASE I )

CASE II )

CASE III )

RDa

RDb

RDa

RDb

RDa RDb

RDb

(Gapless Operation)

: Invalid Data

tCC=15ns

tCC=20ns

tCC=30ns

K3S6V2000M-TC

Synch. MROM

6. Read Cycle depending on t

VCVC

and t

@ RL = 1, CL = 4, BL = 4 ; 50MHz (Gapless Operation)

tVCVC=4

ACT

CLK

CMD

Read out

@ RL = 1, CL = 4, BL = 4 ; 50MHz

CLK

@ RL = 1, CL = 4, BL = 4 ; 50MHz

CLK

RDa

RDb

: Invalid Data

ACT RDc

RDd

tCC=20ns

ACT RDe

RDf

: Invalid Data

CMD

Read out

RDd

ACT RDe

RDf

ACT

CMD

Read out

RDa

RDb

ACT RDc

RDd

ACT RDe

tVCVC=4

ACT RDa

RDb ACT RDc

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: K3S6V2000M

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: K3S6V2000M