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Электронный компонент: K4C560838C

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K4C5608/1638C 256Mb Network-DRAM
REV. 0.7 Aug. 2003
- 1 -
256Mb Network-DRAM Specification
Version 0.7
K4C5608/1638C 256Mb Network-DRAM
REV. 0.7 Aug. 2003
- 2 -
Revision History
Version 0.0 (Oct. / 5 / 2001)
- First Release
Version 0.1 (Dec. / 15 / 2001)
- The product name is changed to Network-DRAM
Version 0.2 (Jan. / 21 / 2002)
-
M-version is renamed to C-version
- Specify DC operating condition values
- Added Power Up Sequence and Power Down(CL=4) Timing Diagrams
Version 0.3 (Mar. / 23 / 2002)
- The product name is changed to Network RAM
- Added Speed bin (366Mbps/pin,183MHz)
Version 0.4 (May. / 01 / 2002)
- The product name is changed to Network-DRAM
- Redefined I
DD1S
, I
DD5
in DC Characteristic
Version 0.5 (Nov. /23 / 2002)
-Updated the current spec. value
Version 0.6 (Apr. /9 / 2003)
-Changed IDD2P value from 2mA to 3mA in page 10.
-Changed capacitance of DQ/DQS
Version 0.7 (Aug.31 / 2003)
-Changed tCK max like below
Unit: pF
From
To
Min
Max
Min
Max
Capacitance(DQ/DQS)
4.0
6.0
3.0
6.0
From
To
D4
DA
D3
D4
DA
D3
8.5
12
12
7.5
7.5
7.5
K4C5608/1638C 256Mb Network-DRAM
REV. 0.7 Aug. 2003
- 3 -
General Information
Organization
D4 (400Mbps)
DA (366Mbps )
D3 (333Mbps )
256Mx8
K4C560838C-TCD4
K4C560838C-TCDA
K4C560838C-TCD3
256Mx16
K4C561638C-TCD4
K4C561638C-TCDA
K4C561638C-TCD3
T : TSOP II (400mil x 875mil)
D4 : 400bps/pin (200MHz, CL=4)
DA : 366bps /pin (183MHz, CL=4)
D3 : 333bps/pin (167MHz, CL=4)
C : (Commercial, Normal)

08 : x8
16 : x16
56 : 256M 8K/64ms
C : Network-DRAM
C : 4th Generation
K 4 C XX XX X X X - X X
Memory
DRAM
Small Classification
Density and Refresh
Temperature & Power
Package
Organization
Version
Interface (VDD & VDDQ)
1. SAMSUNG Memory : K
2. DRAM : 4
3. Small Classification
4. Density & Refresh
5. Organization
8. Version
9. Package
10. Temperature & Power
11. Speed
3 : 4 Bank
6. Bank
1 2 3 4 5 6 7 8 9 10 11
XX
8: SSTL-2(2.5V, 2.5V)
7. Interface (VDD & VDDQ)
Speed
Bank
K4C5608/1638C 256Mb Network-DRAM
REV. 0.7 Aug. 2003
- 4 -
Fully Synchronous Operation
Double Data Rate (DDR)
Data input/output are synchronized with both edges of DQS.
Differential Clock (CK and CK)inputs
CS, FN and all address input signals are sampled on the positive edge of CK.
Output data (DQs and DQS) is referenced to the crossings of CK and CK.
Fast clock cycle time of 5ns minimum Clock : 200MHz maximum
Data : 400Mbps/pin maximum
Quad independent banks operation
Fast cycle and short Iatency
Bidirectional data strobe signal
Distributed Auto-Refresh cycle in 7.8us
Self-Refresh
Power Down Mode
Variable Write Length Control
Write Latency = CAS Latency - 1
Programmable CAS Latency and Burst Length
CAS Latency = 3, 4
Burst Length = 2, 4
Organization K4C561638C-TC : 4,194,304 words x4 banks x 16
K4C560838C-TC : 8,388,608 words x4 banks x 8
Power supply voltage Vdd : 2.5 0.15V
VddQ : 2.5 0.15V
2.5V CMOS I/O comply with SSTL-2 (Strong / Normal / Weaker / Weakest)
Package 400X875mil, 66pin TSOP II, 0.65mm pin pitch (TSOP II 66-P-400-0.65)
Item
K4C560838/1638C-TC
D4 (400Mbps)
DA (366Mbps)
D3 (333Mbps)
t
CK
Clock Cycle Time (Min.)
CL=3
5.5ns
6ns
6.5ns
CL=4
5ns
5.5ns
6ns
t
RC
Random Read/Write Cycle Time (Min.)
25ns
27.5ns
30ns
t
RAC
Random Access Time (Max.)
22ns
24ns
26ns
I
DD1S
Operating Current (Single bank) (Max.)
310mA
300mA
290mA
I
DD2P
Power Down Current (Max.)
2mA
2mA
2mA
I
DD6
Self-Refresh Current(Max.)
3mA
3mA
3mA
Key Feature
K4C5608/1638C 256Mb Network-DRAM
REV. 0.7 Aug. 2003
- 5 -
Pin Names
Pin
Name
A0 to A14
Address Input
BA0, BA1
Bank Address
DQ0 to DQ7 (x8)
Data Input/Output
DQ0 to DQ15 (x16)
CS
Chip Select
FN
Function Control
PD
Power Down Control
CK, (CK)
Clock Input
DQS (X8)
Write/Read Data Strobe
UDQS/LDQS (X16)
Vdd
Power(+2.5V)
Vss
Ground
VddQ
Power (+2.5V)
(for I/O buffer)
VssQ
Ground
(for I/O buffer)
V
REF
Reference Voltage
NC1,NC2
No Connection
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
400mil Width
875mil Length
66Pin TSOP II
0.65mm
Lead Pitch
Vdd Vdd
DQ0 DQ0
VddQ VddQ
DQ1 NC
2
DQ2 DQ1
VssQ VssQ
DQ3 NC
2
DQ4 DQ2
VddQ VddQ
DQ5 NC
2
DQ6 DQ3
VssQ VssQ
DQ7 NC
2
NC
1
NC
1
VddQ VddQ
LDQS NC
2
NC
1
NC
1
Vdd Vdd
NC
1
NC
1
NC
2
NC
2
A14 A14
A13 A13
FN FN
CS CS
NC
1
NC
1
BA0 BA0
BA1 BA1
A10 A10
A0 A0
A1 A1
A2 A2
A3 A3
Vdd Vdd
Vss Vss
DQ7 DQ15
VssQ VssQ
NC
2
DQ14
DQ6 DQ13
VddQ VddQ
NC
2
DQ12
DQ5 DQ11
VssQ VssQ
NC
2
DQ10
DQ4 DQ9
VddQ VddQ
NC
2
DQ8
NC
1
NC
1
VssQ VssQ
DQS UDQS
NC
1
NC
1
VREF VREF
Vss Vss
NC
2
NC
2
CK CK
CK CK
PD PD
NC
1
NC
1
A12 A12
A11 A11
A9 A9
A8 A8
A7 A7
A6 A6
A5 A5
A4 A4
Vss Vss
K4C561638C-TC
K4C560838C-TC
Pin Assignment (Top View)