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Электронный компонент: K4C560838C-TCD3

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K4C5608/1638C 256Mb Network-DRAM
REV. 0.7 Aug. 2003
- 1 -
256Mb Network-DRAM Specification
Version 0.7
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K4C5608/1638C 256Mb Network-DRAM
REV. 0.7 Aug. 2003
- 2 -
Revision History
Version 0.0 (Oct. / 5 / 2001)
- First Release
Version 0.1 (Dec. / 15 / 2001)
- The product name is changed to Network-DRAM
Version 0.2 (Jan. / 21 / 2002)
-
M-version is renamed to C-version
- Specify DC operating condition values
- Added Power Up Sequence and Power Down(CL=4) Timing Diagrams
Version 0.3 (Mar. / 23 / 2002)
- The product name is changed to Network RAM
- Added Speed bin (366Mbps/pin,183MHz)
Version 0.4 (May. / 01 / 2002)
- The product name is changed to Network-DRAM
- Redefined I
DD1S
, I
DD5
in DC Characteristic
Version 0.5 (Nov. /23 / 2002)
-Updated the current spec. value
Version 0.6 (Apr. /9 / 2003)
-Changed IDD2P value from 2mA to 3mA in page 10.
-Changed capacitance of DQ/DQS
Version 0.7 (Aug.31 / 2003)
-Changed tCK max like below
Unit: pF
From
To
Min
Max
Min
Max
Capacitance(DQ/DQS)
4.0
6.0
3.0
6.0
From
To
D4
DA
D3
D4
DA
D3
8.5
12
12
7.5
7.5
7.5
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K4C5608/1638C 256Mb Network-DRAM
REV. 0.7 Aug. 2003
- 3 -
General Information
Organization
D4 (400Mbps)
DA (366Mbps )
D3 (333Mbps )
256Mx8
K4C560838C-TCD4
K4C560838C-TCDA
K4C560838C-TCD3
256Mx16
K4C561638C-TCD4
K4C561638C-TCDA
K4C561638C-TCD3
T : TSOP II (400mil x 875mil)
D4 : 400bps/pin (200MHz, CL=4)
DA : 366bps /pin (183MHz, CL=4)
D3 : 333bps/pin (167MHz, CL=4)
C : (Commercial, Normal)

08 : x8
16 : x16
56 : 256M 8K/64ms
C : Network-DRAM
C : 4th Generation
K 4 C XX XX X X X - X X
Memory
DRAM
Small Classification
Density and Refresh
Temperature & Power
Package
Organization
Version
Interface (VDD & VDDQ)
1. SAMSUNG Memory : K
2. DRAM : 4
3. Small Classification
4. Density & Refresh
5. Organization
8. Version
9. Package
10. Temperature & Power
11. Speed
3 : 4 Bank
6. Bank
1 2 3 4 5 6 7 8 9 10 11
XX
8: SSTL-2(2.5V, 2.5V)
7. Interface (VDD & VDDQ)
Speed
Bank
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K4C5608/1638C 256Mb Network-DRAM
REV. 0.7 Aug. 2003
- 4 -
Fully Synchronous Operation
Double Data Rate (DDR)
Data input/output are synchronized with both edges of DQS.
Differential Clock (CK and CK)inputs
CS, FN and all address input signals are sampled on the positive edge of CK.
Output data (DQs and DQS) is referenced to the crossings of CK and CK.
Fast clock cycle time of 5ns minimum Clock : 200MHz maximum
Data : 400Mbps/pin maximum
Quad independent banks operation
Fast cycle and short Iatency
Bidirectional data strobe signal
Distributed Auto-Refresh cycle in 7.8us
Self-Refresh
Power Down Mode
Variable Write Length Control
Write Latency = CAS Latency - 1
Programmable CAS Latency and Burst Length
CAS Latency = 3, 4
Burst Length = 2, 4
Organization K4C561638C-TC : 4,194,304 words x4 banks x 16
K4C560838C-TC : 8,388,608 words x4 banks x 8
Power supply voltage Vdd : 2.5 0.15V
VddQ : 2.5 0.15V
2.5V CMOS I/O comply with SSTL-2 (Strong / Normal / Weaker / Weakest)
Package 400X875mil, 66pin TSOP II, 0.65mm pin pitch (TSOP II 66-P-400-0.65)
Item
K4C560838/1638C-TC
D4 (400Mbps)
DA (366Mbps)
D3 (333Mbps)
t
CK
Clock Cycle Time (Min.)
CL=3
5.5ns
6ns
6.5ns
CL=4
5ns
5.5ns
6ns
t
RC
Random Read/Write Cycle Time (Min.)
25ns
27.5ns
30ns
t
RAC
Random Access Time (Max.)
22ns
24ns
26ns
I
DD1S
Operating Current (Single bank) (Max.)
310mA
300mA
290mA
I
DD2P
Power Down Current (Max.)
2mA
2mA
2mA
I
DD6
Self-Refresh Current(Max.)
3mA
3mA
3mA
Key Feature
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K4C5608/1638C 256Mb Network-DRAM
REV. 0.7 Aug. 2003
- 5 -
Pin Names
Pin
Name
A0 to A14
Address Input
BA0, BA1
Bank Address
DQ0 to DQ7 (x8)
Data Input/Output
DQ0 to DQ15 (x16)
CS
Chip Select
FN
Function Control
PD
Power Down Control
CK, (CK)
Clock Input
DQS (X8)
Write/Read Data Strobe
UDQS/LDQS (X16)
Vdd
Power(+2.5V)
Vss
Ground
VddQ
Power (+2.5V)
(for I/O buffer)
VssQ
Ground
(for I/O buffer)
V
REF
Reference Voltage
NC1,NC2
No Connection
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
400mil Width
875mil Length
66Pin TSOP II
0.65mm
Lead Pitch
Vdd Vdd
DQ0 DQ0
VddQ VddQ
DQ1 NC
2
DQ2 DQ1
VssQ VssQ
DQ3 NC
2
DQ4 DQ2
VddQ VddQ
DQ5 NC
2
DQ6 DQ3
VssQ VssQ
DQ7 NC
2
NC
1
NC
1
VddQ VddQ
LDQS NC
2
NC
1
NC
1
Vdd Vdd
NC
1
NC
1
NC
2
NC
2
A14 A14
A13 A13
FN FN
CS CS
NC
1
NC
1
BA0 BA0
BA1 BA1
A10 A10
A0 A0
A1 A1
A2 A2
A3 A3
Vdd Vdd
Vss Vss
DQ7 DQ15
VssQ VssQ
NC
2
DQ14
DQ6 DQ13
VddQ VddQ
NC
2
DQ12
DQ5 DQ11
VssQ VssQ
NC
2
DQ10
DQ4 DQ9
VddQ VddQ
NC
2
DQ8
NC
1
NC
1
VssQ VssQ
DQS UDQS
NC
1
NC
1
VREF VREF
Vss Vss
NC
2
NC
2
CK CK
CK CK
PD PD
NC
1
NC
1
A12 A12
A11 A11
A9 A9
A8 A8
A7 A7
A6 A6
A5 A5
A4 A4
Vss Vss
K4C561638C-TC
K4C560838C-TC
Pin Assignment (Top View)
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K4C5608/1638C 256Mb Network-DRAM
REV. 0.7 Aug. 2003
- 6 -
Package Outline Drawing (TSOP II 66-P-400-0.65)
66
34
33
1
0.65
10
.1
6
0.
1
11
.
7
6
0.
2
0.71TYP
+ 0.08
0.24 - 0.07
0.13 M
1
0.1
1.2
MA
X
0.
1
0.
05
22.62 MAX
22.22
0.1
0.1
0.5
0.1
0 ~

10
0.8
0.2
0
.
145
0.
05
5
Unit in mm
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K4C5608/1638C 256Mb Network-DRAM
REV. 0.7 Aug. 2003
- 7 -
Block Diagram
CK
CK
PD
DLL
CLOCK
BUFFER
COMMAND
DECODER
CS
FN
CONTROL
GENERATOR
SIGNAL
ADDRESS
BUFFER
MODE
REGISTER
UPPER ADDRESS
LATCH
LOWER ADDRESS
LATCH
COLUMN DECODER
ROW DECO
DER
BANK #3
BANK #2
BANK #1
BANK #0
MEMORY
CELL
ARRAY
DA
T
A
CO
NT
RO
L AND
LA
TCH
CI
RC
UI
T
BURST
COUNTER
READ
DATA
BUFFER
WRITE
DATA
BUFFER
DQ BUFFER
A0 to A14
BA0, BA1
REFRESH
COUNTER
WRITE ADDRESS
LATCH
ADDRESS
COMPARATOR
DQS
DQ0 to DQn
To Each Block
Note : The K4C560838C-TC configuration is 4 Bank of 32768X256X 8 of cell array with the DQ pins numbered DQ0-7
The K4C561638C-TC configuration is 4 BanK of 32768X128X16 of cell array with the DQ pins numbered DQ0-15.
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K4C5608/1638C 256Mb Network-DRAM
REV. 0.7 Aug. 2003
- 8 -
Absolute Maximum Ratings
Caution : Conditions outside the limits listed under "ABSOLUTE MAXIMUM RATINGS" may cause permanent damage to the device.
The device is not meant to be operated under conditions outside the limits described in the operational section of this specifi-
cation. Exposure to "ABSOLUTE MAXIMUM RATINGS" conditions for extended periods may affect device reliability.
Recommanded DC,AC Operating Conditions (Notes : 1)
(Ta = 0 to 70
C)
Symbol
Parameter
Rating
Units
Notes
Vdd
Power Supply Voltage
-0.3 to 3.3
V
VddQ
Power Supply Voltage (for I/O buffer)
-0.3 to Vdd + 0.3
V
V
IN
Input Voltage
-0.3 to Vdd + 0.3
V
V
OUT
DQ pin Voltage
-0.3 to VddQ + 0.3
V
V
REF
Input Reference Voltage
-0.3 to Vdd + 0.3
V
T
OPR
Operating Temperature
0 to 70
O
C
T
STG
Storage Temperature
-55 to 150
O
C
T
SOLDER
Soldering Temperature(10s)
260
O
C
P
D
Power Dissipation
1
W
I
OUT
Short Circuit Output Current
50
mA
Symbol
Parameter
Min
Typ
Max
Units
Notes
Vdd
Power Supply Voltage
2.35
2.5
2.65
V
VddQ
Power Supply Voltage (for I/O Buffer)
2.35
2.5
2.65
V
V
REF
Input Reference Voltage
VddQ/2*96%
VddQ/2
VddQ/2*104%
V
2
V
IH
(DC)
Input DC high Voltage
V
REF
+0.2
-
VddQ+0.2
V
5
V
IL
(DC)
Input DC Low Voltage
-0.1
-
V
REF
-0.2
V
5
V
ICK
(DC)
Differential Clock DC Input Voltage
-0.1
-
VddQ+0.1
V
10
V
ID
(DC)
Input Differential Voltage. CK and CK Inputs (DC)
0.4
-
VddQ+0.2
V
7,10
V
IH
(AC)
Input AC High Voltage
V
REF
+0.35 -
VddQ+0.2
V
3,6
V
IL
(AC)
Input AC Low Voltage
-0.1
-
V
REF
-0.35
V
4,6
V
ID
(AC)
Input Differential Voltage. CK and CK Inputs (AC)
0.7
-
VddQ+0.2
V
7,10
V
X
(AC)
Differential AC Input Cross Point Voltage
VddQ/2-0.2
-
VddQ/2+0.2
V
8,10
V
ISO
(AC)
Differential Clock AC Middle Level
VddQ/2-0.2
-
VddQ/2+0.2
V
9,10
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K4C5608/1638C 256Mb Network-DRAM
REV. 0.7 Aug. 2003
- 9 -
1. All voltages are referenced to Vss, VssQ.
2. V
REF
is expected to track variations in VddQ DC level of the transmitting device.
Peak to peak AC noise on V
REF
may not exceed 2% of V
REF
(DC).
3. Overshoot Iimit : V
IH
(max.) = VddQ + 0.9V with a pulse width <= 5ns
4. Undershoot Iimit : V
IL
(min.) = -0.9V with a pulse width <= 5ns
5. V
IH
(DC) and V
IL
(DC) are levels to maintain the current logic state.
6. V
IH
(AC) and V
IL
(AC) are levels to change to the new logic state.
7. V
ID
is magnitude of the difference between CK input level and CK input level.
8. The value of Vx(AC) is expected to equal VddQ/2 of the transmitting device.
9. V
ISO
means [V
ICK
(CK) + V
ICK
(CK)]/2
10. Refer to the figure below.
Notes
:
11. In the case of external termination, VTT(Termination Voltage) should be gone in the range of V
REF
(DC) 0.04V.
Pin Capacitance
(Vdd, VddQ = 2.5V, f = 1MHz, Ta = 25
C
)
Note : These parameters are periodically sampled and not 100% tested.
2 The NC
2
pins have additional capacitance for adjustment of the adjacent pin capacitance.
1 The NC
2
pins have Power and Ground clamp.
Symbol
Parameter
Min
Max
Units
C
IN
Input Pin Capacitance
2.5
4.0
pF
C
INC
Clock Pin (CK, CK) Capacitance
2.5
4.0
pF
C
I/O
I/O Pin (DQ, DQS) Capacitance
3.0
6.0
pF
C
NC
1
NC1 Pin Capacitance
-
1.5
pF
C
NC
2
NC2 Pin Capacitance
4.0
6.0
pF
CLK
CLK
V
SS
V
ID
(AC)
0 V Differential
V
ISO
V
SS
V
ICK
V
ISO
(min)
V
X
V
X
V
X
V
X
V
ICK
V
ICK
V
ICK
V
ISO
(max)
V
X
V
ID
(AC)
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K4C5608/1638C 256Mb Network-DRAM
REV. 0.7 Aug. 2003
- 10 -
DC Characteristics and Operating Conditions
(Vdd, VddQ = 2.5V 0.15V, Ta = 0~70
C
)
Notes : 1. These parameters depend on the cycle rate and these values are measured at a cycle rate with the minimum values of t
CK
, t
RC
and I
RC
.
2. These parameters depend on the output loading. The specified values are obtained with the output open.
3. Refer to output driver characteristics for the detail. Output Driver Strength is selected by Extended Mode Register.
Item
Symbol
Max
Units
Notes
D4(400Mbps) DA(366Mbps) D3(333Mbps)
Operating Current
t
CK
= min, I
RC
=min
Read/Write command cycling
OV<=V
IN
<=V
IL(AC)
(max.) V
IH(AC)
(min.) <=V
IN
<=VddQ
1 bank operation, Burst Length = 4
Address change up to 2 times during minimum I
RC
.
I
DD1S
310
300
290
mA
1, 2
Standby Current
t
CK
=min, CS = V
IH
, PD = V
IH
,
0V<=V
IN
<=V
IL(AC)
(max.) V
IH(AC)
(min.)<=V
IH
<=VddQ
All Banks : inactive state
Other input signals are changed one time during 4*t
CK
I
DD2N
85
85
80
1
Standby (Power Down) Current
t
CK
=min, CS = V
IH
, PD = V
IL
(Power Down)
0V<=V
IN
<=VddQ
All Banks : inactive state
I
DD2P
2
2
2
1
Auto-Refresh Current
t
CK
= min, I
REFC
= min, t
REFI
= min
Auto-Refresh command cycling
0V<=V
IN
<=V
IL
(AC) (max.), V
IH
(AC) (min.) <=V
IN
<=VddQ
Address change up to 2 times during minimum I
REFC
.
I
DD5
105
100
95
1
Self-Refresh Current
self-Refresh mode
PD = 0.2V, OV<=V
IN
<=VddQ
I
DD6
3
3
3
Item
Symbol
Min
Max
Unit
Notes
Input Leakage Current
(0V<=V
IN
<=VddQ, All other pins not under test = 0V)
I
LI
-5
5
uA
Output Leakage Current
(Output disabled, 0V<=V
OUT
<=VddQ)
I
LO
-5
5
uA
V
REF
Current
I
REF
-5
5
uA
Normal Output Driver
Output Source DC Current
V
OH
= VddQ - 0.4V
I
OH
(DC)
-10
-
mA
3
Output Sink DC Current
V
OL
=0.4V
I
OL
(DC)
10
-
3
Strong Output Driver
Output Source DC Current
V
OH
= VddQ - 0.4V
I
OH
(DC)
-11
-
3
Output Sink DC Current
V
OL
=0.4V
I
OL
(DC)
11
-
3
Weaker Output Driver
Output Source DC Current
V
OH
= VddQ - 0.4V
I
OH
(DC)
-8
-
3
Output Sink DC Current
V
OL
=0.4V
I
OL
(DC)
8
-
3
Weakest Output Driver
Output Source DC Current
V
OH
= VddQ - 0.4V
I
OH
(DC)
-7
-
3
Output Sink DC Current
V
OL
=0.4V
I
OL
(DC)
7
-
3
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K4C5608/1638C 256Mb Network-DRAM
REV. 0.7 Aug. 2003
- 11 -
AC Characteristics and Operating Conditions (Notes : 1, 2)
Symbol
Item
D4(400Mbps)
DA(366Mbps)
D3(333Mbps)
Units Notes
Min
Max
Min
Max
Min
Max
t
RC
Random Cycle Time
25
-
27.5
-
30
-
ns
3
t
CK
Clock Cycle Time
CL = 3
5.5
7.5
6
7.5
6.5
7.5
3
CL = 4
5
7.5
5.5
7.5
6
7.5
3
t
RAC
Random Access Time
-
22
-
24
-
26
3
t
CH
Clock High Time
0.45*t
CK
-
0.45*t
CK
-
0.45*t
CK
-
3
t
CL
Clock Low Time
0.45*t
CK
-
0.45*t
CK
-
0.45*t
CK
-
3
t
CKQS
DQS Access Time from CLK
-0.65
0.65
-0.75
0.75
-0.85
0.85
3, 8
t
QSQ
Data Output Skew from DQS
-
0.4
-
0.45
-
0.5
4
t
AC
Data Access Time from CLK
-0.65
0.65
-0.75
0.75
-0.85
0.85
3, 8
t
OH
Data Output Hold Time from CLK
-0.65
0.65
-0.75
0.75
-0.85
0.85
3, 8
t
QSPRE
DQS(Read) Preamble Pulse Width
0.9*t
CK
-0.2
1.1*t
CK
+0.2
0.9*t
CK
-0.2
1.1*t
CK
+0.2
0.9*t
CK
-0.2
1.1*t
CK
+0.2
3
t
HP
CLK half period ( minium of Actual t
CH
, t
CL
)
min(t
CH
, t
CL
)
-
min(t
CH
, t
CL
)
-
min(t
CH
, t
CL
)
-
t
QSP
DQS(Read) Pulse Width
t
HP-0.55
-
t
HP-0.6
-
t
HP-0.65
-
4
t
QSQV
Data Output Valid Time from DQS
t
HP-0.55
-
t
HP-0.6
t
HP-0.65
-
4
t
DQSS
DQS(Write) Low to High Setup Time
0.75*t
CK
1.25*t
CK
0.75*t
CK
1.25*t
CK
0.75*t
CK
1.25*t
CK
3
t
DSPRE
DQS(Write) Preamble Pulse Width
0.4*t
CK
-
0.4*t
CK
-
0.4*t
CK
-
4
t
DSPRES DQS First Input Setup Time
0
-
0
-
0
-
3
t
DSPREH DQS First Low Input Hold Time
0.25*t
CK
-
0.25*t
CK
-
0.25*t
CK
-
3
t
DSP
DQS High or Low Input Pulse Width
0.45*t
CK
0.55*t
CK
0.45*t
CK
0.55*t
CK
0.45*t
CK
0.55*t
CK
4
t
DSS
DQS Input Falling Edge to Clock Setup Time
CL = 3
1.3
-
1.4
-
1.5
-
3, 4
CL = 4
1.3
-
1.4
-
1.5
-
3, 4
t
DSPST
DQS(Write) Postamble Pulse Width
0.45*t
CK
-
0.45*t
CK
0.45*t
CK
-
4
t
DSPSTH DQS(Write) Postamble Hold Time
CL = 3
1.3
-
1.4
-
1.5
-
3, 4
CL = 4
1.3
-
1.4
-
1.5
-
3, 4
t
DSSK
UDQS - LDQS Skew (x16)
-0.5*t
CK
0.5*t
CK
-0.5*t
CK
0.5*t
CK
-0.5*t
CK
0.5*t
CK
t
DS
Data Input Setup Time from DQS
0.5
-
0.5
-
0.6
-
4
t
DH
Data Input Hold Time from DQS
0.5
-
0.5
-
0.6
-
4
t
DIPW
Data Input pulse Width (for each device)
1.5
-
1.5
-
1.9
-
t
IS
Command / Address Input Setup Time
0.9
-
0.9
-
1
-
3
t
IH
Command / Address Input Hold Time
0.9
-
0.9
-
1
-
3
t
IPW
Command / Address Input Pulse Width (for each device)
2.0
-
2.0
-
2.2
-
t
LZ
Data-out Low Impedance Time from CLK
-0.65
-
-0.75
-
-0.85
-
3, 6, 8
t
HZ
Data-out High Impedance Time from CLK
-
0.65
-
0.75
-
0.85
3, 7, 8
t
QSLZ
DQS-out Low Impedance Time from CLK
-0.65
-
-0.75
-
-0.85
-
3, 6, 8
t
QSHZ
DQS-out High Impedance Time from CLK
-0.65
0.65
-0.75
0.75
-0.85
0.85
3, 7, 8
t
QPDH
Last Output to PD High Hold Time
0
-
0
-
0
-
t
PDEX
Power Down Exit Time
2
-
2
-
2
-
3
t
T
Input Transition Time
0.1
1
0.1
1
0.1
1
t
FPDL
PD Low Input Window for Self-Refresh Entry
-0.5*t
CK
5
-0.5*t
CK
5
-0.5*t
CK
5
3
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K4C5608/1638C 256Mb Network-DRAM
REV. 0.7 Aug. 2003
- 12 -
AC Characteristics and Operating Conditions (Notes : 1, 2) (Continued)
Symbol
Item
D4(400Mbps)
DA(366Mbps)
D3(333Mbps)
Units Notes
Min
Max
Min
Max
Min
Max
t
REFI
Auto-Refresh Average Interval
0.4
7.8
0.4
7.8
0.4
7.8
us
5
t
PAUSE
Pause Time after Power-up
200
-
200
-
200
-
I
RC
Random Read/Write Cycle Time
(Applicable to Same Bank)
CL = 3
5
-
5
-
5
-
Cycle
CL = 4
5
-
5
-
5
-
I
RCD
RDA/WRA to LAL Command Input Delay
(Applicable to Same Bank)
1
1
1
1
1
1
I
RAS
LAL to RDA/WRA Command Input Delay
(Applicable to Same Bank)
CL = 3
4
-
4
-
4
-
CL = 4
4
-
4
-
4
-
I
RBD
Random Bank Access Delay
(Applicable to Other Bank)
2
-
2
-
2
-
I
RWD
LAL following RDA to WRA Delay
(Applicable to Other Bank)
BL = 2
2
-
2
-
2
-
BL = 4
3
-
3
-
3
-
I
WRD
LAL following WRA to RDA Delay
(Applicable to Other Bank)
1
-
1
-
1
-
I
RSC
Mode Register Set Cycle Time
CL = 3
5
-
5
-
5
-
CL = 4
5
-
5
-
5
-
I
PD
PD Low to Inactive State of Input Buffer
-
1
-
1
-
1
I
PDA
PD High to Active State of Input Buffer
-
1
-
1
-
1
I
PDV
Power down mode valid from REF command
CL = 3
15
-
15
-
15
-
CL = 4
18
-
18
-
18
-
I
REFC
Auto-Refresh Cycle Time
CL = 3
15
-
15
-
15
-
CL = 4
18
-
18
-
18
-
I
CKD
REF Command to Clock Input Disable
at Self-Refresh Entry
16
-
16
-
16
-
I
LOCK
DLL Lock-on Time (Applicable to RDA command)
200
-
200
-
200
-
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K4C5608/1638C 256Mb Network-DRAM
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- 13 -
AC Test Conditions
Symbol
Parameter
Value
Units
Notes
V
IH
(min)
Input high voltage (minimum)
V
REF
+ 0.35
V
V
IL
(max)
Input low voltage (maximum)
V
REF
- 0.35
V
V
REF
Input reference voltage
VddQ/2
V
V
TT
Termination voltage
V
REF
V
V
SWING
Input signal peak to peak swing
1.0
V
V
R
Differential clock input reference level
V
X(AC)
V
V
ID
(AC)
Input differential voltage
1.5
V
SLEW
Input signal minimum slew rate
1.0
V/ns
V
OTR
Output timing measurement reference voltage
VddQ/2
V
V
IH
min
(AC)
V
REF
V
IL
max
(AC)
V
SWING
VddQ
Vss
Z=50
R
T
=50
V
TT
CL=30pF
V
REF
Measurement Point
Output
Output Load Circuit(SSTL_2)
Slew=(V
IH
min
(AC)
- V
IL
max
(AC)
)/
T
T
T
Notes : 1. Transition times are measured between V
IH
min
(DC)
and V
IL
max
(DC)
.
Transition (rise and fall) of input signals have a fixed slope.
2. If the result of nominal calculation with regard to t
CK
contains more than
one decimal place, the result is rounded up to the nearest decimal place.
(i.e., t
DQSS
= 0.75*t
CK
, t
CK
= 5ns, 0.75*5ns = 3.75ns is rounded up to 3.8ns.)
3. These parameters are measured from the differential clock (CK and CK) AC cross point.
4. These parameters are measured from signal transition point of DQS crossing V
REF
level.
5. The t
REFI
(MAX.) applies to equally distributed refresh method.
The t
REFI
(MIN.) applies to both burst refresh method and distributed refresh method.
In such case, the average interval of eight consecutive Auto-Refresh commands has to be more than 400ns always. In
other words, the number of Auto- Refresh cycles which can be performed within 3.2us (8X400ns) is to 8 times in the
maximum.
6. Low Impedance State is speified at VddQ/2 0.2V from steady state.
7. High Impedance State is specified where output buffer is no longer driven.
8. These parameters depend on the clock jitter. These parameters are measured at stable clock.
=0.5*VddQ
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K4C5608/1638C 256Mb Network-DRAM
REV. 0.7 Aug. 2003
- 14 -
Power Up Sequence
1. As for PD, being maintained by the low state (<0.2V) is desirable before a power-supply injection.
2. Apply Vdd before or at the same time as VddQ.
3. Apply VddQ before or at the same time as V
REF
.
4. Start clock (CK, CK) and maintain stable condition for 200us (min.).
5. After stable power and clock, apply DESL and take PD = H.
6. Issue EMRS to enable DLL and to define driver strength. (Note : 1)
7. Issue MRS for set CAS Latency (CL), Burst Type (BT), and Burst Length (BL). (Note : 1)
8. Issue two or more Auto-Refresh commands. (Note:1)
9. Ready for normal operation after 200 clocks from Extended Mode Register programming. (Note : 2)
Note : 1. Sequence 6, 7 and 8 can be issued in random order.
2. L=Logic Low, H = Logic High
DESL
RDA MRS
DESL
RDA MRS
DESL WRA REF
WRA REF
DESL
DESL
EMRS
MRS
op-code
op-code
Hi-Z
V
DD
V
DDQ
V
REF
CLK
CLK
PD
Command
Address
DQ
DQS
200
s(min)
t
PDA
l
RSC
l
RSC
l
REFC
2.5V(TYP)
2.5V(TYP)
1.25V(TYP)
l
REFC
t
PDEX
200 clock cycle(min)
EMRS
MRS
Auto Refresh cycle
Nomal Operation
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K4C5608/1638C 256Mb Network-DRAM
REV. 0.7 Aug. 2003
- 15 -
t
CK
t
CK
t
CH
t
CL
t
IS
t
IH
t
IPW
1st
t
IS
t
IH
2nd
t
IS
t
IH
1st
t
IS
t
IH
2nd
t
IPW
t
IS
t
IH
t
IPW
UA, BA
t
IS
t
IH
LA
t
DIPW
t
DIPW
t
DS
t
DH
t
DS
t
DH
CK
CK
CS
FN
A0-A14
BA0.BA1
DQS
DQ(Input)
~~
Basic Timing Diagrams
Timing of the CK, /CK
Refer to the Command Truth Table.
Input Timing
t
CH
t
CL
t
CK
t
T
t
T
V
IH
V
IH(AC)
V
IL(AC)
V
IL
CK
CK
CK
V
IH
V
IL
V
ID(AC)
CK
V
X
V
X
V
X
~~
~~
~~
~~
~~
~~
~~
~~
~~
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K4C5608/1638C 256Mb Network-DRAM
REV. 0.7 Aug. 2003
- 16 -
Q0
Q1
Q2
Q3
LAL
(after RDA)
t
IPW
t
IS
t
IH
t
CH
t
CL
t
CK
t
QSLZ
t
QSPRE
t
CKQS
t
CKQS
t
QSP
t
QSP
t
CKQS
t
QSHZ
Postamble
Preamble
t
QSLZ
t
QSPRE
t
CKQS
t
QSP
t
QSP
t
QSHZ
t
CKQS
t
CKQS
t
QSQ
t
LZ
t
QSQV
t
AC
t
AC
t
AC
t
QSQV
t
QSQ
t
HZ
t
OH
Q0
Q1
Q2
Q3
t
LZ
t
AC
t
AC
t
AC
t
QSQV
t
QSQ
t
HZ
t
OH
t
QSQ
t
QSQ
t
QSQ
t
QSQV
High-Z
High-Z
High-Z
High-Z
CK
CK
Input
(Control &
Addresses)
CAS latency = 3
DQS
(Output)
DQ
(Output)
DQS
(Output)
DQ
(Output)
CAS latency = 4
Note : The correspondence of LDQS, UDQS to DQ. (K4C561638C-TC)
LDQS
DQ0 to 7
UDQS
DQ8 to 15
Postamble
Preamble
Read Timing (Burst Length = 4)
High-Z
High-Z
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K4C5608/1638C 256Mb Network-DRAM
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- 17 -
D0
D1
D2
D3
LAL
(after WRA)
CK
CK
Input
(Control &
Addresses)
DQS
(Input)
DQ
(Input)
t
IPW
t
IS
t
IH
t
CH
t
CL
t
CK
t
DQSS
t
DSPRES
t
DSP
t
DSP
t
DSP
t
DSPST
t
DSS
t
DSPSTH
Postamble
Preamble
t
DSS
t
DSPRE
t
DS
t
DH
t
DS
t
DH
t
DS
t
DH
t
DQSS
Write Timing (Burst Length = 4)
CAS latency = 3
D0
D1
D2
D3
DQS
(Input)
DQ
(Input)
t
DSPRES
t
DSP
t
DSP
t
DSP
t
DSPST
t
DSS
t
DSPSTH
Postamble
Preamble
t
DSS
t
DS
t
DH
t
DIPW
t
DS
t
DH
t
DS
t
DH
t
DQSS
CAS latency = 4
t
DSS
t
DQSS
Note. The correspondence of LDQS, UDQS to DQ. (K4C561638C-TC)
LDQS
DQ0 to 7
UDQS
DQ8 to 15
Command
CK
CK
Input
(Control &
Addresses)
t
IS
t
IH
tREFI, tPAUSE, Ixxxx Timing
t
IS
t
IH
Command
t
REFI,
t
PAUSE,
I
XXXX
Note. "
I
XXXX
"means "
I
RC
", "
I
RCD
", "
I
RAS
", etc.
~ ~
~ ~
t
DIPW
t
DSPRE
t
DSPREH
t
DSPREH
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K4C5608/1638C 256Mb Network-DRAM
- 18 -
REV. 0.7 Aug. 2003
D0
D1
D2
D3
Postamble
Preamble
t
DSSK
t
DS
t
DH
t
DS
t
DH
t
DS
t
DH
t
DS
t
DH
D0
D1
D2
D3
Postamble
Preamble
t
DS
t
DH
t
DS
t
DH
t
DH
t
DS
t
DH
D0
D1
D2
D3
WRA
CK
CK
Input
(Control &
Addresses)
LDQS
DQ0 ~ 7
Postamble
Preamble
Write Timing (x16 device) (Burst Length = 4)
CAS latency = 3
LAL
t
DSSK
t
DSSK
t
DSSK
t
DSSK
t
DS
t
DH
t
DS
t
DH
t
DS
t
DH
t
DS
t
DH
D0
D1
D2
D3
Postamble
Preamble
t
DS
t
DH
t
DS
t
DH
t
DS
t
DH
t
DS
t
DH
UDQS
DQ8 ~ 15
LDQS
DQ0 ~ 7
CAS latency = 4
UDQS
DQ8 ~ 15
t
DSSK
t
DSSK
t
DSSK
t
DS
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K4C5608/1638C 256Mb Network-DRAM
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- 19 -
Function Truth Table (Notes : 1,2,3)
Command Truth Table (Notes : 4)
The First Command
Symbol
Function
CS
FN
BA1-BA0
A14-A9
A8
A7
A6-A0
DESL
Device Deselect
H
X
X
X
X
X
X
RDA
Read with Auto-close
L
H
BA
UA
UA
UA
UA
WRA
Write with Auto-close
L
L
BA
UA
UA
UA
UA
The Second Command (The next clock of RDA or WRA command)
Notes : 1. L = Logic Low, H = Logic High, X = either L or H, V = Valid (Specified Value), BA = Bank Address, UA = Upper Address,
LA = Lower Address.
2. All commands are assumed to issue at a valid state.
3. All inputs for command (excluding SELFX and PDEX) are latched on the crossing point of differential clock input where
CLK goes to High.
4. Operation mode is decided by the comination of 1st command and 2nd command refer to "STATE DIAGRAM" and the
command table below.
Symbol
Function
CS
FN
BA1-BA0 A14-A13 A12-A11 A10-A9
A8
A7
A6-A0
LAL
Lower Address Latch (x16)
H
X
X
V
V
X
X
X
LA
LAL
Lower Address Latch (x8)
H
X
X
V
X
X
X
LA
LA
REF
Auto-Refresh
L
X
X
X
X
X
X
X
X
MRS
Mode Register Set
L
X
V
L
L
L
L
V
V
Read Command Table
Notes : 5. For x16 device, A7 is "X" (either L or H).
Command (Symbol)
CS
FN
BA1-BA0
A14-A9
A8
A7
A6-A0
Notes
RDA (1st)
L
H
BA
UA
UA
UA
UA
LAL (2nd)
H
X
X
X
X
LA
LA
5
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K4C5608/1638C 256Mb Network-DRAM
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- 20 -
Write Command Table
K4C561638C-TC
Command (Symbol)
CS
FN
BA1-BA0
A14
A13
A12
A11
A10-A9
A8
A7
A6-A0
WRA (1st)
L
L
BA
UA
UA
UA
UA
UA
UA
UA
UA
LAL (2nd)
H
X
X
LVWO
LVW1
UVW0
UVW1
X
X
X
LA
K4C560838C-TC
Note : 6. A14 to A11 are used for variable Write Length (VW) control at Write Operation.
Command (Symbol)
CS
FN
BA1-BA0
A14
A13
A12
A11
A10-A9
A8
A7
A6-A0
WRA (1st)
L
L
BA
UA
UA
UA
UA
UA
UA
UA
UA
LAL (2nd)
H
X
X
VWO
VW1
X
X
X
X
LA
LA
VW Truth Table
Note : 7. For x16 device, LVW0 and LVW1 control DQ0-DQ7, UVW0 and UVW1 control DQ8-DQ15.
Function
VW0
VW1
BL = 2
Write All Words
L
X
Write First One Word
H
X
BL = 4
Reserved
L
L
Write All Words
H
L
Write First Two Words
L
H
Write First One Word
H
H
Mode Register Set Command Truth Table
Note : 8. Refer to "Mode Register Table".
Command (Symbol)
CS
FN
BA1-BA0
A14-A9
A8
A7
A6-A0
Notes
RDA (1st)
L
H
X
X
X
X
X
MRS (2nd)
L
X
V
L
L
V
V
8
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K4C5608/1638C 256Mb Network-DRAM
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- 21 -
Function Truth Table (Continued)
Auto-Refresh Command Table
Function
Command
(Symbol)
Current
State
PD
CS
FN
BA1-BA0 A14-A9
A8
A7
A6-A0
Notes
n-1
n
Active
WRA(1st)
Standby
H
H
L
L
X
X
X
X
X
Auto-Refresh
REF(2nd)
Active
H
H
L
X
X
X
X
X
X
Self-Refresh Command Table
Function
Command
(Symbol)
Current
State
PD
CS
FN BA1-BA0 A14-A9 A8
A7 A6-A0 Notes
n-1
n
Active
WRA(1st)
Standby
H
H
L
L
X
X
X
X
X
Self-Refresh Entry
REF(2nd)
Active
H
L
L
X
X
X
X
X
X
9, 10
Self-Refresh Continue
-
Self-Refresh
L
L
X
X
X
X
X
X
X
Self-Refresh Exit
SELFX
Self-Refresh
L
H
H
X
X
X
X
X
X
11
Power Down Table
Notes : 9. PD has to be brought to Low within t
FPDL
from REF command.
10. PD should be brought to Low after DQ's state turned high impedance.
11. When PD is brought to High from Low, this function is executed asynchronously.
Function
Command
(Symbol)
Current
State
PD
CS
FN BA1-BA0 A14-A9 A8
A7
A6-A0 Notes
n-1
n
Power Down Entry
PDEN
Standby
H
L
H
X
X
X
X
X
X
10
Power Down Continue
-
Power Down
L
L
X
X
X
X
X
X
X
Power Down Exit
PDEX
Power Down
L
H
H
X
X
X
X
X
X
11
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Function Truth Table (Continued)
Notes : 12. Illegal if any bank is not idle.
13. Illegal to bank in specified states : Function may be Legal in the bank indicated by bank Address (BA).
14. Illegal if t
FPDL
is not satisfied.
Current State
PD
CS
FN
Address
Command
Action
Notes
n-1
n
Idle
H
H
H
X
X
DESL
NOP
H
H
L
H
BA, UA
RDA
Row activate for Read
H
H
L
L
BA, UA
WRA
Row activate for Write
H
L
H
X
X
PDEN
Power Down Entry
12
H
L
L
X
X
-
Illegal
L
X
X
X
X
-
Refer to Power Down state
Row Active for Read
H
H
H
X
LA
LAL
Begin read
H
H
L
X
Op-Code
MRS/EMRS Access to Mode Register
H
L
H
X
X
PDEN
Illegal
H
L
L
X
X
REF (Self)
Illegal
L
X
X
X
X
-
Invalid
Row Active for Write
H
H
H
X
LA
LAL
Begin Write
H
H
L
X
X
REF
Auto-Refresh
H
L
H
X
X
PDEN
Illegal
H
L
L
X
X
REF (Self)
Self-Refresh entry
L
X
X
X
X
-
Invalid
Read
H
H
H
X
X
DESL
Continue burst read to end
H
H
L
H
BA, UA
RDA
Illegal
13
H
H
L
L
BA, UA
WRA
Illegal
13
H
L
H
X
X
PDEN
Illegal
H
L
L
X
X
-
Illegal
L
X
X
X
X
-
Invalid
Write
H
H
H
X
X
DESL
Data write & continue burst write to end
13
H
H
L
H
BA, UA
RDA
Illegal
H
H
L
L
BA, UA
WRA
Illegal
13
H
L
H
X
X
PDEN
Illegal
H
L
L
X
X
-
Illegal
L
X
X
X
X
-
Invalid
Auto-Refreshing
H
H
H
X
X
DESL
NOP-> Idle after I
REFC
H
H
L
H
BA, UA
RDA
Illegal
H
H
L
L
BA, UA
WRA
Illegal
H
L
H
X
X
PDEN
Self-Refresh entry
H
L
L
X
X
-
Illegal
L
X
X
X
X
-
Refer to Self-Refreshing state
Mode Register Accessing
H
H
H
X
X
DESL
Nop-> Idle after I
RSC
H
H
L
H
BA, UA
RDA
Illegal
H
H
L
L
BA, UA
WRA
Illegal
H
L
H
X
X
PDEN
Illegal
14
H
L
L
X
X
-
Illegal
L
X
X
X
X
-
Invalid
Power Down
H
X
X
X
X
-
Invalid
L
L
X
X
X
-
Maintain Power Down Mode
L
H
H
X
X
RDEX
Exit Power Down Mode->Idle after t
PDEX
L
H
L
X
X
-
Illegal
Se;f-Refreshing
H
X
X
X
X
-
Invalid
L
L
X
X
X
-
Maintain Self-Refresh
L
H
H
X
X
SELFX
Exit Self-Refresh->Idle after I
REFC
L
H
L
X
X
-
Illegal
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Mode Register Table
Regular Mode Register
(Notes : 1)
Address
BA1
*1
BA0
*1
A14-A8
A7
*3
A6-A4
A3
A2-A0
Register
0
0
0
TM
CL
BT
BL
A7
Test Mode (TM)
0
Regular (Default)
1
Test Mode Entry
A3
Burst Type (BT)
0
Sequential
1
Interleave
A6
A5
A4
CAS Latency (CL)
0
0
X
Reserved
*2
0
1
0
Reserved
*2
0
1
1
3
1
0
0
4
1
0
1
Reserved
*2
1
1
X
Reserved
*2
A2
A1
A0
Burst Length (BL)
0
0
0
Reserved
*2
0
0
1
2
0
1
0
4
0
1
1
Reserved
*2
1
X
X
Extended Mode Register (Notes : 4)
Address
BA1
*4
BA0
*4
A14-A7
A6
A5-A2
A1
A0
Register
0
1
0
DIC
0
DIC
DS
A6
A1
Output Driver Impedance Control (DIC)
0
0
Normal Output Driver
0
1
Strong Output Driver
1
0
Weaker Output Driver
1
1
Weakest Output Driver
A0
DLL Switch (DS)
0
DLL Enable
1
DLL Disable
Note : 1. Regular Mode Register is Chosen Using the combination of BA0 = 0 and BA1 = 0.
2. "Reserved" places in Regular Mode Register should not be set.
3. A7 in Regular Mode Register must be set to "0"(Low state).
Because test Mode is specific mode for supplier.
4. Extended Mode Register is chosen using the Combination of BA0 = 1 and BA1 = 0.
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State Diagram
Self
Refresh
Power
Down
Standby
(Idle)
Mode
Register
Auto-
Refresh
Active
(Restore)
Active
Write
(Buffer)
Read
PDEX
(PD = H)
SELFX
(PD = H)
PD = L
PD = H
LAL
LAL
REF
MRS
RDA
WRA
PDEN
(PD = L)
The second command at Active
state must be issued 1clock after
RDA or WRA command input
Command Input
Automatic Return
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Q0 Q1
Q0 Q1
RDA
LAL
DESL
RDA
LAL
DESL
RDA
LAL
Q0 Q1 Q2 Q3
Q0 Q1 Q2 Q3
0
2
3
4
5
6
7
8
9
10
11
1
I
RC
= 5 cycles
I
RC
= 5 cycles
I
RCD
= 1 cycle
I
RAS
= 4 cycles
I
RCD
= 1 cycle
I
RAS
= 4 cycles
Hi-Z
Hi-Z
Hi-Z
Hi-Z
CL = 3
CL = 3
Hi-Z
Hi-Z
CL = 3
CL = 3
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
CK
CK
Command
DQS
(Output)
BL = 2
DQ
(Output)
DQS
(Output)
BL = 4
DQ
(Output)
Q0 Q1
Q0 Q1
RDA
LAL
DESL
RDA
LAL
DESL
RDA
LAL
Q0 Q1 Q2 Q3
Q0 Q1 Q2
0
2
3
4
5
6
7
8
9
10
11
1
I
RC
= 5 cycles
I
RC
= 5 cycles
I
RCD
= 1 cycle
I
RAS
= 4 cycles
I
RCD
= 1 cycle
I
RAS
= 4 cycles
Hi-Z
Hi-Z
Hi-Z
Hi-Z
CL = 4
CL = 4
Hi-Z
Hi-Z
Hi-Z
Hi-Z
CK
CK
Command
DQS
(Output)
BL = 2
DQ
(Output)
DQS
(Output)
BL = 4
DQ
(Output)
Timing Diagrams
Single Bank Read Timing (CL = 3)
CL = 4
CL = 4
Single Bank Read Timing (CL = 4)
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WRA
LAL
DESL
WRA
LAL
DESL
WRA
LAL
D0 D1
0
2
3
4
5
6
7
8
9
10
11
1
I
RC
= 5 cycles
I
RC
= 5 cycles
CK
CK
Command
DQS
(Input)
BL = 2
DQ
(input)
Single Bank Write Timing (CL = 3)
D0 D1
D0 D1
D0 D1
D2 D3
D2 D3
I
RAS
= 4 cycles
I
RCD
= 1 cycle
I
RAS
= 4 cycles
I
RCD
= 1 cycle
I
RCD
= 1 cycle
WL = 2
WL = 2
DQS
(Input)
BL = 4
DQ
(input)
t
DQSS
t
DQSS
t
DQSS
WL = 2
WL = 2
WRA
LAL
DESL
WRA
LAL
DESL
WRA
LAL
D0 D1
0
2
3
4
5
6
7
8
9
10
11
1
I
RC
= 5 cycles
I
RC
= 5 cycles
CK
CK
Command
DQS
(Input)
BL = 2
DQ
(input)
Single Bank Write Timing (CL = 4)
D0 D1
D0 D1
D0 D1
D2 D3
D2 D3
I
RAS
= 4 cycles
I
RCD
= 1 cycle
I
RAS
= 4 cycles
I
RCD
= 1 cycle
I
RCD
= 1 cycle
WL = 3
WL = 3
DQS
(Input)
BL = 4
DQ
(input)
t
DQSS
t
DQSS
WL = 3
WL = 3
Note :
means "H" or "L"
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D0 D1
Q0 Q1
RDA
LAL
DESL
WRA
LAL
DESL
RDA
LAL
Q0 Q1 Q2 Q3
D0 D1 D2 D3
0
2
3
4
5
6
7
8
9
10
11
1
I
RC
= 5 cycles
I
RC
= 5 cycles
I
RCD
= 1 cycle
I
RAS
= 4 cycles
I
RCD
= 1 cycle
I
RAS
= 4 cycles
Hi-Z
Hi-Z
Hi-Z
Hi-Z
CL = 3
WL = 2
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
CK
CK
Command
DQS
BL = 2
DQ
DQS
BL = 4
DQ
Single Bank Read-Write Timing (CL = 3)
D0 D1
Q0 Q1
RDA
LAL
DESL
WRA
LAL
DESL
RDA
LAL
Q0 Q1 Q2 Q3
D0 D1 D2 D3
0
2
3
4
5
6
7
8
9
10
11
1
I
RC
= 5 cycles
I
RC
= 5 cycles
I
RCD
= 1 cycle
I
RAS
= 4 cycles
I
RCD
= 1 cycle
I
RAS
= 4 cycles
Hi-Z
Hi-Z
Hi-Z
Hi-Z
CL = 4
WL = 3
Hi-Z
Hi-Z
CL = 4
WL = 3
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
CK
CK
Command
Single Bank Read-Write Timing (CL = 4)
CL = 3
WL = 2
t
DQSS
DQS
BL = 2
DQ
DQS
BL = 4
DQ
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RDAa
RDAb
0
2
3
4
5
6
7
8
9
10
11
1
I
RC
= 5 cycles
I
RBD
= 2 cycles
CK
CK
Command
Multiple Bank Read Timing (CL = 3)
I
RAS
= 4 cycles
LALa
RDAb
LALb
DESL
RDAa
LALa
RDAc
LALc
RDAd
LALd
Bank"b"
X
Bank"a"
X
Bank"a"
X
Bank"c"
X
Bank"d"
X
Bank"b"
Hi-Z
Hi-Z
Qa0 Qa1
Hi-Z
CL = 3
CL = 3
Hi-Z
Hi-Z
Hi-Z
Qb0 Qb1
Qa0 Qa1
Qc0
Hi-Z
Qa0 Qa1
Hi-Z
CL = 3
CL = 3
Hi-Z
Qb0 Qb1
Qc0
Qa2 Qa3
Qb3
Qb2
Qa0 Qa1 Qa2 Qa3
CL = 3
CL = 3
I
RBD
= 2 cycles
I
RCD
= 1 cycle
I
RCD
= 1 cycle
I
RCD
= 1 cycle
I
RCD
= 1 cycle
I
RBD
= 2 cycles
I
RBD
= 2 cycles
Bank Add.
(BA0, BA1)
DQS
BL = 2
DQ
DQS
BL = 4
DQ
(Output)
(Output)
(Output)
(Output)
RDAa
RDAb
0
2
3
4
5
6
7
8
9
10
11
1
I
RC
= 5 cycles
I
RBD
= 2 cycles
CK
CK
Command
Multiple Bank Read Timing (CL = 4)
I
RAS
= 4 cycles
LALa
RDAb
LALb
DESL
RDAa
LALa
RDAc
LALc
RDAd
LALd
Bank"b"
X
Bank"a"
X
Bank"a"
X
Bank"c"
X
Bank"d"
X
Bank"b"
Hi-Z
Hi-Z
Qa0 Qa1
Hi-Z
CL = 4
CL = 4
Hi-Z
Hi-Z
Hi-Z
Qb0 Qb1
Qa0 Qa1
Hi-Z
Qa0 Qa1
Hi-Z
CL = 4
CL = 4
Hi-Z
Qb0 Qb1
Qa2
Qa2 Qa3
Qb3
Qb2
Qa0 Qa1
CL = 4
CL = 4
I
RBD
= 2 cycles
I
RCD
= 1 cycle
I
RCD
= 1 cycle
I
RCD
= 1 cycle
I
RCD
=1 cycle
I
RBD
= 2 cycles
I
RBD
= 2 cycles
Bank Add.
(BA0, BA1)
DQS
BL = 2
DQ
DQS
BL = 4
DQ
(Output)
(Output)
(Output)
(Output)
Note : "X" is don't care. I
RC
to the same bank must be satisfied.
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Da0 Da1
0
2
3
4
5
6
7
8
9
10
11
1
CK
CK
Multiple Bank Write Timing (CL = 3)
Da0 Da1
WL = 2
t
DQSS
WRAa
WRAb
I
RC
= 5 cycles
I
RBD
= 2 cycles
I
RAS
= 4 cycles
LALa
WRAb
LALb
DESL
WRAa
LALa
WRAc
LALc
WRAd
LALd
Bank"b"
X
Bank"a"
X
Bank"a"
X
Bank"c"
X
Bank"d"
X
Bank"b"
I
RBD
= 2 cycles
I
RCD
= 1 cycle
I
RCD
= 1 cycle
I
RCD
= 1 cycle
I
RCD
= 1 cycle
I
RBD
= 2 cycles
I
RBD
= 2 cycles
t
DQSS
WL = 2
Db0 Db1
Dc0 Dc1
WL = 2
Da0 Da1
Db0 Db1
Da2 Da3
Db3
Db2
Da0 Da1
Dc0 Dc1
Da2 Da3
Dc2
Command
Bank Add.
(BA0, BA1)
DQS
BL = 2
DQ
DQS
BL = 4
DQ
(input)
(input)
(input)
(input)
WL = 2
t
DQSS
t
DQSS
t
DQSS
Da0 Da1
0
2
3
4
5
6
7
8
9
10
11
1
CK
CK
Multiple Bank Write Timing (CL = 4)
Da0 Da1
WL = 3
t
DQSS
WRAa
WRAb
I
RC
= 5 cycles
I
RBD
= 2 cycles
I
RAS
= 4 cycles
LALa
WRAb
LALb
DESL
WRAa
LALa
WRAc
LALc
WRAd
LALd
Bank"b"
X
Bank"a"
X
Bank"a"
X
Bank"c"
X
Bank"d"
X
Bank"b"
I
RBD
= 2 cycles
I
RCD
= 1 cycle
I
RCD
= 1 cycle
I
RCD
= 1 cycle
I
RCD
= 1 cycle
I
RBD
= 2 cycles
I
RBD
= 2 cycles
t
DQSS
WL = 3
Db0 Db1
Dc0
WL = 3
Da0 Da1
Db0 Db1
Da2 Da3
Db3
Db2
Da0 Da1
Dc0
Da2 Da3
Command
Bank Add.
(BA0, BA1)
DQS
BL = 2
DQ
DQS
BL = 4
DQ
(input)
(input)
(input)
(input)
WL = 3
t
DQSS
t
DQSS
t
DQSS
Dc1
Dc1
Note :
means "H" or "L" "X" is don't care I
RC
to the same bank must be satisfied.
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0
2
3
4
5
6
7
8
9
10
11
1
CK
CK
Multiple Bank Read-Write Timing (BL = 2)
t
DQSS
WRAa
LALc
I
RBD
= 2 cycles
LALa
RDAb
LALb
DESL
WRAc
LALc
RDAd
LALd
DESL
WRAc
Bank"b"
X
Bank"a"
X
Bank"c"
X
Bank"d"
Bank"c"
X
Command
Bank Add.
(BA0, BA1)
DQS
CL = 3
DQ
DQS
CL = 4
DQ
Dc0 Dc1
Da0 Da1
Hi-Z
Hi-Z
WL = 2
Qb0 Qb1
Qd0
X
I
RCD
= 1 cycle
I
RWD
= 2 cycles
I
RBD
= 2 cycles
I
RWD
= 2 cycles
I
RC
= 5 cycles
I
RCD
= 1 cycle
I
WRD
= 1 cycle
I
RCD
= 1 cycle
I
WRD
= 1 cycle
I
RCD
= 1 cycle
t
DQSS
Hi-Z
Hi-Z
CL = 3
WL = 2
CL = 3
t
DQSS
Dc0 Dc1
Da0 Da1
WL =3
Qb0 Qb1
t
DQSS
Hi-Z
Hi-Z
CL = 4
WL = 3
CL = 4
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Multiple Bank Read-Write Timing (BL = 4)
WL = 2
0
2
3
4
5
6
7
8
9
10
11
1
CK
CK
WRAa
I
RBD
= 2 cycles
LALa
RDAb
LALb
WRAc
LALc
RDAd
LALd
Bank"b"
X
Bank"a"
X
Bank"c"
X
Command
Bank Add.
(BA0, BA1)
DQS
CL = 3
DQ
Da0 Da1
Hi-Z
Hi-Z
Qb0 Qb1
I
RCD
= 1 cycle
I
RWD
= 3 cycles
I
RBD
= 2 cycles
I
RCD
= 1 cycle
I
WRD
= 1 cycle
I
RCD
= 1 cycle I
WRD
= 1 cycle
I
RCD
= 1 cycle
t
DQSS
t
DQSS
DESL
X
Bank"d"
DESL
Da2 Da3
Qb2 Qb3
Dc0 Dc1 Dc2 Dc3
t
DQSS
t
DQSS
CL = 3
Hi-Z
WL = 2
CL = 3
Hi-Z
WL = 3
DQS
CL = 4
DQ
Da0 Da1
Hi-Z
Hi-Z
Qb0 Qb1
Da2 Da3
Qb2 Qb3
Dc0 Dc1 Dc2
CL = 4
WL = 3
Dc3
Note : "X" is dont care
I
RC
to the same bank must be satisfied.
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0
2
3
4
5
6
7
8
9
10
11
1
CK
CK
Single Bank Write with VW (CL=3, BL=4, Sequential mode)
DESL
WRA
LAL
WRA
LAL
LAL
Command
Address
DQS
DESL
WRA
UA
LA=#3
UA
LA
UA
I
RC
= 5 cycles
I
RC
= 5 cycles
VW=2
LA=#1
VW=1
D0 D1
D0
DESL
WRA
LAL
WRA
LAL
LAL
Command
DESL
WRA
UA
LA=#3
UA
LA
UA
LVW=1
D0 D1
D0
D0
D0
x8 device
Last two data are masked
.
Last three data are masked
.
Address #3 #0 (#1) (#2)
#1 (#2) (#3) (#0)
(Input)
DQ
(Input)
x16 device
Address
UDQS
(Input)
DQ8 to
DQ15
(Input)
LDQS
(Input)
DQ0 to
DQ7
(Input)
UVW=2
LA=#3
LVW=1
UVW=1
Last two data are masked
.
Last three data are masked
.
Address #3 #0 (#1) (#2)
#1 (#2) (#3) (#0)
Address #3 (#0) (#1) (#2)
#1 (#2) (#3) (#0)
Last three data are masked
.
Last three data are masked
.
Notes : DQS input must be continued till end of burst count even if some of laster data is masked.
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Q0 Q1
RDA
LAL
DESL
RDA
MRS
DESL
RDA
0
2
3
4
5
6
7
8
9
10
11
1
I
RC
= 5 cycles
I
RCS
= 5 cycles
I
RCD
= 1 cycle
I
RAS
= 4 cycles
I
RCD
= 1 cycle
Hi-Z
Hi-Z
CL = 3
Hi-Z
Hi-Z
CK
CK
Command
Mode Register Set Timing (CL=3, BL=2)
DQS
DQ
or
WRA
BA,UA
LA
Valid
X
A14 to A0
(Op-Code)
BA,UA
X
BA0, BA1
(Output)
(Output)
Q0 Q1
RDA
LAL
DESL
X
RDA
0
2
3
4
5
6
7
n-1
n
n+1
n+2
1
I
PDA
= 1 cycles
I
RCD
= 1 cycle
t
IH
Hi-Z
Hi-Z
CL = 3
Hi-Z
Hi-Z
CK
CK
Command
Power Down Timing (CL=3, BL=2)
DQS
DQ
or
WRA
A14 to A0
BA0, BA1
(Output)
(Output)
DESL
IPD = 1 cycle
t
IS
t
QPDH
t
PDEX
Power Down Exit
Power Down Entry
Note : "x" is don't care.
IPD is defined from the first clock rising edage after PD is brought to "Low".
IPDA is defined from the first clock rising edage after PD is brought to "High".
PD must be kept "High" level until end of Burst data output.
PD should be brought to high within t
REFI(max)
to maintain the data written into cell.
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WRA
LAL
DESL
DESL
RDA
D0 D1 D2 D3
D1
0
1
2
3
4
5
6
7
8
9
n-1
n
n+1
n+2
CLK
CLK
Command
PD
BL=4
DQS
(Input)
DQ
(Input)
BL=2
DQS
(Input)
DQ
(Input)
x
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
or
WRA
I
RDA
= 1 cycle
WL=3
2 clock cycles
I
RC
(min), t
REFI
(max)
t
IH
t
IS
I
PD
= 1 cycle
D0
Power Down Entry
Power Down Exit
t
PDEX
Power Down Timing (CL=4)
Write cycle to Power Down Mode
Note : "x" is don't care.
PD must be kept "High" level until WL+2 clock cycles from LAL command.
PD should be brought to high within t
REFI(max)
to maintain the data written into cell.
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Q0 Q1
RDA
LAL
DESL
WRA
REF
DESL
LAL or
0
2
3
4
5
6
7
8
9
10
11
1
I
RC
= 5 cycles
I
REFC
= 15 cycles
I
RCD
= 1 cycle
I
RAS
= 4 cycles
I
RCD
= 1 cycle
Hi-Z
Hi-Z
CL = 3
Hi-Z
Hi-Z
CK
CK
Command
Auto-Refresh Timing (CL=3, BL=4)
DQS
DQ
MRS or
REF
(Output)
(Output)
RDA
or
WRA
Q2 Q3
~~
~~
~~
~~
~~
~~
WRA REF
WRA REF
WRA REF
t
1
t
2
t
3
CK
~~
WRA REF
WRA REF
t
8
~~
t
7
8 Refresh Cycle
t
REFI
=
Total time of 8 Refresh cycle
8
t
1
+ t
2
+ t
3
+ t
4
+ t
5
+ t
6
+ t
7
+ t
8
8
=
t
REFI
is specified to avoid partly concentrated current of Refresh operation that is activated larger area than
Read/Write operation.
Note : In case of CL=3, I
REFC
must be meet 15 clock cycles. When the Auto-Refresh operation is performed,
the synthetic average interval of Auto-Refresh command specified by t
REFI
must be satisfied. t
REFI
is
average Interval time in 8 Refresh cycles that is sampled randomly.
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Qx
WRA
REF
DESL
X
*1
0
2
3
4
5
m-1
m
m+1
1
I
REFC
t
FPDL
(min)
Hi-Z
CK
CK
Command
Self-Refresh Entry Timing
DQS
DQ
(Output)
(Output)
~~
~~
I
RCD
= 1 cycle
t
FPDL
(max)
t
QPDH
Hi-Z
I
CKD
= 16 cycleS
*3
~~
~~
~~
~~
~~
~~
~~
Note : 1. "X" is don't care.
2. PD msut be brought to "Low" within the timing between t
FPDL
(min) and t
FPDL
(max) to Self Refresh mode
When PD is brought to "Low" after I
PDV
, Network-DRAM perform Auto Refresh and enter Power down mode.
3. It is desirable that clock input is continued at least 16 clock cycles from REF command even though
PD is brought to "Low" for Self-Refresh Entry.
PD
X
*1
DESL
*3
WRA
*5
REF
*5
0
2
m-1
m
m+1
m+2
n-1
n
n+1
p-1
p
1
I
REFC
I
REFC
I
PDA
= 1 cycle *4
I
RCD
= 1 cycle
Hi-Z
Hi-Z
CK
CK
Command
Self-Refresh Exit Timing
DQS
DQ
(Output)
(Output)
~~
DESL
Command
(1st)
*6
Command
(2nd)
*6
RDA
*7
LAL
*7
t
PDEX
IRCD = 1 cycle
~~
~~
~~
~~
~~
~~
~~
~~
~~
~~
~~
~~
PD
Note : 1. "X" is don't care.,
2. Clock should be stable prior to PD = "High" if clock input is suspended in Self-Refresh mode.
3. DESL command must be asserted during I
REFC
after PD is brought to "High".
4. IPDA is defined from the first clock rising edge after PD is brought to "High".
5. It is desirable that one Auto-Refresh command is issued just after Self-Refresh Exit before any other operation.
6. Any command (except Read command) can be issued after I
REFC
.
7. Read command (RDA+LAL) can be issued after ILOCK.
ILOCK
Self-Refresh Exit
Auto Refresh
Self Refresh Entry
I
PDV
*2
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K4C5608/1638C 256Mb Network-DRAM
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Function Description
Network-DRAM
The Network-DRAM is Double Data Rate (DDR) operating. The Network-DRAM is competent to perform fast random core access,
low latency, low consumption and high-speed data bandwidth.
Pin Functions
Clock Inputs : CK & CK
The CK and CK inputs are used as the reference for synchronus operation. CK is master clock input. The CS, FN and all address
input signals are sampled on the crossing of the positive edge of CK and the negative edge of CK. The DQS and DQ and DQ output
data are referenced to the crossing point of CK and CK. The timing reference point for the differential clock is when the CK and CK sig-
nals cross during a transition.
Power Down : PD
The PD input controls the entry to the Power Down or Self-Refresh modes. The PD input does not have a Clock Suspend function like
a CKE input of a standard SDRAMs, therefore it is illegal to bring PD pin into low state if any Read or Write operation is being per-
formed.
Chip Select & Function Control : CS & FN
The CS and FN inputs are a control aignal for forming the operation commands on Network-DRAM. Each operation mode is decided
by the combination of the two consecutive operation commands using the CS and FN inputs.
Bank Addresses : BA0 & BA1
The BA0 and BA1 inputs are latched at the time of assertion of the RDA or WRA command and are selected the bank to be used for
the operation.
BA0
BA1
Bank #0
0
0
Bank #1
1
0
Bank #2
0
1
Bank #3
1
1
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K4C5608/1638C 256Mb Network-DRAM
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Functional Description (Continued)
Address Inputs : A0 to A14
Address inputs are used to access the arbitrary address of the memory cell array within each bank. The Upper Addresses with Bank
address are latched at the RDA or WRA command and the Lower Addresses are latched at the LAL command. The A0 to A14 inputs
are also used for setting the data in the Regular or Extended Mode Register set cycle.
Data Input/Output : DQ0 to DQ7 or DQ15
The input data of DQ0 to DQ15 are taken in synchronizing with the both edges of DQS input signal.
The output data of DQ0 to DQ15 are outputted synchronizing with the both edges of DQS output signal.
Data Strobe : DQS or LDQS, UDQS
The DQS is bi-directional signal. Both edges of DQS are used as the reference of data input or output. The LDQS is allotted for Lower
Byte (DQ0 to DQ7) Data. The UDQS is allotted for Upper Byte(DQ8 to DQ15) Data. In write operation, the DQS used as an input signal
is utilized for a latch of write data. In read operation, the DQS that is an output signal provides the read data strobe.
Power Supply : Vdd, VddQ, Vss, VssQ
Vdd and Vss are supply pins for memory core and peripheral circuits.
VddQ and VssQ are power supply pins for the output buffer.
Reference Voltage : V
REF
V
REF
is reference voltage for all input signals.
Upper Address
Lower Address
K4C560838C-TC
A0 to A14
A0 to A7
K4C561638C-TC
A0 to A14
A0 to A6
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K4C5608/1638C 256Mb Network-DRAM
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Functional Description (Continued)
Command Functions and Operations
K4C5608/1638C-TC are introduced the two consccutive command input method. Therefore, except for Power Down mode, each
operation mode decided by the combination of the first command and the second command from stand-by states of the bank to be
accessed.
Read Operation (1st command + 2nd command = RDA + LAL)
Issuing the RDA command with Bank Addresses and Upper Addresses to the idle bank puts the bank designated by Bank Address in
a read mode. When the LAL command with Lower Addresses is issued at the next clock of the RDA command, the data is read out
sequentially synchroniaing with the both edges of DQS output signal (Burst Read Operation). The initial valid read data appears after
CAS latency, the burst length of read data and the burst type must be set in the Mode Register beforehand. The read operated bank
goes back automatically to the idle state after I
RC
.
Write Operation (1st command + 2nd command = WRA + LAL)
Issuing the WRA command with Bank Addresses and Upper Addresses to the idle bank puts the bank designated by Bank Address
in a write mode. When the LAL command with Lower Addresses is issued at the next clock of the WRA command, the input data is
latched sequentially synchronizing with the both edges of DQS input signal (Burst Write Operation). The data and DQS inputs have to
be asserted in keeping with clock input after CAS latency-1 from the issuing of the LAL command. The write data length is set by the
VW in the LAL command. The DQS have to be provided for a burst length. The CAS latency and the burst type must be set in the
Mode Register beforehand. The write operated bank goes back automatically to the idle state after I
RC
.
Auto-Refresh Operation (1st command + 2nd command = WRA + REF)
K4C560838/1638C-TC are required to refresh like a standard SDRAM. The Auto-Refresh operation is begun with the REF command
following to the WRA command. The Auto-Refresh mode can be effective only when all banks are in the idle state and all outputs are
in Hi-z states. In a point to notice, the write mode started with the WRA command is canceled by the REF command having gone into
the next clock of the WRA command instead of the LAL command. The minimum period between the Auto-Refresh command and the
next command is specified by I
REFC
. However, about a synthetic average interval of Auto-Refresh command, it must be careful. In
case of equally distributed refresh, Auto-Refresh command has to be issued within once for every 7.8us by the maximum In case of
burst refresh or random distributed refresh, the average interval of eight consecutive Auto-Refresh command has to be more than
400ns always. In other words, the number of Auto-Refresh cycles which can be performed within 3.2us (8x400ns) is to 8 times in the
maximum.
Self-Refresh Operation (1st command + 2nd command = WRA + REF with PD="L")
It is the function of Self-Refresh operation that refresh operation can be performed automatically by using an internal timer. When all
banks are in the idle state and all outputs are in Hi-z states, the K4C560838/1638C-TC become Self-Refresh mode by issuing the Self-
Refresh command. PD has to be brought to "Low" within t
FPDL
from the REF command following to the WRA command for a Self-
Refresh mode entry. In order to satisfy the refresh period, the Self-Refresh entry command should be asserted within 7.8us after the
latest Auto-Refresh command. Once the device enters Self-Refresh mode, the DESL command must be continued for I
REFC
period. In
addition, it is desirable that clock input is kept in I
CKD
period. The device is in Self-Refresh mode as long as PD held "Low". During
Self-Refresh mode, all input and output buffers except for PD are disabled, therefore the power dissipation lowers. Regarding a Self-
Refresh mode exit, PD has to be changed over from "Low" to "High" along with the DESL command, and the DESL command has to
be continuously issued in the number of clocks specified by I
REFC
. The Self-Refresh exit function is asynchronous operation. It is
required that one Auto-Refresh command is issued to avoid the violence of the refresh period just after I
REFC
from Self-Refresh exit.
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K4C5608/1638C 256Mb Network-DRAM
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Power Down Mode( PD="L" )
When all banks are in the idle state and all outputs are in Hi-Z states, the K4C560838/1638C-TC become Power Down Mode by
asserting PD is "Low". When the device enters the Power Down Mode, all input and output buffers except for PD are disabled after
specified time. Therefore, the power dissipation lowers. To exit the Power Down Mode, PD has to be brought to "High" and the DESL
command has to be issued at next CK rising edge after PD goes high. The Power Down exit function is asynchronous operation.
Mode Register Set (1st command + 2nd command = RDA + MRS)
When all banks are in the idle state, issuing the MRS command following to the RDA command can program the Mode Register. In a
point to notice, the read mode started with the RDA command is canceled by the MRS command having gone into the next clock of the
RDA command instead of the LAL command. The data to be set in the Mode Register is transferred using A0 to A14, BA0 and BA1
address inputs. The K4C560838/1638C-TC have two mode registers. These are Regule and Extended Mode Register. The Regular or
Extended Mode Register is chosen by BA0 in the MRS command.The Regular Mode Register designates the operation mode for a
read or write cycle. The Regular Mode Register has four function fields.
The four fields are as follows :
(R-1) Burst Length field to set the length of burst data
(R-2) Burst Type field to designate the lower address access sequence in a burst cycle
(R-3) CAS Latency field to set the access time in clock cycle
(R-4) Test Mode field to use for supplier only.
The Extended Mode Register has two function fields.
The two fields are as follows:
(E-1) DLL Switch field to choose either DLL enable or DLL disable
(E-2) Output Driver Impedance Control field.
Once these fields in the Mode Register are set up, the register contents are maintained until the Mode Register is set up again by
another MRS command or power supply is lost. The initial value of the Regular or Extended Mode Register after power-up is unde-
fined, therefore the Mode Register Set command must be issued before proper operation.
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K4C5608/1638C 256Mb Network-DRAM
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Functional Description (Continued)
Regular Mode Register/Extended Mode Register change bits (BA0, BA1)
These bits are used to choose either Regular MRS or Extended MRS
Regular Mode Register Fields
(R-1) Burst Length field (A2 to A0)
This field specifies the data length for column access using the A2 to A0 pins and sets the Burst Length to be 2 or 4
words.
(R-2) Burst Type field (A3)
This Burst Type can be chosen Interleave mode or Sequential mode. When the A3 bit is " 0", Sequential mode is
selected. When the A3 bit is "1", Interleave mode is selected. Both burst types support burst length of 2 and 4 words.
Addressing sequence of Sequential mode (A3)
A column access is started from the inputted lower address and is performed by incrementing the lower address input to
the device. The address is varied by the Burst Length as the following.
BA1
BA0
A14 - A0
0
0
Regular MRS cycle
0
1
Extended MRS cycle
1
X
Reserved
A2
A1
A0
Burst Length
0
0
0
Reserved
0
0
1
2 words
0
1
0
4 words
0
1
1
Reserved
1
X
X
Reserved
A3
Burst Type
0
Sequential
1
Interleave
RDA
LAL
Data 0 Data 1 Data 2 Data 3
Addressing sequence for Sequential mode
Data
Access Address
Burst Length
Data 0
n
2 words (Address bits is LA0)
not carried from LA0 to LA1
4 words(Address bits is LA1, LA0)
not carried from LA0 to LA1
Data 1
n + 1
Data 2
n + 2
Data 3
n + 3
CAS Latency = 2
CK
CK
Command
DQS
DQ
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Functional Description (Continued)
Addressing sequence of Inteleave mode
A column access is started from the inputted lower address and is performed by interleaving the address bits in the
sequence shown as the following.
Addressing sequence for Interleave mode
(R-3) CAS Latency field (A6 to A4)
This field specifies the number of clock cycles from the assertion of the LAL command following the RDA command to
the first data read. The minimum values of CAS Latency depends on the frequency of CK. In a write mode, the place of
clock which should input write data is CAS Latency cycles - 1.
(R-4) Test Mode field (A7)
This bit is used to enter Test Mode for supplier only and must be set to "0" for normal operation.
(R-5) Reserved field in the Regular Mode Register
Reserved bits (A8 to A14)
These bits are reserved for future operations. They must be set to "0" for normal operation.
Data
Access Address
Burst Length
Data 0
...A8 A7 A6 A5 A4 A3 A2 A1 A0
2 words
4 words
Data 1
...A8 A7 A6 A5 A4 A3 A2 A1 A0
Data 2
...A8 A7 A6 A5 A4 A3 A2 A1 A0
Data 3
...A8 A7 A6 A5 A4 A3 A2 A1 A0
A6
A5
A4
CAS Latency
0
0
0
Reserved
0
0
1
Reserved
0
1
0
Reserved
0
1
1
3
1
0
0
4
1
0
1
Reserved
1<