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K4C89183AF
- 1 -
REV. 0.7 Jan. 2005
288Mb x18 Network-DRAM2 Specification
Version 0.7
K4C89183AF
- 2 -
REV. 0.7 Jan. 2005
Revision History
Version 0.0 (Oct. 2002)
- First Release
Version 0.01 (Nov. 2002)
- Changed die revision from D-die to F-die
- Corrected typo
- Corrected DQS to DS and QS(DQS -> DS and QS) in AC timing table and timing diagram.
Version 0.1 (Apr. 2003)
- Added 800Mbps(400Mhz) product
- Changed operating temperature from Ta to Tc.
- Changed capacitance of ADDR/CMD/CLK
- Changed tDSS(DS input Falling Edge to Clock Setup Time)
- Added CL7 for 800Mbps
- Deleted TSOP package outline
Version 0.11 (Apr. 2003)
- Corrected typo in page 3.(Deleted bi-directional strobe)
- Corrected min. Vref to VDDQ/2x95% in page 7
Version 0.2 (Aug. 2003)
- Added package physical dimension
- Extracted 800Mbps(G7) binning from target spec ( G7 will be added in the future)
- Changed DC test condition
- Changed low frequency spec like below
- Changed AC test load picture
Version 0.3 (Nov. 2003)
- Changed Packge type from die-exposed to full molded
- Changed Package code in Partnumber
From
To
Min
Max
Min
Max
Addr/CMD/CLK
1.5
2.5
1.5
3.0
From
To
F6
FB
F5
G7
F6
FB
F5
CL4
0.9
0.9
1.0
0.75
0.75
0.8
1.0
CL5
0.9
0.9
1.0
0.75
0.75
0.8
1.0
CL6
0.9
0.9
1.0
0.75
0.75
0.8
1.0
CL7
-
-
-
0.75
-
-
-
From
To
Changed point
IDD1S,IDD2N,IDD2P,IDD5,IDD6
IDD1S,IDD2N,IDD2P,IDD5B,IDD6
Changed condition
-
IDD4W, IDD4R
newly inserted
From
To
Unit : ns
F6
FB
F5
F6
FB
F5
tCK max@CL=4
7.5
7.5
7.5
6.0
6.0
6.0
tCK max@CL=5
7.5
7.5
7.5
6.0
6.0
6.0
tCK max@CL=6
7.5
7.5
7.5
6.0
6.0
6.0
K4C89183AF
- 3 -
REV. 0.7 Jan. 2005
Version 0.31 (Mar., 2004)
- Corrected typo. in page 7 (Changed operating Temperature to 85'C, case temperature)
Version 0.4 (Jun., 2004)
- Changed from "target" to "Preliminary"
- Changed min. tCK@CL5 to 3.5ns in "-F6"
Version 0.5 (Aug., 2004)
- Deleted self-refresh function and BL2 from spec
Version 0.51 (Aug., 2004)
- Corrected error in page 54, "Package Out line Drawing". (Just 4 balls were missing in drawing)
Version 0.6 (Nov., 2004)
- Deleted "preliminary"
- Changed current value in page 9
Version 0.7 (Jan., 2005)
- Deleted the tDQSQA in page 11
- Deleted the tSSK in page 11
From
To
F6
F6
t
CK
Clock Cycle Time (min)
CL = 4
4.0 ns
4.0 ns
CL = 5
3.33 ns
3.5 ns
CL = 6
3.0ns
3.0ns
K4C89183AF
- 4 -
REV. 0.7 Jan. 2005
4,194,304-WORDS x 4 BANKS x 18-BITS DOUBLE DATA RATE Network-DRAM
DESCRIPTION
K4C89183AF is a CMOS Double Data Rate Network-DRAM containing 301,989,888 memory cells. K4C89183AF is organized as
4,194,304-words x 4 banks x18 bits. K4C89183AF feature a fully synchronous operation referenced to clock edge whereby all opera-
tions are synchronized at a clock input which enables high performance and simple user interface coexistence. K4C89183AF can oper-
ate fast core cycle compared with regular DDR SDRAM.
K4C89183AF is suitable for Server, Network and other applications where large memory density and low power consumption are
required. The Output Driver for Network-DRAM is capable of high quality fast data transfer under light loading condition.
FEATURES
Parameter
K4C89183AF
F6
FB
F5
t
CK
Clock Cycle Time (min)
CL = 4
4.0 ns
4.5 ns
5.0 ns
CL = 5
3.5 ns
3.75 ns
4.5 ns
CL = 6
3.0ns
3.33 ns
4.0 ns
t
RC
Random Read/Write Cycle Time (min)
20.0 ns
22.5 ns
25 ns
t
RAC
Random Access Time (min)
20.0 ns
22.5 ns
25 ns
I
DD1S
Operating Current (single bank) (max)
320mA
300mA
280mA
I
DD2P
Power Down Current (max)
70mA
65mA
60mA
Fully Synchronous Operation
- Double Data Rate (DDR)
- Data input/output are synchronized with both edges of DS / QS.
- Differential Clock (CLK and CLK) inputs
- CS, FN and all address input signals are sampled on the positive edge of CLK.
- Output data (DQs and QS) is aligned to the crossings of CLK and CLK.
Fast clock cycle time of 3.0 ns minimum
- Clock : 333 MHz maximum
- Data : 666 Mbps/pin maximum
Quad Independent Banks operation
Fast cycle and Short Latency
Uni-directional Data Strobe
Distributed Auto-Refresh cycle in 3.9us
Power Down Mode
Variable Write Length Control
Write Latency = CAS Latency-1
Programable CAS Latency and Burst Length
- CAS Laatency = 4, 5, 6
- Burst Length = 4
Organization : 4,194,304 words x 4 banks x 18 bits
Power Supply Voltage V
DD
: 2.5V
0.125V
V
DDQ
: 1.4V
1.9V
1.8V CMOS I/O comply with SSTL - 1.8 (half strength driver) and HSTL
Package : 60Ball BGA, 1.0mm x 1.0mm Ball pitch
Notice : Network-DRAM is trademark of Samsung Electronics., Co LTD
K4C89183AF
- 5 -
REV. 0.7 Jan. 2005
Pin Names
Pin
Name
A0 ~ A14
Address Input
BA0, BA1
Bank Address
DQ0 ~ DQ17
Data Input/Output
CS
Chip Select
FN
Function Control
PD
Power Down Control
CLK, CLK
Clock Input
DS/QS
Write/Read data strobe
VDD
Power (+2.5V)
V
SS
Ground
V
DDQ
Power (+1.8V)
(for I/O buffer)
V
SSQ
Ground
(for I/O buffer)
V
REF
Reference Voltage
NC
No Connection
ball pitch=1.0 x 1.0mm
PIN ASSIGNMENT (TOP VIEW)
x18
Index
V
ss
DQ16
DQ15
DQ14
DQ12
DQ11
DQ10
DQ9
V
REF
CLK
A12
A11
A8
A5
V
SS
DQ17
V
ss
Q
V
DD
Q
DQ13
V
ss
Q
V
DD
Q
V
ss
Q
DS
V
ss
CLK
PD
A9
A7
A6
A4
DQ0
V
DD
Q
V
ss
Q
DQ4
V
DD
Q
V
ss
Q
V
DD
Q
QS
V
DD
FN
CS
BA1
A0
A2
A3
V
DD
DQ1
DQ2
DQ3
DQ5
DQ6
DQ7
DQ8
A14
A13
NC
BA0
A10
A1
V
DD
1
2
3
4
5
6
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
K4C89183AF
- 6 -
REV. 0.7 Jan. 2005
Block Diagram
CLK
CLK
PD
DLL
CLOCK
BUFFER
COMMAND
DECODER
CS
FN
CONTROL
GENERATOR
SIGNAL
ADDRESS
BUFFER
MODE
REGISTER
UPPER ADDRESS
LATCH
LOWER ADDRESS
LATCH
COLUMN DECODER
R
O
W DE
CODER
BANK #3
BANK #2
BANK #1
BANK #0
MEMORY
CELL
ARRAY
DA
T
A
C
O
NTR
O
L AND LA
TCH
C
I
RC
UI
T
BURST
COUNTER
READ
DATA
BUFFER
WRITE
DATA
BUFFER
DQ BUFFER
A0 ~ A14
BA0, BA1
REFRESH
COUNTER
WRITE ADDRESS
LATCH
ADDRESS
COMPARATOR
DS
DQ0 ~ DQ17
To Each Block
Note : The K4C89183AD configuration is 4 Bank of 32768 x 128 x 18 of cell array with the DQ pins numbered DQ0~DQ17.
QS
K4C89183AF
- 7 -
REV. 0.7 Jan. 2005
Absolute Maximum Ratings
Caution : Conditions outside the limits listed under "ABSOLUTE MAXIMUM RATINGS" may cause permanent damage to the device.
The device is not meant to be operated under conditions outside the limits described in the operational section of this specifi-
cation. Exposure to "ABSOLUTE MAXIMUM RATINGS" conditions for extended periods may affect device reliability.
Recommended DC,AC Operating Conditions (Notes : 1)
(Tcase = 0 ~ 85
O
C)
Symbol
Parameter
Rating
Units
Notes
V
DD
Power Supply Voltage
-0.3 ~ 3.3
V
V
DDQ
Power Supply Voltage (for I/O buffer)
-0.3 ~ V
DD
+ 0.3
V
V
IN
Input Voltage
-0.3 ~ V
DD
+ 0.3
V
V
OUT
DQ pin Voltage
-0.3 ~ V
DDQ
+ 0.3
V
V
REF
Input Reference Voltage
-0.3 ~ V
DDQ
+ 0.3
V
T
OPR
Operating Temperature
0 ~ 85
O
C
Case Temp.
T
STG
Storage Temperature
-55 ~ 150
O
C
T
SOLDER
Soldering Temperature(10s)
260
O
C
P
D
Power Dissipation
2
W
I
OUT
Short Circuit Output Current
50
mA
Symbol
Parameter
Min
Typ
Max
Units
Notes
V
DD
Power Supply Voltage
2.375
2.5
2.625
V
V
DDQ
Power Supply Voltage (for I/O Buffer)
1.7
1.8
1.9
V
V
REF
Input Reference Voltage
V
DDQ
/2x95%
V
DDQ
/2
V
DDQ
/2x105%
V
2
V
IH
(DC)
Input DC high Voltage
V
REF
+0.125
-
V
DDQ
+0.2
V
5
V
IL
(DC)
Input DC Low Voltage
-0.1
-
V
REF
-0.125
V
5
V
ICK
(DC)
Differential Clock DC Input Voltage
-0.1
-
V
DDQ
+0.1
V
10
V
ID
(DC)
Input Differential Voltage. CLK and CLK Inputs (DC)
0.4
-
V
DDQ
+0.2
V
7,10
V
IH
(AC)
Input AC High Voltage
V
REF
+0.2
-
V
DDQ
+0.2
V
3,6
V
IL
(AC)
Input AC Low Voltage
-0.1
-
V
REF
-0.2
V
4,6
V
ID
(AC)
Input Differential Voltage. CLK and CLK Inputs (AC)
0.55
-
V
DDQ
+0.2
V
7,10
V
X
(AC)
Differential AC Input Cross Point Voltage
V
DDQ
/2-0.125
-
V
DDQ
/2+0.125
V
8,10
V
ISO
(AC)
Differential Clock AC Middle Level
V
DDQ
/2-0.125
-
V
DDQ
/2+0.125
V
9,10
K4C89183AF
- 8 -
REV. 0.7 Jan. 2005
1. All voltages are referenced to Vss, VssQ.
2. V
REF
is expected to track variations in VddQ DC level of the transmitting device.
Peak to peak AC noise on V
REF
may not exceed 2% of V
REF
(DC).
3. Overshoot Iimit : V
IH
(max.) = VddQ + 0.7V with a pulse width <= 5ns
4. Undershoot Iimit : V
IL
(min.) = -0.7V with a pulse width <= 5ns
5. V
IH
(DC) and V
IL
(DC) are levels to maintain the current logic state.
6. V
IH
(AC) and V
IL
(AC) are levels to change to the new logic state.
7. V
ID
is magnitude of the difference between CLK input level and CLK input level.
8. The value of Vx(AC) is expected to equal VddQ/2 of the transmitting device.
9. V
ISO
means [V
ICK
(CLK) + V
ICK
(CLK)]/2
10. Refer to the figure below.
Notes
:
11. In the case of external termination, VTT(Termination Voltage) should be gone in the range of V
REF
(DC) 0.04V.
Pin Capacitance
(V
DD
= 2.5V, V
DDQ
= 1.8V, f = 1 MHz, Ta = 25
o
C)
Note : These parameters are periodically sampled and not 100% tested.
Symbol
Parameter
Min
Max
Delts
Units
C
IN
Input Pin Capacitance
1.5
3.0
0.25
pF
C
INC
Clock Pin (CLK, CLK) Capacitance
1.5
3.0
0.25
pF
C
I/O
DQ, DS, QS Capacitance
2.5
3.5
0.5
pF
C
NC
NC Pin Capacitance
-
1.5
-
pF
CLK
CLK
V
SS
V
ID
(AC)
0 V Differential
V
ISO
V
SS
V
ICK
V
ISO
(min)
V
X
V
X
V
X
V
X
V
ICK
V
ICK
V
ICK
V
ISO
(max)
V
X
V
ID
(AC)
K4C89183AF
- 9 -
REV. 0.7 Jan. 2005
DC Characteristics and Operating Conditions
(VDD = 2.5V 0.125V, VDDQ = 1.8V 0.1V, Tcase = 0~85
C)
Parameter
Symbol
Max
Units
Notes
F6
FB
F5
Operating Current
One bank Read or Write operation;
t
CK
= min, I
RC
= min, I
OUT
= 0mA;
Burst Length = 4, CAS Latency = 6, Free running QS mode;
0V
V
IN
V
IL(AC)
(max.), V
IH(AC)
(min.)
V
IN
V
DDQ;
Address inputs change up to 2 times during minimum I
RC
,
Read data change twice per clock cycle
I
DD1S
320
300
280
mA
1, 2
Standby Current
All Banks : inactive state;
t
CK
=min, CS = V
IH
, PD = V
IH
;
0V
V
IN
V
IL
(AC)(max.), V
IH
(AC)(min.)
V
IH
V
DDQ;
Other input signals change one time during 4*t
CK,
DQ and DS inputs change twice per clock cycle
I
DD2N
100
95
90
1
Standby (Power Down) Current
All Banks : inactive state;
t
CK
=min, PD = V
IL
(Power Down);
CAS Latency = 6, Free running QS mode;
0V
V
IN
V
IL
(AC)(max), V
IH
(AC)(min)
V
IN
V
DDQ
;
Other input signals change one time during 4*t
CK
,
DQ and DS inputs are floating(V
DDQ
/2)
I
DD2P
70
65
60
1
Write Operating Current(4 Banks)
4 Bank intereaved continuous burst write operation;
t
CK
= min, I
RC
= min;
Burst Length = 4, CAS Latency = 6, Free running QS mode;
0V
V
IN
V
IL
(AC) (max.), V
IH
(AC)(min.)
V
IN
V
DDQ;
Address inputs change once per clock cycle,
DQ and DS inputs change twice per clock cycle
I
DD4W
650
600
550
1
Read Operating Current(4 Banks)
4 Bank intereaved continuous burst write operation;
t
CK
= min, I
RC
= min, I
OUT
= 0mA;
Burst Length = 4, CAS Latency = 6, Free running QS mode;
0V
V
IN
V
IL
(AC) (max.), V
IH
(AC)(min.)
V
IN
V
DDQ;
Address inputs change once per clock cycle,
Read data change twice per clock cycle
I
DD4R
650
600
550
1,2
Burst Auto-Refresh Current
Refresh command at every I
REFC
interval;
t
CK
= min, I
REFC
= min;
CAS Latency = 6, Free running QS mode;
0V
V
IN
V
IL
(AC) (max.), V
IH
(AC) (min.)
V
IN
V
DDQ;
Address change up to 2 times during minimum I
REFC
,
DQ and DS inputs change twice per clock cycle
I
DD5B
250
235
210
1,3
K4C89183AF
- 10 -
REV. 0.7 Jan. 2005
DC Characteristics and Operating Conditions
(VDD = 2.5V 0.125V, VDDQ = 1.8V 0.1V, Tcase = 0~85
C)
Notes : 1. These parameters depend on the cycle rate and these values are measured at a cycle rate with the minimum values of
t
CK
, t
RC
and I
RC
.
2. These parameters depend on the output loading. The specified values are obtained with the output open.
3. I
DD5B
is specified under burst refresh condition. Actual system should use distributed refresh that meet to t
REFI
specification
4. Refer to output driver characteristics for the detail. Output Driver Strength is selected by Extended Mode Register.
Parameter
Symbol
Min
Max
Unit
Notes
Input Leakage Current (0V<=V
IN
<=VddQ, All other pins not under test = 0V)
I
LI
-5
5
uA
Output Leakage Current (Output disabled, 0V<=V
OUT
<=VddQ)
I
LO
-5
5
uA
V
REF
Current
I
REF
-5
5
uA
Normal Output
Driver
Output DC Current
(V
DDQ
= 1.7 ~ 1.9V)
V
OH
= 1.420V
I
OH
(DC)
-5.6
-
mA
4
V
OL
= 0.280V
I
OL
(DC)
5.6
-
4
Strong Output
Driver
V
OH
= 1.420V
I
OH
(DC)
-9.8
-
4
V
OL
= 0.280V
I
OL
(DC)
9.8
-
4
Weak Output
Driver
V
OH
= 1.420V
I
OH
(DC)
-2.8
-
4
V
OL
= 0.280V
I
OL
(DC)
2.8
-
Normal Output
Driver
Output DC Current
(V
DDQ
= 1.4 ~ 1.6V)
V
OH
= V
DDQ
- 0.4
I
OH
(DC)
-4
-
mA
3
V
OL
= 0.4V
I
OL
(DC)
-4
-
3
Strong Output
Driver
V
OH
= V
DDQ
- 0.4
I
OH
(DC)
-8
-
3
V
OL
= 0.4V
I
OL
(DC)
-8
-
3
Weak Output
Driver
Not defined
I
OH
(DC)
-
-
Not defined
I
OL
(DC)
-
-
K4C89183AF
- 11 -
REV. 0.7 Jan. 2005
AC Characteristics and Operating Conditions (Notes : 1, 2)
Symbol
Parameter
F6
FB
F5
Units Notes
Min
Max
Min
Max
Min
Max
t
RC
Random Cycle Time
20.0
-
22.5
-
25
-
ns
3
t
CK
Clock Cycle Time
C
L
= 4
4.0
6.0
4.5
6.0
5.0
6.0
3
C
L
= 5
3.33
6.0
3.75
6.0
4.5
6.0
3
C
L
= 6
3.0
6.0
3.33
6.0
4.0
6.0
3
t
RAC
Random Access Time
-
20.0
-
22.5
-
25
3
t
CH
Clock High Time
0.45*t
CK
-
0.45*t
CK
-
0.45*t
CK
-
3
t
CL
Clock Low Time
0.45*t
CK
-
0.45*t
CK
-
0.45*t
CK
-
3
t
CKQS
QS Access Time from CLK
-0.45
0.45
-0.45
0.45
-0.5
0.5
3, 8
t
QSQ
Data Output Skew from QS
-
0.2
-
0.25
-
0.3
4
t
AC
Data Access Time from CLK
-0.5
0.5
-0.5
0.5
-0.6
0.6
3, 8
t
OH
Data Output Hold Time from CLK
-0.5
0.5
-0.5
0.5
-0.6
0.6
3, 8
t
HP
CLK half period ( minium of Actual t
CH
, t
CL
)
min(t
CH
,
t
CL
)
-
min(t
CH
,
t
CL
)
-
min(t
CH
,
t
CL
)
-
3
t
QSP
QS(Read) Pulse Width
t
HP
-
t
QHS
-
t
HP
-
t
QHS
-
t
HP
-
t
QHS
-
4, 8
t
QSQV
Data Output Valid Time from QS
t
HP
-
t
QHS
-
t
HP
-
t
QHS
-
t
HP
-
t
QHS
-
4, 8
t
QHS
DQ, QS Hold skew factor
-
0.055x
t
CK
+0.17
-
0.055x
t
CK
+0.17
-
0.055x
t
CK
+0.17
t
DQSS
DS(Write) Low to High Setup Time
0.8*t
CK
1.2*t
CK
0.8*t
CK
1.2*t
CK
0.8*t
CK
1.2*t
CK
3
t
DSPRE
DS(Write) Preamble Pulse Width
0.4*t
CK
-
0.4*t
CK
-
0.4*t
CK
-
4
t
DSPRES
DS First Input Setup Time
0
-
0
-
0
-
3
t
DSPREH
DS First Low Input Hold Time
0.3*t
CK
-
0.3*t
CK
-
0.3*t
CK
-
3
t
DSP
DS High or Low Input Pulse Width
0.45*t
CK
0.55*t
CK
0.45*t
CK
0.55*t
CK
0.45*t
CK
0.55*t
CK
4
t
DSS
DS Input Falling Edge to Clock Setup
Time
C
L
= 4
0.75
-
0.8
-
1.0
-
3, 4
C
L
= 5
0.75
-
0.8
-
1.0
-
3, 4
C
L
= 6
0.75
-
0.8
-
1.0
-
3, 4
C
L
= 7
-
-
-
-
-
-
3, 4
t
DSPST
DS(Write) Postamble Pulse Width
0.45*t
CK
-
0.45*t
CK
0.45*t
CK
-
4
t
DSPSTH
DS(Write) Postamble Hold Time
C
L
= 4
0.75
-
0.8
-
1.0
-
3, 4
C
L
= 5
0.75
-
0.8
-
1.0
-
3, 4
C
L
= 6
0.75
-
0.8
-
1.0
3, 4
C
L
= 7
-
-
-
-
-
-
3, 4
t
DS
Data Input Setup Time from DS
0.3
-
0.35
-
0.4
-
4
t
DH
Data Input Hold Time from DS
0.3
-
0.35
-
0.4
-
4
t
IS
Command / Address Input Setup Time
0.6
-
0.6
-
0.7
-
3
t
IH
Command / Address Input Hold Time
0.6
-
0.6
-
0.7
-
3
K4C89183AF
- 12 -
REV. 0.7 Jan. 2005
AC Characteristics and Operating Conditions (Notes : 1, 2) (Continued)
Symbol
Parameter
F6
FB
F5
Units Notes
Min
Max
Min
Max
Min
Max
t
LZ
Data-out Low Impedance Time from CLK
-0.5
-
-0.5
-
-0.6
-
3, 6, 8
t
HZ
Data-out High Impedance Time from CLK
-
0.5
-
0.5
-
0.6
3, 7, 8
t
QPDH
Last Output to PD High Hold Time
0
-
0
-
0
-
t
PDEX
Power Down Exit Time
0.6
-
0.6
-
0.7
-
3
t
T
Input Transition Time
0.1
1
0.1
1
0.1
1
t
FPDL
PD Low Input Window for Self-Refresh Entry
-0.5*t
CK
5
-0.5*t
CK
5
-0.5*t
CK
5
3
t
REFI
Auto-Refresh Average Interval
0.4
3.9
0.4
3.9
0.4
3.9
us
5
t
PAUSE
Pause Time after Power-up
200
-
200
-
200
-
I
RC
Random Read/Write Cycle Time
(Applicable to Same Bank)
C
L
= 4
5
-
5
-
5
-
Cycle
C
L
= 5
6
-
6
-
6
-
C
L
= 6
7
-
7
-
7
-
C
L
= 7
-
-
-
-
-
-
I
RCD
RDA/WRA to LAL Command Input Delay
(Applicable to Same Bank)
1
1
1
1
1
1
I
RAS
LAL to RDA/WRA Command Input Delay
(Applicable to Same Bank)
C
L
= 4
4
-
4
-
4
-
C
L
= 5
5
-
5
-
5
-
C
L
= 6
6
-
6
-
6
-
C
L
= 7
-
-
-
-
-
-
I
RBD
Random Bank Access Delay
(Applicable to Other Bank)
2
-
2
-
2
-
I
RWD
LAL following RDA to WRA Delay
(Applicable to Other Bank)
BL = 4
3
-
3
-
3
-
I
WRD
LAL following WRA to RDA Delay
(Applicable to Other Bank)
1
-
1
-
1
-
I
RSC
Mode Register Set Cycle Time
C
L
= 4
7
-
7
-
7
-
C
L
= 5
7
-
7
-
7
-
C
L
= 6
7
-
7
-
7
-
C
L
= 7
I
PD
PD Low to Inactive State of Input Buffer
-
2
-
2
-
2
I
PDA
PD High to Active State of Input Buffer
1
-
1
-
1
-
I
PDV
Power down mode valid from REF com-
mand
C
L
= 4
19
-
19
-
19
-
C
L
= 5
23
-
23
-
23
-
C
L
= 6
25
-
25
-
25
-
C
L
= 7
I
REFC
Auto-Refresh Cycle Time
C
L
= 4
19
-
19
-
19
-
C
L
= 5
23
-
23
-
23
-
C
L
= 6
25
-
25
-
25
-
C
L
= 7
I
LOCK
DLL Lock-on Time (Applicable to RDA command)
200
-
200
-
200
-
K4C89183AF
- 13 -
REV. 0.7 Jan. 2005
AC Test Conditions
Symbol
Parameter
Value
Units
Notes
V
IH
(min)
Input high voltage (minimum)
V
REF
+ 0.2
V
V
IL
(max)
Input low voltage (maximum)
V
REF
- 0.2
V
V
REF
Input reference voltage
VddQ/2
V
V
TT
Termination voltage
V
REF
V
V
SWING
Input signal peak to peak swing
0.7
V
V
R
Differential clock input reference level
V
X(AC)
V
V
ID
(AC)
Input differential voltage
1.0
V
SLEW
Input signal minimum slew rate
2.5
V/ns
V
OTR
Output timing measurement reference voltage
VddQ/2
V
9
V
IH
min
(AC)
V
REF
V
IL
max
(AC)
V
SWING
VddQ
Vss
V
TT
Output
Slew=(V
IH
min
(AC)
- V
IL
max
(AC)
)/
T
T
T
Notes : 1. Transition times are measured between V
IH
min
(DC)
and V
IL
max
(DC)
.
Transition (rise and fall) of input signals have a fixed slope.
2. If the result of nominal calculation with regard to t
CK
contains more than
one decimal place, the result is rounded up to the nearest decimal place.
(i.e., t
DQSS
= 0.8*t
CK
, t
CK
= 3.3ns, 0.8*3.3 ns = 2.64 ns is rounded up to 2.7 ns.)
3. These parameters are measured from the differential clock (CLK and CLK) AC cross point.
4. These parameters are measured from signal transition point of DS crossing V
REF
level.
5. The t
REFI
(MAX.) applies to equally distributed refresh method.
The t
REFI
(MIN.) applies to both burst refresh method and distributed refresh method.
In such case, the average interval of eight consecutive Auto-Refresh commands has to be more than 400ns always. In
other words, the number of Auto- Refresh cycles which can be performed within 3.2us (8X400ns) is to 8 times in the
maximum.
6. Low Impedance State is speified at VddQ/2 0.2V from steady state.
7. High Impedance State is specified where output buffer is no longer driven.
8. These parameters depend on the clock jitter. These parameters are measured at stable clock.
9. Output timing is measured by using Normal driver strength at V
DDQ
= 1.7V ~ 1.9V.
Output timing is measured by using Strong driver strength at V
DDQ
= 1.4V ~ 1.6V
AC Test Load
25
Measurement Point
K4C89183AF
- 14 -
REV. 0.7 Jan. 2005
Power Up Sequence
1. As for PD, being maintained by the low state (<0.2V) is desirable before a power-supply injection.
2. Apply V
DD
before or at the same time as V
DDQ
.
3. Apply V
DDQ
before or at the same time as V
REF
.
4. Start clock (CLK, CLK) and maintain stable condition for 200us (min.).
5. After stable power and clock, apply DESL and take PD = H.
6. Issue EMRS to enable DLL and to define driver strength and data strobe type. (Note : 1)
7. Issue MRS for set CAS Latency (CL), Burst Type (BT), and Burst Length (BL). (Note : 1)
8. Issue two or more Auto-Refresh commands. (Note:1)
9. Ready for normal operation after 200 clocks from Extended Mode Register programming.
Note : 1. Sequence 6, 7 and 8 can be issued in random order.
2. L=Logic Low, H = Logic High
DESL
RDA MRS
DESL
RDA MRS
DESL WRA REF
WRA REF
DESL
DESL
EMRS
MRS
op-code
op-code
V
DD
V
DDQ
V
REF
CLK
CLK
PD
Command
Address
DQ
DS
200
s(min)
I
PDA
l
RSC
l
RSC
l
REFC
2.5V(TYP)
1.8V(TYP)
0.9V(TYP)
l
REFC
t
PDEX
200 clock cycle(min)
QS
EMRS
Hi-Z
QS
(Free Running mode)
(Uni-QS mode)
MRS
Auto Refresh cycle
Normal Operation
Low
K4C89183AF
- 15 -
REV. 0.7 Jan. 2005
t
CK
t
CK
t
CH
t
CL
t
IS
t
IH
t
IPW
1st
t
IS
t
IH
2nd
t
IS
t
IH
1st
t
IS
t
IH
2nd
t
IPW
t
IS
t
IH
UA, BA
t
IS
t
IH
LA
t
DS
t
DH
CLK
CK
CS
FN
A0-A14
BA0.BA1
DS
DQn (Input)
~~
Basic Timing Diagrams
Timing of the CLK, CLK
Input Timing
t
CH
t
CL
t
CK
t
T
t
T
V
IH
V
IH(AC)
V
IL(AC)
V
IL
CLK
CLK
CLK
V
IH
V
IL
V
ID(AC)
CK
V
X
V
X
V
X
~~
~~
~~
~~
~~
~~
~~
~~
~~
Command and Address
t
DH
t
DS
t
DS
t
DH
DQm (Input)
~~
~~
t
DH
t
DS
Data
Refer to the Command Truth Table.
K4C89183AF
- 16 -
REV. 0.7 Jan. 2005
Q0
LAL(after RDA)
t
IS
t
IH
t
CH
t
CL
t
CK
t
CKQS
t
CKQS
t
QSP
t
QSP
t
CKQS
t
QSQ
t
LZ
t
QSQV
t
AC
t
QSQV
t
QSQ
t
HZ
t
QSQ
Low
High-Z
CK
CK
Input
(Control &
Addresses)
CAS latency = 4
LQS/UQS
(Output)
DQ
(Output)
Read Timing (Burst Length = 4)
Low
DESL
LDS/UDS
(Input)
Q1
Q2
Q3
t
AC
t
AC
t
OH
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Q0
t
CKQS
t
CKQS
t
QSP
t
QSP
t
CKQS
t
QSQ
t
LZ
t
QSQV
t
AC
t
QSQV
t
QSQ
t
HZ
t
QSQ
Low
High-Z
CAS latency = 5
LQS/UQS
(Output)
DQ
(Output)
Low
Q1
Q2
Q3
t
AC
t
AC
t
OH
Note : DQ0 to DQ17 are aligned with LQS.
Unidirectional DS/QS mode
DQ18 to DQ35 are aligned with UQS.
Q0
t
CKQS
t
CKQS
t
QSP
t
QSP
t
CKQS
t
QSQ
t
LZ
t
QSQV
t
AC
t
QSQV
t
QSQ
t
HZ
t
QSQ
Low
High-Z
CAS latency = 6
LQS/UQS
(Output)
DQ
(Output)
Low
Q1
Q2
Q3
t
AC
t
AC
t
OH
K4C89183AF
- 17 -
REV. 0.7 Jan. 2005
Q0
LAL(after RDA)
t
IS
t
IH
t
CH
t
CL
t
CK
t
CKQS
t
CKQS
t
QSP
t
QSP
t
CKQS
t
QSQ
t
LZ
t
QSQV
t
AC
t
QSQV
t
QSQ
t
HZ
t
QSQ
High-Z
CK
CK
Input
(Control &
Addresses)
CAS latency = 4
LQS/UQS
(Output)
DQ
(Output)
Read Timing (Burst Length = 4)
DESL
LDS/UDS
(Input)
Q1
Q2
Q3
t
AC
t
AC
t
OH
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Q0
t
CKQS
t
CKQS
t
QSP
t
QSP
t
CKQS
t
QSQ
t
LZ
t
QSQV
t
AC
t
QSQV
t
QSQ
t
HZ
t
QSQ
High-Z
CAS latency = 5
LQS/UQS
(Output)
DQ
(Output)
Q1
Q2
Q3
t
AC
t
AC
t
OH
Note : DQ0 to DQ17 are aligned with LQS.
LQS/UQS is always asserted in Free Running QS mode.
Unidirectional DS/Free Running QS mode
DQ18 to DQ35 are aligned with UQS.
Q0
t
CKQS
t
CKQS
t
QSP
t
QSP
t
CKQS
t
QSQ
t
LZ
t
QSQV
t
AC
t
QSQV
t
QSQ
t
HZ
t
QSQ
High-Z
CAS latency = 6
LQS/UQS
(Output)
DQ
(Output)
Q1
Q2
Q3
t
AC
t
AC
t
OH
K4C89183AF
- 18 -
REV. 0.7 Jan. 2005
t
DSPSTH
LAL(after RDA)
t
IS
t
IH
t
CH
t
CL
t
CK
CK
CK
Input
(Control &
Addresses)
Write Timing (Burst Length = 4)
DESL
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Q0
t
DSP
t
DQSS
t
DSP
t
DSP
t
DSS
t
DH
Q1
Q2
Q3
t
DSPRES
t
DSPREH
t
DSPST
t
DSS
t
DSPSTH
Postamble
Preamble
t
DSPRE
t
DS
t
DS
t
DH
t
DQSS
t
DH
t
DS
CAS latency = 4
LDS/UDS
(Input)
DQ
(Input)
Q0
t
DSP
t
DSP
t
DSP
t
DH
Q1
Q2
Q3
t
DSPRES
t
DSPREH
t
DSPST
t
DSS
Postamble
Preamble
t
DSPRE
t
DS
t
DS
t
DH
t
DH
t
DS
CAS latency = 5
LDS/UDS
(Input)
DQ
(Input)
t
DSS
LQS/UQS
(Uni-QS)
LQS/UQS
(Free Runninig)
Low
Unidirectional DS/QS mode, Unidirectional DS/Free Running QS mode
Note : DQ0 to DQ17 are sampled at both edges of LDS.
DQ18 to DQ35 are sampled at both edges of UDS.
t
DSPSTH
t
DQSS
Q0
t
DSP
t
DSP
t
DSP
t
DH
Q1
Q2
Q3
t
DSPRES
t
DSPREH
t
DSPST
t
DSS
Postamble
Preamble
t
DSPRE
t
DS
t
DS
t
DH
t
DH
t
DS
CAS latency = 6
LDS/UDS
(Input)
DQ
(Input)
t
DSS
K4C89183AF
- 19 -
REV. 0.7 Jan. 2005
Command
CLK
CLK
Input
(Control &
Addresses)
t
IS
t
IH
t
REFI
, t
PAUSE
, Ixxxx Timing
t
IS
t
IH
Command
t
REFI,
t
PAUSE,
I
XXXX
Note. "
I
XXXX
"means "
I
RC
", "
I
RCD
", "
I
RAS
", etc.
~ ~
~ ~
K4C89183AF
- 20 -
REV. 0.7 Jan. 2005
Function Truth Table (Notes : 1,2,3)
Command Truth Table (Notes : 4)
The First Command
Symbol
Function
CS
FN
BA1-BA0
A14-A9
A8
A7
A6-A0
DESL
Device Deselect
H
X
X
X
X
X
X
RDA
Read with Auto-close
L
H
BA
UA
UA
UA
UA
WRA
Write with Auto-close
L
L
BA
UA
UA
UA
UA
The Second Command (The next clock of RDA or WRA command)
Notes : 1. L = Logic Low, H = Logic High, X = either L or H, V = Valid (Specified Value), BA = Bank Address, UA = Upper Address,
LA = Lower Address.
2. All commands are assumed to issue at a valid state.
3. All inputs for command (excluding SELFX and PDEX) are latched on the crossing point of differential clock input where
CLK goes to High.
4. Operation mode is decided by the comination of 1st command and 2nd command refer to "STATE DIAGRAM" and the
command table below.
Symbol
Function
CS
FN
BA1-BA0 A14-A13 A12-A11 A10-A9
A8
A7
A6-A0
LAL
Lower Address Latch
H
X
X
V
X
X
X
X
LA
REF
Auto-Refresh
L
X
X
X
X
X
X
X
X
MRS
Mode Register Set
L
X
V
L
L
L
L
V
V
Read Command Table
Command (Symbol)
CS
FN
BA1-BA0
A14-A9
A8
A7
A6-A0
Notes
RDA (1st)
L
H
BA
UA
UA
UA
UA
LAL (2nd)
H
X
X
X
X
X
LA
Write Command Table
Notes : 5. A14~A13 are used for Variable Write Length (VW) control at Write Operation.
Command (Symbol)
CS
FN
BA1-
BA0
A14
A13
A12
A11
A10~
A9
A8
A7
A6-A0
WRA (1st)
L
L
BA
UA
UA
UA
UA
UA
UA
UA
UA
LAL (2nd)
H
X
X
VW0
VW1
X
X
X
X
X
LA
VW Truth Table
Function
VW0
VW1
BL = 4
Reserved
L
L
Write All Words
H
L
Write First Two Words
L
H
Write First One Word
H
H
K4C89183AF
- 21 -
REV. 0.7 Jan. 2005
Auto-Refresh Command Table
Function
Command
(Symbol)
Current
State
PD
CS
FN
BA1-BA0 A14-A9
A8
A7
A6-A0
Notes
n-1
n
Active
WRA(1st)
Standby
H
H
L
L
X
X
X
X
X
Auto-Refresh
REF(2nd)
Active
H
H
L
X
X
X
X
X
X
Power Down Table
Notes : 7. PD has to be brought to Low within t
FPDL
from REF command.
8. PD should be brought to Low after DQ's state turned high impedance.
9. When PD is brought to High from Low, this function is executed asynchronously.
Function
Command
(Symbol)
Current
State
PD
CS
FN
BA1-
BA0
A14-A9 A8
A7 A6-A0 Notes
n-1
n
Power Down Entry
PDEN
Standby
H
L
H
X
X
X
X
X
X
8
Power Down Continue
-
Power Down
L
L
X
X
X
X
X
X
X
Power Down Exit
PDEX
Power Down
L
H
H
X
X
X
X
X
X
9
Mode Register Set Command Truth Table
Note : 6. Refer to "Mode Register Table".
Command (Symbol)
CS
FN
BA1-BA0
A14-A9
A8
A7
A6-A0
Notes
RDA (1st)
L
H
X
X
X
X
X
MRS (2nd)
L
X
V
L
L
V
V
6
Function Truth Table (Continued)
K4C89183AF
- 22 -
REV. 0.7 Jan. 2005
Function Truth Table (Continued)
Notes : 10. Illegal if any bank is not idle.
11. Illegal to bank in specified states : Function may be Legal in the bank indicated by bank Address (BA).
12. Illegal if t
FPDL
is not Stisfied.
Current State
PD
CS
FN
Address
Command
Action
Notes
n-1
n
Idle
H
H
H
X
X
DESL
NOP
H
H
L
H
BA, UA
RDA
Row activate for Read
H
H
L
L
BA, UA
WRA
Row activate for Write
H
L
H
X
X
PDEN
Power Down Entry
10
H
L
L
X
X
-
Illegal
L
X
X
X
X
-
Refer to Power Down state
Row Active for Read
H
H
H
X
LA
LAL
Begin read
H
H
L
X
Op-Code
MRS/EMRS Access to Mode Register
H
L
H
X
X
PDEN
Illegal
H
L
L
X
X
MRS/EMRS Illegal
L
X
X
X
X
-
Invalid
Row Active for Write
H
H
H
X
LA
LAL
Begin Write
H
H
L
X
X
REF
Auto-Refresh
H
L
H
X
X
PDEN
Illegal
H
L
L
X
X
REF (Self)
Self-Refresh entry
L
X
X
X
X
-
Invalid
Read
H
H
H
X
X
DESL
Continue burst read to end
H
H
L
H
BA, UA
RDA
Illegal
11
H
H
L
L
BA, UA
WRA
Illegal
11
H
L
H
X
X
PDEN
Illegal
H
L
L
X
X
-
Illegal
L
X
X
X
X
-
Invalid
Write
H
H
H
X
X
DESL
Data write & continue burst write to end
H
H
L
H
BA, UA
RDA
Illegal
11
H
H
L
L
BA, UA
WRA
Illegal
11
H
L
H
X
X
PDEN
Illegal
H
L
L
X
X
-
Illegal
L
X
X
X
X
-
Invalid
Auto-Refreshing
H
H
H
X
X
DESL
NOP-> Idle after I
REFC
H
H
L
H
BA, UA
RDA
Illegal
H
H
L
L
BA, UA
WRA
Illegal
H
L
H
X
X
PDEN
Self-Refresh entry
12
H
L
L
X
X
-
Illegal
L
X
X
X
X
-
Refer to Self-Refreshing state
Mode Register Accessing
H
H
H
X
X
DESL
Nop-> Idle after I
RSC
H
H
L
H
BA, UA
RDA
Illegal
H
H
L
L
BA, UA
WRA
Illegal
H
L
H
X
X
PDEN
Illegal
H
L
L
X
X
-
Illegal
L
X
X
X
X
-
Invalid
Power Down
H
X
X
X
X
-
Invalid
L
L
X
X
X
-
Maintain Power Down Mode
L
H
H
X
X
RDEX
Exit Power Down Mode->Idle after t
PDEX
L
H
L
X
X
-
Illegal
K4C89183AF
- 23 -
REV. 0.7 Jan. 2005
Mode Register Table
Regular Mode Register
(Notes : 1)
Address
BA1
*1
BA0
*1
A14-A8
A7
*3
A6-A4
A3
A2-A0
Register
0
0
0
TM
CL
BT
BL
A7
Test Mode (TE)
0
Regular (Default)
1
Test Mode Entry
A3
Burst Type (BT)
0
Sequential
1
Interleave
A6
A5
A4
CAS Latency (CL)
0
0
X
Reserved
*2
0
1
0
Reserved
*2
0
1
1
Reserved
*2
1
0
0
4
1
0
1
5
1
1
0
6
1
1
1
Reserved
*2
A2
A1
A0
Burst Length (BL)
0
0
0
Reserved
*2
0
0
1
Reserved
*2
0
1
0
4
0
1
1
Reserved
*2
1
X
X
Extended Mode Register (Notes : 4)
Address
BA1
*4
BA0
*4
A14-A7
A6~A5
A4-A3
A2~A1
A0
*5
Register
0
1
0
SS
DIC(QS)
DIC(DQ)
DS
QS
DQ
Output Driver Impedance Control
(DIC)
A4
A3
A2
A1
0
0
0
0
Normal Output Driver
0
1
0
1
Strong Output Driver
1
0
1
0
Weak Output Driver
1
1
1
1
Reserved
A0
DLL Switch (DS)
0
DLL Enable
1
DLL Disable
Note : 1. Regular Mode Register Is Chosen Using the combination of BA0 = 0 and BA1 = 0.
2. "Reserved" places in Regular Mode Register should not be set.
3. A7 in Regular Mode Register must be set to "0"(Low state).
Because Test Mode is specific mode for supplier.
4. Extended Mode Register is chosen using the Combination of BA0 = 1 and BA1 = 0.
5. A0 in Extended Mode Register must be set to "0" to enable DLL for normal operation.
A6
A5
Strobe Select
0
0
Reserved
*2
0
1
Reserved
*2
1
0
Unidirectional DS/QS
1
1
Unidirectional DS/Free Running QS
K4C89183AF
- 24 -
REV. 0.7 Jan. 2005
State Diagram
Power
Down
Standby
(Idle)
Mode
Register
Auto-
Refresh
Active
(Restore)
Active
Write
(Buffer)
Read
PDEX
(PD = H)
PD = H
LAL
LAL
REF
MRS
RDA
WRA
PDEN
(PD = L)
The second command at Active
state must be issued 1clock after
RDA or WRA command input
Command Input
Automatic Return
- 25 -
K4C89183AF
0
2
3
4
5
6
7
8
9
10
11
1
12
13
14
15
REV. 0.7 Jan. 2005
Timing Diagrams
Single Bank Read Timing (CL=4)
CLK
CLK
Command
Address
RDA
DESL
LAL
RDA
DESL
LAL
RDA
DESL
LAL
RDA
LA
UA
LA
UA
LA
UA
UA
#0
#0
#0
#0
Unidirectional DS/QS mode
Bank Add.
(Output)
QS
(Output)
DQ
(Input)
DS
Unidirectional DS/Free Running QS mode
Q0 Q1 Q2 Q3
Q0 Q1 Q2 Q3
Q0
Q0 Q1 Q2 Q3
Q0 Q1 Q2 Q3
Q0
l
RC
=5cycles
l
RC
=5cycles
l
RC
=5cycles
l
RCD
=1cycle
l
RAS
=4cycles
l
RCD
=1cycle
l
RAS
=4cycles
l
RCD
=1cycle
l
RAS
=4cycles
Low
CL=4
Hi-Z
CL=4
CL=4
CL=4
Hi-Z
CL=4
CL=4
(Output)
QS
(Output)
DQ
(Input)
DS
- 26 -
K4C89183AF
0
2
3
4
5
6
7
8
9
10
11
1
12
13
14
15
REV. 0.7 Jan. 2005
Single Bank Read Timing (CL=5)
Command
Address
RDA
DESL
LAL
#0
Unidirectional DS/QS mode
Bank Add.
Unidirectional DS/Free Running QS mode
Q0 Q1 Q2 Q3
Q0 Q1 Q2 Q3
l
RC
=6cycles
Low
Hi-Z
RDA
DESL
LAL
l
RC
=6cycles
RDA
DESL
LAL
UA
LA
l
RAS
=5cycles
l
RCD
=1cycle
l
RAS
=5cycles
l
RCD
=1cycle
UA
LA
l
RCD
=1cycle
UA
LA
#0
#0
CL=5
CL=5
Q0 Q1 Q2 Q3
Q0 Q1 Q2 Q3
Hi-Z
CL=5
CL=5
CLK
CLK
(Output)
QS
(Output)
DQ
(Input)
DS
(Output)
QS
(Output)
DQ
(Input)
DS
- 27 -
K4C89183AF
0
2
3
4
5
6
7
8
9
10
11
1
12
13
14
15
REV. 0.7 Jan. 2005
Single Bank Read Timing (CL=6)
Command
Address
RDA
DESL
LAL
#0
Unidirectional DS/QS mode
Bank Add.
Unidirectional DS/Free Running QS mode
Q0 Q1 Q2 Q3
Q0 Q1 Q2
l
RC
=7cycles
Low
Hi-Z
UA
LA
l
RAS
=6cycles
l
RCD
=1cycle
CL=6
CL=6
RDA
DESL
LAL
l
RC
=7cycles
RDA
LAL
UA
LA
l
RAS
=6cycles
l
RCD
=1cycle
UA
LA
#0
#0
Q0 Q1 Q2 Q3
Q0 Q1 Q2
Hi-Z
CL=6
CL=6
l
RCD
=1cycle
CLK
CLK
(Output)
QS
(Output)
DQ
(Input)
DS
(Output)
QS
(Output)
DQ
(Input)
DS
- 28 -
K4C89183AF
0
2
3
4
5
6
7
8
9
10
11
1
12
13
14
15
REV. 0.7 Jan. 2005
Single Bank Write Timing (CL=4)
Command
Address
WRA
DESL
LAL
WRA
DESL
LAL
WRA
DESL
LAL
WRA
LA
UA
LA
UA
LA
UA
UA
#0
#0
#0
#0
Unidirectional DS/QS mode
Bank Add.
Unidirectional DS/Free Running QS mode
(Output)
QS
(Input)
DQ
(Input)
DS
l
RC
=5cycles
l
RC
=5cycles
l
RC
=5cycles
l
RCD
=1cycle
l
RAS
=4cycles
l
RCD
=1cycle
l
RAS
=4cycles
l
RCD
=1cycle
l
RAS
=4cycles
(Output)
QS
(Input)
DQ
(Input)
DS
D0 D1
Low
WL=3
WL=3
D2 D3
D0 D1 D2 D3
WL=3
D0 D1 D2 D3
D0 D1
WL=3
WL=3
D2 D3
D0 D1 D2 D3
WL=3
D0 D1 D2 D3
CLK
CLK
- 29 -
K4C89183AF
0
2
3
4
5
6
7
8
9
10
11
1
12
13
14
15
REV. 0.7 Jan. 2005
Single Bank Write Timing (CL=5)
Command
Address
WRA
DESL
LAL
LA
UA
#0
Unidirectional DS/QS mode
Bank Add.
Unidirectional DS/Free Running QS mode
l
RC
=6cycles
l
RCD
=1cycle
l
RAS
=5cycles
(Output)
QS
(Input)
DQ
(Input)
DS
D0 D1
Low
D2 D3
WRA
DESL
LAL
l
RC
=6cycles
WRA
DESL
LAL
LA
UA
l
RCD
=1cycle
l
RAS
=5cycles
LA
UA
l
RCD
=1cycle
#0
#0
D0 D1 D2 D3
WL=4
WL=4
D0 D1 D2 D3
D0 D1 D2 D3
WL=4
WL=4
CLK
CLK
(Output)
QS
(Input)
DQ
(Input)
DS
- 30 -
K4C89183AF
0
2
3
4
5
6
7
8
9
10
11
1
12
13
14
15
REV. 0.7 Jan. 2005
Single Bank Write Timing (CL=6)
Command
Address
WRA
DESL
LAL
LA
UA
#0
Unidirectional DS/QS mode
Bank Add.
Unidirectional DS/Free Running QS mode
(Output)
QS
(Input)
DQ
(Input)
DS
l
RC
=7cycles
l
RCD
=1cycle
l
RAS
=6cycles
(Output)
QS
(Input)
DQ
(Input)
DS
D0 D1
Low
D2 D3
WRA
DESL
LAL
LA
UA
l
RC
=7cycles
l
RCD
=1cycle
l
RAS
=6cycles
WRA
LAL
LA
UA
l
RCD
=1cycle
#0
#0
D0 D1 D2 D3
WL=5
WL=5
D0 D1 D2 D3
D0 D1 D2 D3
WL=5
WL=5
CLK
CLK
- 31 -
K4C89183AF
0
2
3
4
5
6
7
8
9
10
11
1
12
13
14
15
REV. 0.7 Jan. 2005
Single Bank Read-Write Timing (CL=4)
Command
Address
RDA
DESL
LAL
WRA
DESL
LAL
RDA
DESL
LAL
WRA
LA
UA
LA
UA
LA
UA
UA
#0
#0
#0
#0
Unidirectional DS/QS mode
Bank Add.
Unidirectional DS/Free Running QS mode
(Output)
QS
DQ
(input)
DS
l
RC
=5cycles
l
RC
=5cycles
l
RC
=5cycles
(Output)
QS
DQ
(input)
DS
Q0 Q1 Q2 Q3
CL=4
CL=4
WL=3
Low
D0 D1 D2 D3
Q0
Q0 Q1 Q2 Q3
CL=4
CL=4
WL=3
D0 D1 D2 D3
Q0
Hi-Z
Hi-Z
CLK
CLK
- 32 -
K4C89183AF
0
2
3
4
5
6
7
8
9
10
11
1
12
13
14
15
REV. 0.7 Jan. 2005
Single Bank Read-Write Timing (CL=5)
Unidirectional DS/QS mode
Bank Add.
Unidirectional DS/Free Running QS mode
(Output)
QS
DQ
(input)
DS
(Output)
QS
DQ
(input)
DS
Q0 Q1 Q2 Q3
Low
D0 D1 D2 D3
Hi-Z
Command
Address
RDA
DESL
LAL
LA
UA
l
RC
=6cycles
WRA
DESL
LAL
l
RC
=6cycles
RDA
DESL
LAL
LA
UA
LA
UA
#0
#0
#0
CL=5
WL=4
Q0 Q1 Q2 Q3
D0 D1 D2 D3
Hi-Z
CL=5
WL=4
Read data
Write data
CLK
CLK
- 33 -
K4C89183AF
0
2
3
4
5
6
7
8
9
10
11
1
12
13
14
15
REV. 0.7 Jan. 2005
Single Bank Read-Write Timing (CL=6)
Unidirectional DS/QS mode
Unidirectional DS/Free Running QS mode
Q0 Q1 Q2 Q3
Low
D0 D1 D2 D3
Hi-Z
CL=6
WL=5
Read data
Write data
Command
Address
RDA
DESL
LAL
LA
UA
#0
Bank Add.
l
RC
=7cycles
WRA
DESL
LAL
LA
UA
l
RC
=7cycles
RDA
LAL
LA
UA
#0
#0
(Output)
QS
DQ
(input)
DS
(Output)
QS
DQ
(input)
DS
Q0 Q1 Q2 Q3
D0 D1 D2 D3
Hi-Z
CL=6
WL=5
CLK
CLK
- 34 -
K4C89183AF
0
2
3
4
5
6
7
8
9
10
11
1
12
13
14
15
REV. 0.7 Jan. 2005
Multiple Bank Read Timing (CL=4)
Unidirectional DS/QS mode
Unidirectional DS/Free Running QS mode
Command
Address
RDA
LAL
LA
UA
Bank
Bank Add.
RDA
LAL
DESL
RDA
LAL
RDA
LAL
RDA
LAL
RDA
LAL
RDA
LAL
RDA
LA
UA
LA
UA
LA
UA
LA
UA
LA
UA
LA
UA
UA
"a"
Bank
"b"
Bank
"a"
Bank
"b"
Bank
"c"
Bank
"d"
Bank
"a"
Bank
"b"
l
RBD
=2cycles
Qa0 Qa1
CL=4
Low
Hi-Z
(Output)
QS
DQ
(input)
DS
Qb0 Qb1
Qa0 Qa1
Qb0 Qb1
Qc0 Qc1
CL=4
(Output)
Qa2 Qa3
Qb2 Qb3
Qa2 Qa3
Qb2 Qb3
Qc2
Qa0 Qa1
CL=4
Hi-Z
(Output)
QS
DQ
(input)
DS
Qb0 Qb1
Qa0 Qa1
Qb0 Qb1
Qc0 Qc1
CL=4
(Output)
Qa2 Qa3
Qb2 Qb3
Qa2 Qa3
Qb2 Qb3
Qc2
l
RBD
=2cycles
l
RBD
=2cycles
l
RBD
=2cycles
l
RBD
=2cycles
l
RC
(Bank"a")=5cycles
l
RC
(Bank"b")=5cycles
CLK
CLK
Note : l
RC
to the same bank must be satisfied
- 35 -
K4C89183AF
0
2
3
4
5
6
7
8
9
10
11
1
12
13
14
15
REV. 0.7 Jan. 2005
Multiple Bank Read Timing (CL=5)
Unidirectional DS/QS mode
Unidirectional DS/Free Running QS mode
Command
Address
RDA
LAL
LA
UA
Bank
Bank Add.
RDA
LAL
DESL
RDA
LAL
RDA
LAL
RDA
LAL
RDA
LAL
RDA
LAL
LA
UA
LA
UA
LA
UA
LA
UA
LA
UA
LA
UA
"a"
Bank
"b"
Bank
"a"
Bank
"b"
Bank
"c"
Bank
"d"
Bank
"a"
l
RBD
=2cycles
Qa0 Qa1
Low
Hi-Z
(Output)
QS
DQ
(input)
DS
Qb0 Qb1
Qa0 Qa1
Qb0 Qb1
(Output)
Qa2 Qa3
Qb2 Qb3
Qa2 Qa3
Qb2
(Output)
QS
DQ
(input)
DS
(Output)
l
RBD
=2cycles
l
RBD
=2cycles
l
RBD
=2cycles
l
RBD
=2cycles
l
RC
(Bank"a")=6cycles
l
RC
(Bank"6")=6cycles
CL=5
CL=5
Qa0 Qa1
Hi-Z
Qb0 Qb1
Qa0 Qa1
Qb0 Qb1
Qa2 Qa3
Qb2 Qb3
Qa2 Qa3
Qb2
CL=5
CL=5
CLK
CLK
Note : l
RC
to the same bank must be satisfied
- 36 -
K4C89183AF
0
2
3
4
5
6
7
8
9
10
11
1
12
13
14
15
REV. 0.7 Jan. 2005
Multiple Bank Read Timing (CL=6)
Unidirectional DS/QS mode
Unidirectional DS/Free Running QS mode
Command
Address
RDA
LAL
LA
UA
Bank
Bank Add.
RDA
LAL
DESL
RDA
LAL
RDA
LAL
RDA
LAL
RDA
LAL
RDA
LA
UA
LA
UA
LA
UA
LA
UA
LA
UA
UA
"a"
Bank
"b"
Bank
"a"
Bank
"b"
Bank
"c"
Bank
"d"
Bank
"a"
l
RBD
=2cycles
Qa0 Qa1
Low
Hi-Z
(Output)
QS
DQ
(input)
DS
Qb0 Qb1
Qa0 Qa1
(Output)
Qa2 Qa3
Qb2 Qb3
Qa2
(Output)
QS
DQ
(input)
DS
(Output)
l
RBD
=2cycles
l
RBD
=2cycles
l
RBD
=2cycles
l
RBD
=2cycles
l
RC
(Bank"a")=7cycles
l
RC
(Bank"b")=7cycles
CL=6
CL=6
Qa0 Qa1
Hi-Z
Qb0 Qb1
Qa0 Qa1
Qa2 Qa3
Qb2 Qb3
Qa2
CL=6
CL=6
CLK
CLK
Note : l
RC
to the same bank must be satisfied
- 37 -
K4C89183AF
0
2
3
4
5
6
7
8
9
10
11
1
12
13
14
15
REV. 0.7 Jan. 2005
Multiple Bank Write Timing (CL=4)
Unidirectional DS/QS mode
Unidirectional DS/Free Running QS mode
Command
Address
WRA
LAL
LA
UA
Bank
Bank Add.
WRA
LAL
DESL
WRA
LAL
WRA
LAL
WRA
LAL
WRA
LAL
WRA
LAL
WRA
LA
UA
LA
UA
LA
UA
LA
UA
LA
UA
LA
UA
UA
"a"
Bank
"b"
Bank
"a"
Bank
"b"
Bank
"c"
Bank
"d"
Bank
"a"
Bank
"b"
l
RBD
=2cycles
Da0 Da1
Low
(Output)
QS
DQ
(input)
DS
Db0 Db1
Da0 Da1
Db0 Db1
Dc0 Dc1
(Input)
Da2 Da3
Db2 Db3
Da2 Da3
Db2 Db3
Dc2
(Output)
QS
DQ
(input)
DS
(Input)
l
RBD
=2cycles
l
RBD
=2cycles
l
RBD
=2cycles
l
RBD
=2cycles
l
RC
(Bank"a")=5cycles
l
RC
(Bank"b")=5cycles
Dc3 Dd0 Dd1
WL=3
WL=3
Da0 Da1
Db0 Db1
Da0 Da1
Db0 Db1
Dc0 Dc1
Da2 Da3
Db2 Db3
Da2 Da3
Db2 Db3
Dc2 Dc3 Dd0 Dd1
WL=3
WL=3
CLK
CLK
Note : l
RC
to the same bank must be satisfied
- 38 -
K4C89183AF
0
2
3
4
5
6
7
8
9
10
11
1
12
13
14
15
REV. 0.7 Jan. 2005
Multiple Bank Write Timing (CL=5)
Unidirectional DS/QS mode
Unidirectional DS/Free Running QS mode
Command
Address
Bank Add.
Da0 Da1
Low
(Output)
QS
DQ
(input)
DS
Db0 Db1
Da0 Da1
Db0 Db1
Dc0 Dc1
(input)
Da2 Da3
Db2 Db3
Da2 Da3
Db2 Db3
(Output)
QS
DQ
(input)
DS
(input)
WRA
LAL
LA
UA
Bank
WRA
LAL
DESL
WRA
LAL
WRA
LAL
WRA
LAL
WRA
LAL
WRA
LAL
LA
UA
LA
UA
LA
UA
LA
UA
LA
UA
LA
UA
"a"
Bank
"b"
Bank
"a"
Bank
"b"
Bank
"c"
Bank
"d"
Bank
"a"
l
RBD
=2cycles
l
RBD
=2cycles
l
RBD
=2cycles
l
RBD
=2cycles
l
RBD
=2cycles
l
RC
(Bank"a")=6cycles
l
RC
(Bank"b")=6cycles
WL=4
WL=4
Da0 Da1
Db0 Db1
Da0 Da1
Db0 Db1
Dc0 Dc1
Da2 Da3
Db2 Db3
Da2 Da3
Db2 Db3
WL=4
WL=4
Note :I
RC
to the same bank must be satisfied.
CLK
CLK
- 39 -
K4C89183AF
0
2
3
4
5
6
7
8
9
10
11
1
12
13
14
15
REV. 0.7 Jan. 2005
Multiple Bank Write Timing (CL=6)
Unidirectional DS/QS mode
Unidirectional DS/Free Running QS mode
Command
Address
Bank Add.
Da0 Da1
Low
(Output)
QS
DQ
(input)
DS
Db0 Db1
Da0 Da1
Db0 Db1
(input)
Da2 Da3
Db2 Db3
Da2 Da3
(Output)
QS
DQ
(input)
DS
(input)
WL=5
WL=5
Note :I
RC
to the same bank must be satisfied.
WRA
LAL
LA
UA
Bank
WRA
LAL
DESL
WRA
LAL
WRA
LAL
WRA
LAL
WRA
LAL
WRA
LA
UA
LA
UA
LA
UA
LA
UA
LA
UA
UA
"a"
Bank
"b"
Bank
"a"
Bank
"b"
Bank
"c"
Bank
"d"
Bank
"a"
l
RBD
=2cycles
l
RBD
=2cycles
l
RBD
=2cycles
l
RBD
=2cycles
l
RBD
=2cycles
l
RC
(Bank"a")=7cycles
l
RC
(Bank"a")=7cycles
Da0 Da1
Db0 Db1
Da0 Da1
Db0 Db1
Da2 Da3
Db2 Db3
Da2 Da3
WL=5
WL=5
CLK
CLK
- 40 -
K4C89183AF
0
2
3
4
5
6
7
8
9
10
11
1
12
13
14
15
REV. 0.7 Jan. 2005
WL=3
CL=4
Low
Unidirectional DS/QS mode
Da0 Da1
Qb0 Qb1
Hi-Z
Da2 Da3
Qb2 Qb3
Da0 Da1
Qb0 Qb1
Da2 Da3
Qb2 Qb3
Low
Da0 Da1
Qb0 Qb1
Hi-Z
Da2 Da3
Qb2 Qb3
Da0 Da1
Qb0 Qb1
Da2 Da3
Qb2 Qb3
Low
Da0 Da1
Qb0 Qb1
Hi-Z
Da2 Da3
Qb2 Qb3
Da0 Da1
Qb0 Qb1
Da2 Da3
WL=4
CL=5
WL=5
CL=6
CL =4
(Output)
QS
DQ
(Input)
DS
(Output)
CL =5
(Output)
QS
DQ
(Input)
DS
(Output)
CL =6
(Output)
QS
DQ
(Input)
DS
(Output)
Multiple Bank Read-Write Timing (BL=4)
Command
Address
WRA
LAL
LA
UA
Bank
Bank Add.
RDA
LAL
DESL
WRA
LAL
RDA
LAL
DESL
WRA
LAL
RDA
LAL
LA
UA
LA
UA
LA
UA
UA
UA
LA
LA
"a"
Bank
"b"
Bank
"c"
Bank
"d"
l
RBD
=2cycles
Bank
"a"
Bank
"b"
l
RC
(Bank"a")
l
RC
(Bank"a")
l
WRD
=1cycle
l
RWD
=3cycles
l
WRD
=1cycle
l
RWD
=3cycles
l
WRD
=1cycle
Note :I
RC
to the same bank must be satisfied.
CLK
CLK
- 41 -
K4C89183AF
0
2
3
4
5
6
7
8
9
10
11
1
12
13
14
15
REV. 0.7 Jan. 2005
Multiple Bank Read-Write Timing (BL=4)
Command
Address
WRA
LAL
LA
UA
Bank
Bank Add.
RDA
LAL
DESL
WRA
LAL
RDA
LAL
DESL
WRA
LAL
RDA
LAL
LA
UA
LA
UA
LA
UA
UA
UA
LA
LA
"a"
Bank
"b"
Bank
"c"
Bank
"d"
l
RBD
=2cycles
Bank
"a"
Bank
"b"
l
RC
(Bank"a")
l
RC
(Bank"a")
Unidirectional DS/Free Running QS mode
l
WRD
=1cycle
l
RWD
=3cycles
l
WRD
=1cycle
l
RWD
=3cycles
l
WRD
=1cycle
WL=3
CL=4
Da0 Da1
Qb0 Qb1
Hi-Z
Da2 Da3
Qb2 Qb3
Da0 Da1
Qb0 Qb1
Da2 Da3
Qb2 Qb3
Da0 Da1
Qb0 Qb1
Hi-Z
Da2 Da3
Qb2 Qb3
Da0 Da1
Qb0 Qb1
Da2 Da3
Qb2 Qb3
Da0 Da1
Qb0 Qb1
Hi-Z
Da2 Da3
Qb2 Qb3
Da0 Da1
Qb0 Qb1
Da2 Da3
WL=4
CL=5
WL=5
CL=6
Note :I
RC
to the same bank must be satisfied.
CLK
CLK
CL =4
(Output)
QS
DQ
(Input)
DS
(Output)
CL =5
(Output)
QS
DQ
(Input)
DS
(Output)
CL =6
(Output)
QS
DQ
(Input)
DS
(Output)
K4C89183AF
- 42 -
REV. 0.7 Jan. 2005
Write with Variable Write Length (VW) Control(CL=4)
Command
WRA
LAL
DESL
WRA
LAL
BL=2, SEQUENTIAL MODE
DESL
Address
UA
LA=#3
UA
VW=All
LA=#1
VW=1
Bank Add.
Bank
Bank
"a"
(Input)
DQ
(Input)
DS
D0 D1
D0
Lower Address #3 #2
#1 (#0)
Last one data is masked.
Command
WRA
LAL
DESL
WRA
LAL
BL=4, SEQUENTIAL MODE
DESL
Address
UA
LA=#3
UA
VW=All
LA=#1
VW=1
Bank Add.
Bank
"a"
(Input)
DQ
(Input)
DS
D0 D1
D0
Lower Address #3 #0 #1 #2
#1 (#2) (#3) (#0)
Last three data are masked.
Bank
"a"
DESL
WRA
LAL
UA
LA=#2
VW=2
Bank
"a"
D2 D3
D0 D1
#2 #3 (#0) (#1)
Last two data are masked.
Note : DS input must be continued till end of burst count even if some of laster data is masked.
0
2
3
4
5
6
7
8
9
10
11
1
12
13
14
15
CLK
CLK
VW0 = Low
VW1 = don't care
VW0 = High
VW1 = don't care
"a"
VW0 = High
VW1 = Low
VW0 = High
VW1 = High
VW0 = Low
VW1 = High
K4C89183AF
- 43 -
REV. 0.7 Jan. 2005
Power Down Timing (CL=4, BL=4)
Command
RDA
LAL
RDA
BL=2, SEQUENTIAL MODE
Address
UA
UA
DESL
or
WRA
LA
Unidirectional DS/Free Running QS mode
Unidirectional DS/QS mode
PD
t
IH
t
QPDH
t
PDEX
t
IS
I
PD
=2 cycle
I
RC(min),
t
REFI(max)
Q0 Q1
Low
Hi-Z
(Output)
QS
DQ
(input)
DS
(Output)
CL=4
Q2 Q3
Q0 Q1
Hi-Z
(Output)
QS
DC
(input)
DS
(Output)
CL=4
Q2 Q3
Hi-Z
Hi-Z
PD must be kept "High" level until end of Burst data output.
PD should be brought to "High" within t
REFI
(max.) to maintain the data written into cell.
In Power Down Mode, PD "Low" and a stable clock signal must be maintained.
When PD is brought to "High", a valid executable command may be applied I
PDA
cycles later.
Note :
Power Down Entry
Power Down Exit
0
2
3
4
5
6
7
8
9
10
n-1
1
n
n+1
n+2
n+3
CLK
CLK
Read cycle to Power Down Mode
DESL
I
PDA
K4C89183AF
- 44 -
REV. 0.7 Jan. 2005
Power Down Timing (CL=4, BL=4)
Command
WRA
LAL
Address
UA
DESL
LA
Unidirectional DS/Free Running QS mode
Unidirectional DS/QS mode
PD
t
IH
t
PDEX
t
IS
I
PD
=2 cycle
I
RC(min),
t
REFI(max)
Low
(Output)
QS
DC
(input)
DS
(Output)
WL=3
(Output)
QS
DC
(input)
DS
(Output)
D0 D1 D2 D3
WL=3
I
PD
=2 cycle
D0 D1 D2 D3
WL=3
PD must be kept "High" level until end of Burst data output.
PD should be brought to "High" within t
REFI
(max.) to maintain the data written into cell.
In Power Down Mode, PD "Low" and a stable clock signal must be maintained.
When PD is brought to "High", a valid executable command may be applied I
PDA
cycles later.
Note :
0
2
3
4
5
6
7
8
9
10
n-1
1
n
n+1
n+2
n+3
I
PDA
Write cycle to Power Down Mode
CLK
CLK
RDA
UA
or
WRA
DESL
K4C89183AF
- 45 -
REV. 0.7 Jan. 2005
0
2
3
4
5
6
7
8
9
10
11
1
12
13
14
15
Mode Register Set Timing (CL=4, BL=4)
Command
A14~A0
WRA
DESL
LAL
LA
UA
BA
BA0, BA1
RDA
DESL
MRS
l
RC
=7cycles
LAL
LA
UA
BA1="0"
BA
RDA
or
WRA
BA0="0"
(opcode)
Valid
From Write operation to Mode Register Set operation
Unidirectional DS/Free Running QS mode
(Output)
QS
DC
(input)
DS
(input)
(Output)
QS
DC
(input)
DS
Low
(Output)
QS
DC
(input)
DS
(Output)
QS
DC
(input)
DS
D0 D1 D2 D3
D0 D1 D2 D3
Unidirectional DS/QS mode
(input)
Note : Minimum delay from LAL following WRA to RDA of MRS operation is WL+BL/2.
CLK
CLK
WL + BL/2
K4C89183AF
- 46 -
REV. 0.7 Jan. 2005
Extended Mode Register Set Timing (CL=4, BL=4)
Command
A14~A0
WRA
DESL
LAL
LA
UA
BA
BA0, BA1
RDA
DESL
MRS
l
RC
=7cycles
LAL
LA
UA
BA1="0"
BA
RDA
or
WRA
BA0="0"
(opcode)
Valid
From Write operation to Extended Mode Register Set operation
When DQ strobe mode is changed by EMRS, QS output is invalid for I
RSC
period.
DLL switch in Extended Mode Register must be set to enable mode for normal operation.
DLL lock-on time is needed after initial EMRS operation. See Power Up Sequence.
Minimum delay from LAL following WRA to RDA of EMRS operation is WL+BL/2.
Note :
Unidirectional DS/Free Running QS mode
(Output)
QS
DC
(input)
DS
(input)
(Output)
QS
DQ
(input)
DS
Low
(Output)
QS
DQ
(input)
DS
(Output)
QS
(input)
DS
D0 D1 D2 D3
D0 D1 D2 D3
Unidirectional DS/QS mode
(input)
0
2
3
4
5
6
7
8
9
10
11
1
12
13
14
15
CLK
CLK
WL + BL/2
K4C89183AF
- 47 -
REV. 0.7 Jan. 2005
0
2
3
4
5
6
7
n-1
n
n+1
n+2
1
Auto-Refresh Timing (CL=4, BL=4)
RDA
LAL
DESL
WRA
REF
DESL
RDA
Bank,
LA
Command
Bank, Address
or
WRA
LAL or
MRS or
REF
UA
Q0 Q1 Q2 Q3
QS
(output)
DQ
(output)
Unidirectional DS/Free Running QS mode
CL=4
l
RC
=5cycles
l
REFC
=19cycles
l
RCD
=1cycle
l
RAS
=4cycles
l
RCD
=1cycle
Low
Hi-Z
Low
Hi-Z
RDA
LAL
DESL
WRA
REF
DESL
RDA
Bank,
LA
Command
Bank, Address
or
WRA
LAL or
MRS or
REF
UA
Q0 Q1 Q2 Q3
QS
(output)
DQ
(output)
CL=4
l
RC
=5cycles
l
REFC
=19cycles
l
RCD
=1cycles
l
RAS
=4cycles
l
RCD
=1cycles
Hi-Z
Hi-Z
In case of CL=4, I
REFC
must be meet 19 clock cycles.
When the Auto-Refresh operation is perfomed, the synthetic average interval of Auto-Refresh command
specified by t
REFI
must be satisfied.
t
REFI
is average interval time in 8 Refresh cycles that is sampled randomly.
Note :
Unidirectional DS/QS mode
WRA REF
WRA REF
WRA REF
WRA REF
WRA REF
t
1
t
2
t
3
t
7
t
8
8 Refresh cycle
Total time of 8 Refresh cycle
8
t
1
+t
2
+t
3
+t
4
+t
5
+t
6
+t
7
+t
8
8
=
t
REFI
=
t
REFI
is specified to avoid partly concentrated current of Refresh operation that is acivated
larger are than Read/Write operation.
CLK
CLK
CLK
CLK
CLK
K4C89183AF
- 48 -
REV. 0.7 Jan. 2005
Function Description
Network - DRAM
Network - DRAM is an acronym of Double Data Rate Network - DRAM.
Network - DRAM is competent to perform fast random core access, low latency and high-speed data transfer.
Pin Functions
Clock Inputs : CLK & CLK
The CLK and CLK inputs are used as the reference for synchronous operation. CLK is master clock input. The CS, FN and all
address input signals are sampled on the crossing of the positive edge of CLK and the negative edge of CLK. The QS and DQ output
data are aligned to the crossing point of CLK and CLK. The timing reference point for the differential clock is when the CLK and CLK
signals cross during a transition.
Power Down : PD
The PD input controls the entry to the Power Down or Self-Refresh modes. The PD input does not have a Clock Suspend function like
a CKE input of a standard SDRAMs, therefore it is illegal to bring PD pin into low state if any Read or Write operation is being per-
formed.
Chip Select & Function Control : CS & FN
The CS and FN inputs are a control signal for forming the operation commands on Network-DRAM. Each operation mode is decided
by the combination of the two consecutive operation commands using the CS and FN inputs.
Bank Addresses : BA0 & BA1
The BA0 and BA1 inputs are latched at the time of assertion of the RDA or WRA command and are selected the bank to be used for
the operation. BA0 and BA1 also define which mode register is loaded during the Mode Register Set command (MRS or EMRS).
Address Inputs : A0 to A14
Address inputs are used to access the arbitrary address of the memory cell array within each bank. The Upper Addresses with Bank
address are latched at the RDA or WRA command and the Lower Addresses are latched at the LAL command. The A0 to A14 inputs
are also used for setting the data in the Regular or Extended Mode Register set cycle.
BA0
BA1
Bank #0
0
0
Bank #1
1
0
Bank #2
0
1
Bank #3
1
1
Upper Address
Lower Address
K4C89183AF
A0 to A14
A0 to A6
K4C89183AF
- 49 -
REV. 0.7 Jan. 2005
Functional Description (Continued)
Data Input/Output : DQ0 ~ DQ17
The input data of DQ0 to DQ17 are taken in synchronizing with the both edges of DS input signal.
The output data of DQ0 to DQ17 are outputted synchronizing with the both edges of QS output signal.
Data Strobe : DS or QS
Method of data strobe is chosen by Extended mode register.
(1) Unidirectional DS/QS mode
DS is input signal and QS is output signal. Both edges of DS are used to sample all DQs at Write operation. Both edges of QS
are used for trigger signal of all DQs at Read operation. During Write. Auto-Refresh and NOP cycle, QS assert always "Low"
level. QS is Hi-Z in Self-Refresh mode.
(2) Unidirectional DS/Free running QS mode
DS is input signal and QS is output signal. Both edges of DS are used to sample all DQs at Write operation. Both edges of QS
are used for trigger signal of all DQs at Read operation. QS assert always toggle signal except Self-Refresh mode. This strobe
type is easy to use for pin to pin connect application.
Power Supply : V
DD
, V
DDQ
, V
SS
, V
SSQ
V
DD
and V
SS
are supply pins for memory core and peripheral circuits.
V
DDQ
and V
SSQ
are power supply pins for the output buffer.
Reference Voltage : V
REF
V
REF
is reference voltage for all input signals.
K4C89183AF
- 50 -
REV. 0.7 Jan. 2005
Command Functions and Operations
K4C89093AF is introduced the two consecutive command input method. Therefore, except for Power Down mode, each operation
mode decided by the combination of the first command and the second command from stand-by states of the bank to be accessed.
Read Operation (1st command + 2nd command = RDA + LAL)
Issuing the RDA command with Bank Addresses and Upper Addresses to the idle bank puts the bank designated by Bank Address in
a read mode. When the LAL command with Lower Addresses is issued at the next clock of the RDA command, the data is read out
sequentially synchronizing with the both edges of QS output signal (Burst Read Operation). The initial valid read data appears after
CAS latency, the burst length of read data and the burst type must be set in the Mode Register beforehand. The read operated bank
goes back automatically to the idle state after I
RC
.
Write Operation (1st command + 2nd command = WRA + LAL)
Issuing the WRA command with Bank Addresses and Upper Addresses to the idle bank puts the bank designated by Bank Address in
a write mode. When the LAL command with Lower Addresses is issued at the next clock of the WRA command, the input data is
latched sequentially synchronizing with the both edges of DS input signal (Burst Write Operation). The data and DS inputs have to be
asserted in keeping with clock input after CAS latency-1 from the issuing of the LAL command. The DS have to be provided for a burst
length. The CAS latency and the burst type must be set in the Mode Register beforehand. The write operated bank goes back automat-
ically to the idle state after I
RC
. Write Burst Length is controlled by VW0 and VW1 inputs with LAL command. See VW truth table.
Auto-Refresh Operation (1st command + 2nd command = WRA + REF)
K4C89093AF is required to refresh like a standard SDRAM. The Auto-Refresh operation is begun with the REF command following to
the WRA command. The Auto-Refresh mode can be effective only when all banks are in the idle state and all DQ are in Hi-Z states. In
a point to notice, the write mode started with the WRA command is canceled by the REF command having gone into the next clock of
the WRA command instead of the LAL command. The minimum period between the Auto-Refresh command and the next command is
specified by I
REFC
. However, about a synthetic average interval of Auto-Refresh command, it must be careful. In case of equally distrib-
uted refresh, Auto-Refresh command has to be issued within once for every 3.9 us by the maximum In case of burst refresh or random
distributed refresh, the average interval of eight consecutive Auto-Refresh command has to be more than 400ns always. In other words,
the number of Auto-Refresh cycles which can be performed within 3.2 us (8x400ns) is to 8 times in the maximum.
Power Down Mode( PD="L" )
When all banks are in the idle state and all DQ outputs are in Hi-Z states, the K4C89183AF become Power Down Mode by asserting
PD is "Low". When the device enters the Power Down Mode, all input and output buffers except for PD, CLK, CLK and QS. Therefore,
the power dissipation lowers. To exit the Power Down Mode, PD has to be brought to "High" and the DESL command has to be issued
for I
PDA
cycle after PD goes high. The Power Down exit function is asynchronous operation.
Mode Register Set (1st command + 2nd command = RDA + MRS)
When all banks are in the idle state, issuing the MRS command following to the RDA command can program the Mode Register. In a
point to notice, the read mode started with the RDA command is canceled by the MRS command having gone into the next clock of the
RDA command instead of the LAL command. The data to be set in the Mode Register is transferred using A0 to A14, BA0 and BA1
address inputs. The K4C89183AF have two mode registers. These are Regular and Extended Mode Register. The Regular or Extended
Mode Register is chosen by BA0 and BA1 in the MRS command.The Regular Mode Register designates the operation mode for a read
or write cycle. The Regular Mode Register has four function fields.
K4C89183AF
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REV. 0.7 Jan. 2005
The four fields are as follows :
(R-1) Burst Length field to set the length of burst data
(R-2) Burst Type field to designate the lower address access sequence in a burst cycle
(R-3) CAS Latency field to set the access time in clock cycle
(R-4) Test Mode field to use for supplier only.
The Extended Mode Register has two function fields.
The two fields are as follows:
(E-1) DLL Switch field to choose either DLL enable or DLL disable
(E-2) Output Driver Impedance Control field.
(E-3) Data Strobe Select
Once these fields in the Mode Register are set up, the register contents are maintained until the Mode Register is set up again by
another MRS command or power supply is lost. The initial value of the Regular or Extended Mode Register after power-up is unde-
fined, therefore the Mode Register Set command must be issued before proper operation.
Regular Mode Register/Extended Mode Register change bits (BA0, BA1)
These bits are used to choose either Regular MRS or Extended MRS
Regular Mode Register Fields
(R-1) Burst Length field (A2 to A0)
This field specifies the data length for column access using the A2 to A0 pins and sets the Burst Length to be 4 words.
(R-2) Burst Type field (A3)
This Burst Type can be chosen Interleave mode or Sequential mode. When the A3 bit is " 0", Sequential mode is
selected. When the A3 bit is "1", Interleave mode is selected. Both burst types support burst length of 2 and 4 words.
Addressing sequence of Sequential mode (A3)
A column access is started from the inputted lower address and is performed by incrementing the lower address input to
the device.
BA1
BA0
A14~A0
0
0
Regular MRS cycle
0
1
Extended MRS cycle
1
X
Reserved
A2
A1
A0
Burst Length
0
0
0
Reserved
0
0
1
Reserved
0
1
0
4 words
0
1
1
Reserved
1
X
X
Reserved
A3
Burst Type
0
Sequential
1
Interleave
K4C89183AF
- 52 -
REV. 0.7 Jan. 2005
RDA
LAL
Data 0 Data 1 Data 2 Data 3
Addressing sequence for Sequential mode
Data
Access Address
Burst Length
Data 0
n
4 words(Address bits is LA1, LA0)
not carried from LA1~LA2
Data 1
n + 1
Data 2
n + 2
Data 3
n + 3
CAS Latency = 4 (Free Running QS mode)
CK
CK
Command
QS
DQ
Functional Description (Continued)
Addressing sequence of Inteleave mode
A column access is started from the inputted lower address and is performed by interleaving the address bits in the
sequence shown as the following.
Addressing sequence for Interleave mode
(R-3) CAS Latency field (A6 to A4)
This field specifies the number of clock cycles from the assertion of the LAL command following the RDA command to
the first data read. The minimum values of CAS Latency depends on the frequency of CLK. In a write mode, the place of
clock which should input write data is CAS Latency cycles - 1.
Data
Access Address
Burst Length
Data 0
...A8 A7 A6 A5 A4 A3 A2 A1 A0
4 words
Data 1
...A8 A7 A6 A5 A4 A3 A2 A1 A0
Data 2
...A8 A7 A6 A5 A4 A3 A2 A1 A0
Data 3
...A8 A7 A6 A5 A4 A3 A2 A1 A0
Addressing sequence for Interleave mode
A6
A5
A4
CAS Latency
0
0
0
Reserved
0
0
1
Reserved
0
1
0
Reserved
0
1
1
Reserved
1
0
0
4
1
0
1
5
1
1
0
6
1
1
1
7
K4C89183AF
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REV. 0.7 Jan. 2005
(R-4) Test Mode field (A7)
This bit is used to enter Test Mode for supplier only and must be set to "0" for normal operation.
(R-5) Reserved field in the Regular Mode Register
Reserved bits (A8 to A14)
These bits are reserved for future operations. They must be set to "0" for normal operation.
Extended Mode Register Fields
(E-1) DLL Switch field (A0)
This bit is used to enable DLL. When the A0 bit is set "0", DLL is enabled.
(E-2) Output Driver Impedance Control field (A1 to A4)
This field is used to choose Output Driver Strength. Four types of Driver Strength are supported. QS and DQ Driver
Strength can be chosen separately. A2-A1 specified the DQ Driver Strength. A4-A3 specified the QS Driver Strength.
(E-3) Strobe Select (A6/A5)
Two types of strobe are supported. This field is used to choose the type of data strobe.
(1) Unidirectional DS/QS mode
Data strobe is separated DS for write strobe and QS for read strobe.
DS is used to sample write data at write operation. QS is aligned with read data at Read operation.
(2) Unidirectional DS/Free running QS mode
Data strobe is separated DS for write strobe and QS for read strobe.
DS is used to sample write data at write operation. QS is aligned with read data and always clocking
(E-4)Reserved fied (A7 to A14)
These bits are reserved for future operations and must be set to "0" for normal operation.
QS
DQ
Output Driver Impedance Control
A4
A3
A2
A1
0
0
0
0
Normal Output Driver
0
1
0
1
Strong Output Driver
1
0
1
0
Weaker Output Driver
1
1
1
1
Reserved
A6
A5
Strobe Select
0
0
Reserved
0
1
Reserved
1
0
Unidirectional DS/QS mode
1
1
Unidirectional DS/Free running QS mode
K4C89183AF
- 54 -
REV. 0.7 Jan. 2005
Package Outline Drawing (FBGA 60ball, 1.0 x 1.0 mm)
10.50
0.10
15.
50
0.
1
0
1
5
.
50
0.1
0
0.
1
0
M
a
x
0.
5
0.
05
0.35
0.05
1.10
0.10
Window Mold Area
TOP VIEW
1
3
4
5
6
10.50
0.10
A
B
C
D
E
F
G
H
J
K
L
M
7.00
1.00
x 14
= 14.0
0
1
5
.50
0.10
7.00
1.00 x 5 = 5.00
BOTTOM VIEW
1.0
0
1.00
P
R
1.50
1.50
2
1.00
60 -
0.45 solder ball
2.50
#A1 Mark (Option)
#A1
N
K4C89183AF
- 55 -
REV. 0.7 Jan. 2005
General Information
F6 : 667Mbps/pin (333MHz, CL=6)
FB : 600Mbps /pin (300MHz, CL=6)
F5 : 500Mbps/pin (250MHz, CL=6)
C : (Commercial, Normal)
I : (Industrial, Normal)
08 : x8
09 : x9
16 : x16
18 : x18
89 : 288M 8K/32ms
C : Network-DRAM
F : 7th Generation
K 4 C XX XX X X X - X X
Memory
DRAM
Small Classification
Density and Refresh
Temperature & Power
Package
Organization
Version
Interface (VDD & VDDQ)
1. SAMSUNG Memory : K
2. DRAM : 4
3. Small Classification
4. Density & Refresh
5. Organization
8. Version
9. Package
10. Temperature & Power
11. Speed
3 : 4 Bank
6. Bank
1 2 3 4 5 6 7 8 9 10 11
XX
A: SSTL-2(2.5V, 1.8V)
7. Interface (VDD & VDDQ)
Speed
Bank
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