128M DDR SDRAM
K4D261638E
- 1 -
Rev. 1.2 (Jul. 2003)
128Mbit DDR SDRAM
Revision 1.2
July 2003
2M x 16Bit x 4 Banks
Double Data Rate Synchronous DRAM
Samsung Electronics reserves the right to change products or specification without notice.
128M DDR SDRAM
K4D261638E
- 2 -
Rev. 1.2 (Jul. 2003)
Revision History
Revision 1.2 (July 21, 2003)
Added K4D261638E-TC2A in the spec
Revision 1.1 (January 16, 2003)
Changed ICC6 from 2mA to 4mA
Changed ICC5 of K4D261638E-TC33 from 260mA to 320mA
Changed ICC5 of K4D261638E-TC36 from 250mA to 310mA
Changed ICC5 of K4D261638E-TC40 from 230mA to 290mA
Changed ICC5 of K4D261638E-TC50 from 210mA to 270mA
Revision 1.0 (December 24, 2002)
Defined DC spec
Changed tRC of K4D261638E-TC33/36 from 13tCK to 15tCK
Changed tRFC of K4D261638E-TC33/36 from 15tCK to 17tCK
Changed tRAS of K4D261638E-TC33/36 from 9tCK to 10tCK
Changed tRP of K4D261638E-TC33/36 from 4tCK to 5tCK
Changed tDAL of K4D261638E-TC33/36 from 7tCK to 8tCK
Revision 0.3 (December 3, 2002) -
Target Spec
Typo corrected
Revision 0.2 (November 12, 2002) -
Target Spec
Changed tPDEX of K4D261638E-TC33/36/40/50 from 1tCK+tIS to 3tCK+tIS
Revision 0.1 (November 7, 2002) -
Target Spec
Changed tCK(max) of K4D261638E-TC33 from 4ns to 10ns
Changed tCK(max) of K4D261638E-TC36 from 6ns to 10ns
Typo corrected
Revision 0.0 (October 28, 2002) -
Target Spec
Defined Target Specification
128M DDR SDRAM
K4D261638E
- 3 -
Rev. 1.2 (Jul. 2003)
The K4D261638E is 134,217,728 bits of hyper synchronous data rate Dynamic RAM organized as 4 x 2,097,152 words by
16 bits, fabricated with SAMSUNG
'
s high performance CMOS technology. Synchronous features with Data Strobe allow
extremely high performance up to 1.4GB/s/chip. I/O transactions are possible on both edges of the clock cycle. Range of
operating frequencies, programmable burst length and programmable latencies allow the device to be useful for a variety
of high performance memory system applications.
2.5V + 5% power supply for device operation
2.5V + 5% power supply for I/O interface
SSTL_2 compatible inputs/outputs
4 banks operation
MRS cycle with address key programs
-. Read latency 3, 4 (clock)
-. Burst length (2, 4 and 8)
-. Burst type (sequential & interleave)
All inputs except data & DM are sampled at the positive
going edge of the system clock
Differential clock input
No Wrtie-Interrupted by Read Function
GENERAL DESCRIPTION
FEATURES
2 DQS's ( 1DQS / Byte )
Data I/O transactions on both edges of Data strobe
DLL aligns DQ and DQS transitions with Clock transition
Edge aligned data & data strobe output
Center aligned data & data strobe input
DM for write masking only
Auto & Self refresh
32ms refresh period (4K cycle)
66pin TSOP-II
Maximum clock frequency up to 350MHz
Maximum data rate up to 700Mbps/pin
FOR 2M x 16Bit x 4 Bank DDR SDRAM
2M x 16Bit x 4 Banks Double Data Rate Synchronous DRAM
with Bi-directional Data Strobe and DLL
ORDERING INFORMATION
For the K4D261638E-TC2A, VDD & VDDQ = 2.8V+0.1V
Part NO.
Max Freq.
Max Data Rate
Interface
Package
K4D261638E-TC2A
350MHz
700Mbps/pin
SSTL_2
66pin TSOP-II
K4D261638E-TC33
300MHz
600Mbps/pin
K4D261638E-TC36
275MHz
550Mbps/pin
K4D261638E-TC40
250MHz
500Mbps/pin
K4D261638E-TC50
200MHz
400Mbps/pin
128M DDR SDRAM
K4D261638E
- 4 -
Rev. 1.2 (Jul. 2003)
PIN CONFIGURATION
(Top View)
PIN DESCRIPTION
CK,CK
Differential Clock Input
BA
0
, BA
1
Bank Select Address
CKE
Clock Enable
A
0
~A
11
Address Input
CS
Chip Select
DQ
0
~ DQ
15
Data Input/Output
RAS
Row Address Strobe
V
DD
Power
CAS
Column Address Strobe
V
SS
Ground
WE
Write Enable
V
DDQ
Power for DQ
'
s
L(U)DQS
Data Strobe
V
SSQ
Ground for DQ
'
s
L(U)DM
Data Mask
NC
No Connection
RFU
Reserved for Future Use
1
66 PIN TSOP(II)
(400mil x 875mil)
2
3
4
5
6
7
8
9
10
11
12
20
19
18
17
16
15
14
13
27
26
25
24
23
22
21
54
53
52
51
50
49
48
47
46
45
44
43
35
36
37
38
39
40
41
42
55
56
57
58
59
60
34
(0.65 mm Pin Pitch)
33
32
31
30
29
28
61
62
63
64
65
66
V
DD
DQ
0
V
DDQ
DQ
1
DQ
2
V
SSQ
DQ
3
DQ
4
V
DDQ
DQ
5
DQ
6
V
SSQ
BA
0
CS
RAS
CAS
WE
LDM
V
DDQ
DQ
7
V
DD
A
3
A
2
A
1
A
0
AP/A
10
BA
1
NC
LDQS
NC
NC
NC
V
DD
V
SS
DQ
15
V
SSQ
DQ
14
DQ
13
V
DDQ
DQ
12
DQ
11
V
SSQ
DQ
10
DQ
9
V
DDQ
A
11
CKE
CK
UDM
V
REF
V
SSQ
DQ
8
V
SS
A
4
A
5
A
6
A
7
A
8
A
9
NC
UDQS
NC
V
SS
CK
NC
NC
128M DDR SDRAM
K4D261638E
- 5 -
Rev. 1.2 (Jul. 2003)
INPUT/OUTPUT FUNCTIONAL DESCRIPTION
*1 : The timing reference point for the differential clocking is the cross point of CK and CK.
For any applications using the single ended clocking, apply V
REF
to CK pin.
Symbol
Type
Function
CK, CK*1
Input
The differential system clock Input.
All of the inputs are sampled on the rising edge of the clock except
DQ
'
s and DM
'
s that are sampled on both edges of the DQS.
CKE
Input
Activates the CK signal when high and deactivates the CK signal
when low. By deactivating the clock, CKE low indicates the Power
down mode or Self refresh mode.
CS
Input
CS enables the command decoder when low and disabled the com-
mand decoder when high. When the command decoder is disabled,
new commands are ignored but previous operations continue.
RAS
Input
Latches row addresses on the positive going edge of the CK with
RAS low. Enables row access & precharge.
CAS
Input
Latches column addresses on the positive going edge of the CK with
CAS low. Enables column access.
WE
Input
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
LDQS,UDQS
Input/Output
Data input and output are synchronized with both edge of DQS.
For the x16, LDQS corresponds to the data on DQ0-DQ7 ; UDQS
corresponds to the data on DQ8-DQ15.
LDM,UDM
Input
Data in Mask. Data In is masked by DM Latency=0 when DM is
high in burst write. For the x16, LDM corresponds to the data on
DQ0-DQ7 ; UDM correspons to the data on DQ8-DQ15.
DQ
0
~ DQ
15
Input/Output
Data inputs/Outputs are multiplexed on the same pins.
BA
0
, BA
1
Input
Selects which bank is to be active.
A
0
~ A
11
Input
Row/Column addresses are multiplexed on the same pins.
Row addresses : RA
0
~ RA
11
, Column addresses : CA
0
~ CA
8
.
V
DD
/V
SS
Power Supply
Power and ground for the input buffers and core logic.
V
DDQ
/V
SSQ
Power Supply
Isolated power supply and ground for the output buffers to provide
improved noise immunity.
V
REF
Power Supply
Reference voltage for inputs, used for SSTL interface.
NC/RFU
No connection/
Reserved for future use
This pin is recommended to be left "No connection" on the device
PDF 
ZIP