128M DDR SDRAM

K4D263238M

- 2 -

Rev. 1.3 (Aug. 2001)

Revision History

Revision 1.3 (August 2, 2001)

· Removed K4D263238M-QC40 with VDD&VDDQ=2.8V
· Changed VDD&VDDQ of K4D263238M-QC45 from 2.8V to 2.5V.
· Changed tCK(max) from 7ns to 10ns.

Revision 1.2 (July 12, 2001)

· Corrected CAS latency of K4D263238M-QC45 from CL3 to CL4
· The specification for the 222MHz/250MHz is preliminary one.

Revision 1.1 (March 5, 2000)

· Added K4D263238M-QC40 with VDD&VDDQ=2.8V
· Changed VDD/VDDQ of K4D263238M-QC45 from 2.5V to 2.8V. Accordingly, DC current characteristics values have been changed.

- Changed CAS latency of K4D263238M-QC45 from CL4 to CL3.

· Changed tWPREH of K4D263238M-QC50 from 0.3tCK to 0.25tCK

128M DDR SDRAM

K4D263238M

- 3 -

Rev. 1.3 (Aug. 2001)

Revision 1.0 (December 13, 2000)

· Defined capacitance values
· Chagned tRCDWR of K4D263238M-QC60 from 1tCK to 2tCK

Revision 0.5 (December 8, 2000)

· Changed AC input level from Vref + 0.31V to Vref + 0.35V
· Changed tRC/tRFC/tRAS/tRP/tRCDRD/tRCDWR from ns unit based from clock unit based.

Changed V

OUT

DDQ

in absolute maximum ratings from -1.0V ~3.6V to -0.5V ~ 3.6V.

Revision 0.4 (November 29, 2000) - Preliminary

· Removed K4D263238M-QC40
· Several AC parameters of K4D263238M-QC45 have been changed

- Changed tDQSQ from 0.4ns to 0.45ns. Changed tQH from tHP-0.6ns to tHP-0.45ns.
- Changed tDQSCK & tAC from 0.6ns to 0.7ns
- Changed tDQSS from 0.75tCK/1.25tCK to 0.8tCK/1.2tCK. Accordingly, changed tWPREH from 0.25tCK to 0.3tCK.
- Changed tDS/tDH from 0.4ns to 0.45ns. Changed tIS/tIH from 0.9ns to 1.0ns
- Corrected tDAL from 5tCK to 6tCK

· Several AC parameters of K4D263238M-QC50 have been changed

- Changed tQH from tHP-0.6ns to tHP-0.45ns.
- Changed tDQSCK & tAC from 0.6ns to 0.7ns
- Changed tDQSS from 0.75tCK/1.25tCK to 0.8tCK/1.2tCK. Accordingly, changed tWPREH from 0.25tCK to 0.3tCK.
- Corrected tDAL from 5tCK to 6tCK

· Several AC parameters of K4D263238M-QC55 have been changed

- Changed tDQSQ from 0.45ns to 0.5ns. Changed

tOH from tHP-0.6ns to tHP-0.5ns.

- Changed tDQSCK & tAC from 0.6ns to 0.75ns
- Changed tDS/tDH from 0.45ns to 0.5ns. Changed tIS/tIH from 1.0ns to 1.1ns
- Changed tRC/tRFC from 60.5ns/71.5ns to 66ns/77ns. Changed tRP from 16.5ns to 22ns.
- Corrected tRCDWR from 5.5ns to 11ns. Corrected tDAL from 5tCK to 6tCK

· Changed tQH of K4D263238M-QC60 from tHP-0.75ns to tHP-0.5ns
· Add DC Characteristics value

Define V

(max) / V

(min) as a note in Power & DC operating Condition table

· Changed refresh cycle time from 16ms to 32ms.Accordingly, tREF has been changed from 3.9us to 7.8us.

Changed I

test condition from 0V< V

+0.3V to 0V< V

Revision 0.3 (June 8, 2000)

· Removed Block Write function

Revision 0.2 (April 10, 2000)

· Separated tRCD into tRCDRD and tRCDWR

- tRCDRD: Row to Column delay for READ

- tRCDWR: Row to Column delay at WRITE

Revision 0.1 (March 16, 2000)

· Define the spec based on Vdd&Vddq=2.5V
· Maximum target frequency upto 250MHz@CL4

Removed Write Interrupt by Read function

Revision 0.0 (December 27, 1999) - Target Spec

· Defined Target Specification

128M DDR SDRAM

K4D263238M

- 4 -

Rev. 1.3 (Aug. 2001)

The K4D263238 is 134,217,728 bits of hyper synchronous data rate Dynamic RAM organized as 4 x 1,048,576 words by

32 bits, fabricated with SAMSUNG

s high performance CMOS technology. Synchronous features with Data Strobe allow

extremely high performance up to

1.8GB/s/chip.

I/O transactions are possible on both edges of the clock cycle. Range of

operating frequencies, programmable burst length and programmable latencies allow the device to be useful for a variety

of high performance memory system applications.

· 2.5V ± 5% power supply

· SSTL_2 compatible inputs/outputs

· 4 banks operation

· MRS cycle with address key programs

-. Read latency 3,4 (clock)

-. Burst length (2, 4, 8 and Full page)

-. Burst type (sequential & interleave)

· Full page burst length for sequential burst type only

· Start address of the full page burst should be even

· All inputs except data & DM are sampled at the positive

going edge of the system clock

· Differential clock input

· No Write Interrupted by Read function

GENERAL DESCRIPTION

FEATURES

· Data I/O transactions on both edges of Data strobe

· DLL aligns DQ and DQS transitions with Clock transition

· Edge aligned data & data strobe output

· Center aligned data & data strobe input

· DM for write masking only

· Auto & Self refresh

· 32ms refresh period (4K cycle)

· 100pin TQFP package

· Maximum clock frequency up to 222MHz

· Maximum data rate up to 444Mbps/pin

FOR 1M x 32Bit x 4 Bank DDR SDRAM

1M x 32Bit x 4 Banks Double Data Rate Synchronous RAM
with Bi-directional Data Strobe and DLL

ORDERING INFORMATION

Part NO.

Max Freq.

Max Data Rate

Interface

Package

K4D263238M-QC45

222MHz

444Mbps/pin

SSTL_2

100 TQFP

K4D263238M-QC50

200MHz

400Mbps/pin

K4D263238M-QC55

183MHz

366Mbps/pin

K4D263238M-QC60

166MHz

333Mbps/pin

128M DDR SDRAM

K4D263238M

- 5 -

Rev. 1.3 (Aug. 2001)

PIN CONFIGURATION

(Top View)

PIN DESCRIPTION

CK,CK

Differential Clock Input

, BA

Bank Select Address

CKE

Clock Enable

Address Input

Chip Select

~ DQ

Data Input/Output

RAS

Row Address Strobe

Power

CAS

Column Address Strobe

Ground

Write Enable

DDQ

Power for DQ

DQS

Data Strobe

SSQ

Ground for DQ

DMi

Data Mask

MCL

Must Connect Low

RFU

Reserved for Future Use

DQ29

VSSQ

DQ30

DQ31

VSS

VDDQ

N.C

VSSQ

RFU

DQS

VDDQ

VDD

DQ0

DQ1

VSSQ

DQ2

100

VSS

N.C

A11

A10

VDD

100 Pin TQFP

20 x 14 mm

0.65mm pin Pitch

(
A

)

128M DDR SDRAM

K4D263238M

- 6 -

Rev. 1.3 (Aug. 2001)

INPUT/OUTPUT FUNCTIONAL DESCRIPTION

*1 : The timing reference point for the differential clocking is the cross point of CK and CK.

For any applications using the single ended clocking, apply V

REF

to CK pin.

Symbol

Type

Function

CK, CK

Input

The differential system clock Input.

All of the inputs are sampled on the rising edge of the clock except

s and DM

s that are sampled on both edges of the DQS.

CKE

Input

Activates the CK signal when high and deactivates the CK signal

when low. By deactivating the clock, CKE low indicates the Power

down mode or Self refresh mode.

Input

CS enables the command decoder when low and disabled the com-

mand decoder when high. When the command decoder is disabled,

new commands are ignored but previous operations continue.

RAS

Input

Latches row addresses on the positive going edge of the CK with

RAS low. Enables row access & precharge.

CAS

Input

Latches column addresses on the positive going edge of the CK with

CAS low. Enables column access.

Input

Enables write operation and row precharge.

Latches data in starting from CAS, WE active.

DQS

Input/Output

Data input and output are synchronized with both edge of DQS.

~ DM

Input

Data In mask. Data In is masked by DM Latency=0 when DM is high

in burst write. DM

for DQ

~ DQ

for DQ

~ DQ

15,

for

~ DQ

23,

for DQ

~ DQ

31.

~ DQ

Input/Output

Data inputs/Outputs are multiplexed on the same pins.

, BA

Input

Selects which bank is to be active.

~ A

Input

Row/Column addresses are multiplexed on the same pins.

Row addresses : RA

~ RA

, Column addresses : CA

~ CA

Column address CA

is used for auto precharge.

Power Supply

Power and ground for the input buffers and core logic.

DDQ

SSQ

Power Supply

Isolated power supply and ground for the output buffers to provide

improved noise immunity.

REF

Power Supply

Reference voltage for inputs, used for SSTL interface.

MCL

Must Connect Low

Must connect Low

128M DDR SDRAM

K4D263238M

- 7 -

Rev. 1.3 (Aug. 2001)

BLOCK DIAGRAM

(1Mbit x 32I/O x 4 Bank)

Bank Select

Timing Register

r
e

i
s

t
e

f
r
e

t
e

f
f
e

l
.

B

f
f
e

Data Input Register

Serial to parallel

1Mx32

-
b

i
t

p

r
e

f
e

t
c

t
p

t

B

f
f
e

I
/
O

t
r
o

Column Decoder

Latency & Burst Length

Programming Register

t
r
o

CK,CK

ADDR

LCKE

CK,CK

CKE

RAS

CAS

DMi

LDMi

CK,CK

LCAS

LRAS

LCBR

LWE

LWCBR

CK, CK

LWE

LDMi

x32

DQi

Data Strobe

Intput Buffer

DLL

128M DDR SDRAM

K4D263238M

- 8 -

Rev. 1.3 (Aug. 2001)

· Power-Up Sequence

DDR SDRAMs must be powered up and initialized in a predefined manner to prevent undefined operations.

1. Apply power and keep CKE at low state (All other inputs may be undefined)
- Apply VDD before VDDQ .
- Apply VDDQ before VREF & VTT
2. Start clock and maintain stable condition for minimum 200us.
3. The minimum of 200us after stable power and clock(CK,CK ), apply NOP and take CKE to be high.
4. Issue precharge command for all banks of the device.
5. Issue a EMRS command to enable DLL

6. Issue a MRS command to reset DLL. The additional 200 clock cycles are required to lock the DLL.

1,2

7. Issue precharge command for all banks of the device.

8. Issue at least 2 or more auto-refresh commands.
9. Issue a mode register set command with A8 to low to initialize the mode register.

*1 The additional 200cycles of clock input is required to lock the DLL after enabling DLL.
*2 Sequence of 6&7 is regardless of the order.

FUNCTIONAL DESCRIPTION

Power up & Initialization Sequence

Command

tRP

2 Clock min.

precharge

ALL Banks

2nd Auto

Refresh

Mode

Any

Command

RFC

1st Auto

Refresh

RFC

EMRS

MRS

2 Clock min.

DLL Reset

precharge

ALL Banks

CK
CK

Inputs must be

stable for 200us

200 Clock min.

2 Clock min.

128M DDR SDRAM

K4D263238M

- 9 -

Rev. 1.3 (Aug. 2001)

The mode register stores the data for controlling the various operating modes of DDR SDRAM. It programs CAS latency,

addressing mode, burst length, test mode, DLL reset and various vendor specific options to make DDR SDRAM useful for
variety of different applications. The default value of the mode register is not defined, therefore the mode register must be
written after EMRS setting for proper operation. The mode register is written by asserting low on CS, RAS, CAS and
WE(The DDR SDRAM should be in active mode with CKE already high prior to writing into the mode register). The state of
address pins A

~ A

and BA

, BA

in the same cycle as CS, RAS, CAS and WE going low is written in the mode register.

Minimum two clock cycles are requested to complete the write operation in the mode register. The mode register contents
can be changed using the same command and clock cycle requirements during operation as long as all banks are in the
idle state. The mode register is divided into various fields depending on functionality. The burst length uses A

~ A

addressing mode uses A

, CAS latency(read latency from column address) uses A

~ A

. A

is used for test mode. A

used for DLL reset. A

, BA

and BA

must be set to low for normal MRS operation. Refer to the table for specific codes

for various burst length, addressing modes and CAS latencies.

MODE REGISTER SET(MRS)

Address Bus

Mode

CAS Latency

Latency

Reserved

Burst Length

Burst Type

Sequential

Interleave

Reserve

Full page

Reserve

Burst Type

Type

Sequential

Interleave

* RFU(Reserved for future use)

should stay "0" during MRS
cycle.

MRS Cycle

Command

*1: MRS can be issued only at all banks precharge state.
*2: Minimum

is required to issue MRS command.

CK, CK

Precharge

NOP

MRS

NOP

Any

NOP

All Banks

Command

MRD

=2 t

RFU

DLL

CAS Latency

Burst Length

~ A

MRS

EMRS

DLL

DLL Reset

Yes

Test Mode

mode

Normal

Test

NOP

128M DDR SDRAM

K4D263238M

- 10 -

Rev. 1.3 (Aug. 2001)

The extended mode register stores the data for enabling or disabling DLL and selecting output driver strength. The

default value of the extended mode register is not defined, therefore the extend mode register must be written after power
up for enabling or disabling DLL. The extended mode register is written by asserting low on CS, RAS, CAS, WE and high
on BA0(The DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the extended mode
register). The state of address pins A0, A2 ~ A5, A7 ~ A11 and BA1 in the same cycle as CS, RAS, CAS and WE going
low are written in the extended mode register. A1 and A6 are used for setting driver strength to weak or matched imped-
ance. Two clock cycles are required to complete the write operation in the extended mode register. The mode register
contents can be changed using the same command and clock cycle requirements during operation as long as all banks
are in the idle state. A0 is used for DLL enable or disable. "High" on BA0 is used for EMRS. All the other address pins
except A0,A1,A6 and BA0 must be set to low for proper EMRS operation. Refer to the table for specific codes.

DLL Enable

Enable

Disable

~ A

MRS

EMRS

Figure 7. Extend Mode Register set

EXTENDED MODE REGISTER SET(EMRS)

Address Bus

Extended

RFU

D.I.C

RFU

D.I.C

DLL

Mode Register

* RFU(Reserved for future use)

should stay "0" during EMRS
cycle.

Output Driver Impedance Control

Weak

60% of full drive strength

Matched impedance 30% of full drive strength

128M DDR SDRAM

K4D263238M

- 11 -

Rev. 1.3 (Aug. 2001)

ABSOLUTE MAXIMUM RATINGS

Parameter

Symbol

Value

Unit

Voltage on any pin relative to Vss

, V

OUT

-0.5 ~ 3.6

Voltage on V

supply relative to Vss

-1.0 ~ 3.6

Voltage on V

supply relative to Vss

DDQ

-0.5 ~ 3.6

Storage temperature

STG

-55 ~ +150

Power dissipation

2.0

Short circuit current

Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

Note :

POWER & DC OPERATING CONDITIONS(SSTL_2 In/Out)

Recommended operating conditions(Voltage referenced to V

=0V, T

=0 to 65

Parameter

Symbol

Min

Typ

Max

Unit

Note

Device Supply voltage

2.375

2.50

2.625

Output Supply voltage

DDQ

2.375

2.50

2.625

Reference voltage

REF

0.49*V

DDQ

0.51*V

DDQ

Termination voltage

Vtt

REF

-0.04

REF

+0.04

Input logic high voltage

REF

+0.15

DDQ

+0.30

Input logic low voltage

-0.30

REF

-0.15

Output logic high voltage

Vtt+0.76

=-15.2mA

Output logic low voltage

Vtt-0.76

=+15.2mA

Input leakage current

-5

Output leakage current

-5

1. Under all conditions V

DDQ

must be less than or equal to V

2. V

REF

is expected to equal 0.50*V

DDQ

of the transmitting device and to track variations in the DC level of the same. Peak to

peak noise on the V

REF

may not exceed +

2% of the DC value. Thus, from 0.50*V

DDQ

, V

REF

is allowed +

25mV for DC error

and an additional +

25mV for AC noise.

3. V

of the transmitting device must track V

REF

of the receiving device.

4. V

(max.)= V

DDQ

+1.5V for a pulse and it which can not be greater than 1/3 of the cycle rate.

5. V

(min.)= -1.5V for a pulse width and it can not be greater than 1/3 of the cycle rate.

6. For any pin under test input of 0V

is acceptable. For all other pins that are not under test V

=0V.

Note :

128M DDR SDRAM

K4D263238M

- 12 -

Rev. 1.3 (Aug. 2001)

DC CHARACTERISTICS

Note: 1. Measured with outputs open.

2. Refresh period is 32ms.

Parameter

Sym-
bol

Test Condition

Version

Unit Note

-45*

-50

-55

-60

Operating Current
(One Bank Active)

CC1

Burst Lenth=2

(min)

=0mA,

(min)

310

260

Precharge Standby Current
in Power-down mode

CC2

CKE

(max),

(min)

Precharge Standby Current
in Non Power-down mode

CC2

CKE

(min), CS

(min),

(min).

155

135

130

125

Active Standby Current
power-down mode

CC3

CKE

(max),

(min)

105

Active Standby Current in
in Non Power-down mode

CC3

CKE

VIH(min), CS

VIH(min),

(min) .

190

160

150

140

Operating Current
( Burst Mode)

CC4

=0mA ,

(min), Page

Burst, All Banks activated.

660

550

500

460

Refresh Current

CC5

RFC

(min)

380

330

320

Self Refresh Current

CC6

CKE

0.2V

Recommended operating conditions Unless Otherwise Noted, T

=0 to 65

AC INPUT OPERATING CONDITIONS

Recommended operating conditions(Voltage referenced to V

=0V,

/ V

DDQ

=2.5V+

=0 to 65

Parameter

Symbol

Min

Typ

Max

Unit

Note

Input High (Logic 1) Voltage; DQ

REF

+0.35

Input Low (Logic 0) Voltage; DQ

REF

-0.35

Clock Input Differential Voltage; CK and CK

0.7

DDQ

+0.6

Clock Input Crossing Point Voltage; CK and CK

0.5*V

DDQ

-0.2

0.5*V

DDQ

+0.2

1. V

is the magnitude of the difference between the input level on CK and the input level on CK

2. The value of V

is expected to equal 0.5*V

DDQ

of the transmitting device and must track variations in the DC level of the same

Note :

128M DDR SDRAM

K4D263238M

- 13 -

Rev. 1.3 (Aug. 2001)

AC OPERATING TEST CONDITIONS

(

/ V

DDQ

=2.5V+

= 0 to 65

Parameter

Value

Unit

Note

Input reference voltage for CK(for single ended)

0.50*V

DDQ

CK and CK signal maximum peak swing

1.5

CK signal minimum slew rate

1.0

V/ns

Input Levels(V

)

REF

+0.35/V

REF

-0.35

Input timing measurement reference level

REF

Output timing measurement reference level

Output load condition

See Fig.1

=50

Output

LOAD

=30pF

(Fig. 1) Output Load Circuit

Z0=50

REF

=0.5*V

DDQ

=0.5*V

DDQ

DECOUPLING CAPACITANCE GUIDE LINE

Recommended decoupling capacitance added to power line at board.

Parameter

Symbol

Value

Unit

Decoupling Capacitance between V

and V

DC1

0.1 + 0.01

Decoupling Capacitance between V

DDQ

and V

SSQ

DC2

0.1 + 0.01

1. V

and V

DDQ

pins are separated each other.

All V

pins are connected in chip. All V

DDQ

pins are connected in chip.

2. V

and V

SSQ

pins are separated each other

All V

pins are connected in chip. All V

SSQ

pins are connected in chip.

Note :

CAPACITANCE

=2.5V, T

= 25

f=1MHz)

Parameter

Symbol

Min

Max

Unit

Input capacitance(

CK, CK )

IN1

1.0

5.0

Input capacitance(A

, BA

~BA

)

IN2

1.0

4.0

Input capacitance
(

CKE, CS, RAS,CAS, WE )

IN3

1.0

4.0

Data & DQS input/output capacitance(DQ

~DQ

)

OUT

1.0

6.0

Input capacitance(DM0 ~ DM3)

IN4

1.0

6.0

128M DDR SDRAM

K4D263238M

- 14 -

Rev. 1.3 (Aug. 2001)

tCL

tCK

Hi-Z

CK, CK

DQS

tIS

tIH

tDS tDH

tRPST

tRPRE

Db0

Db1

tDQSS

tDQSH

tCH

Da1

Da2

tWPST

COMMAND

READA

WRITEB

tDQSQ

WPRES

WPREH

tDQSCK

tAC

AC CHARACTERISTICS

Simplified Timing @ BL=2, CL=3

Parameter

Symbol

-45*

-50

-55

-60

Unit

Note

Min

Max

Min

Max

Min

Max

Min

Max

CK cycle time

CL=3

5.0

5.5

6.0

CL=4

4.5

CK high level width

0.45

0.55

0.45

0.55

0.45

0.55

0.45

0.55

tCK

CK low level width

0.45

0.55

0.45

0.55

0.45

0.55

0.45

0.55

tCK

DQS out access time from CK

DQSCK

-0.7

+0.7

-0.7

+0.7

-0.75

+0.75

-0.75

+0.75

Output access time from CK

-0.7

+0.7

-0.7

+0.7

-0.75

+0.75

-0.75

+0.75

Data strobe edge to Dout edge

DQSQ

+0.45

+0.5

Read preamble

RPRE

0.9

1.1

0.9

1.1

0.9

1.1

0.9

1.1

tCK

Read postamble

RPST

0.4

0.6

0.4

0.6

0.4

0.6

0.4

0.6

tCK

CK to valid DQS-in

DQSS

0.8

1.2

0.8

1.2

0.75

1.25

0.75

1.25

tCK

DQS-In setup time

WPRES

DQS-in hold time

WPREH

0.25

tCK

DQS write postamble

WPST

0.4

0.6

0.4

0.6

0.4

0.6

0.4

0.6

tCK

DQS-In high level width

DQSH

0.4

0.6

0.4

0.6

0.4

0.6

0.4

0.6

tCK

DQS-In low level width

DQSL

0.4

0.6

0.4

0.6

0.4

0.6

0.4

0.6

tCK

Address and Control input
setup

1.0

1.1

Address and Control input hold

1.0

1.1

DQ and DM setup time to DQS

0.45

0.5

DQ and DM hold time to DQS

0.45

0.5

Clock half period

tCLmin

tCHmin

tCLmin

tCHmin

tCLmin

tCHmin

tCLmin

tCHmin

Data output hold time from
DQS

tHP-0.45

tHP-0.5

128M DDR SDRAM

K4D263238M

- 15 -

Rev. 1.3 (Aug. 2001)

Note 1 :

- The JEDEC DDR specification currently defines the output data valid window(tDV) as the time period when the data

strobe and all data associated with that data strobe are coincidentally valid.

- The previously used definition of tDV(=0.35tCK) artificially penalizes system timing budgets by assuming the worst case

output valid window even then the clock duty cycle applied to the device is better than 45/55%

- A new AC timing term, tQH which stands for data output hold time from DQS is defined to account for clock duty cycle

variation and replaces tDV

- tQHmin = tHP-X where

. tHP=Minimum half clock period for any given cycle and is defined by clock high or clock low time(tCH,tCL)

. X=A frequency dependent timing allowance account for tDQSQmax

tQH Timing (CL3, BL2)

tHP

CK, CK

DQS

COMMAND

READA

tQH

Da0

tDQSQ(max)

Da1

128M DDR SDRAM

K4D263238M

- 16 -

Rev. 1.3 (Aug. 2001)

AC CHARACTERISTICS (I)

Note :1 For normal write operation, even numbers of Din are to be written inside DRAM

Parameter

Symbol

-45*

-50

-55

-60

Unit

Note

Min

Max

Min

Max

Min

Max

Min

Max

Row cycle time

tCK

Refresh row cycle time

RFC

tCK

Row active time

RAS

100K

tCK

RAS to CAS delay for Read

RCDRD

tCK

RAS to CAS delay for Write

RCDWR

tCK

Row precharge time

tCK

Row active to Row active

RRD

tCK

Last data in to Row precharge

tCK

Last data in to Read com-
mand

CDLR

tCK

Col. address to Col. address

CCD

tCK

Mode register set cycle time

MRD

tCK

Auto precharge write recovery
+ Precharge

DAL

tCK

Exit self refresh to read com-

XSR

200

tCK

Power down exit time

PDEX

1tCK+tIS

Refresh interval time

REF

7.8

128M DDR SDRAM

K4D263238M

- 17 -

Rev. 1.3 (Aug. 2001)

AC CHARACTERISTICS (II)

K4D263238M-QC45*

Frequency

Cas Latency

tRC

tRFC

tRAS

tRCDRD

tRCDWR

tRP

tRRD

Unit

222MHz ( 4.5ns )

tCK

200MHz ( 5.0ns )

tCK

183MHz ( 5.5ns )

tCK

166MHz ( 6.0ns )

tCK

143MHz ( 7.0ns )

tCK

K4D263238M-QC50

Frequency

Cas Latency

tRC

tRFC

tRAS

tRCDRD

tRCDWR

tRP

tRRD

Unit

200MHz ( 5.0ns )

tCK

183MHz ( 5.5ns )

tCK

166MHz ( 6.0ns )

tCK

143MHz ( 7.0ns )

tCK

K4D263238M-QC55

Frequency

Cas Latency

tRC

tRFC

tRAS

tRCDRD

tRCDWR

tRP

tRRD

Unit

183MHz ( 5.5ns )

tCK

166MHz ( 6.0ns )

tCK

143MHz ( 7.0ns )

tCK

K4D263238M-QC60

Frequency

Cas Latency

tRC

tRFC

tRAS

tRCDRD

tRCDWR

tRP

tRRD

Unit

166MHz ( 6.0ns )

tCK

143MHz ( 7.0ns )

tCK

(Unit : Number of Clock)

128M DDR SDRAM

K4D263238M

- 18 -

Rev. 1.3 (Aug. 2001)

BAa

tRCD

ACTIVEA

ACTIVEB

WRITEA

WRITEB

Db0 Db1

Db3

BAa

BAb

BAa

PRECH

BAa

Da0 Da1 Da2 Da3

Normal Write Burst

(@ BL=4)

Multi Bank Interleaving Write Burst

(@ BL=4)

BAa

BAb

Db2

tRAS

tRC

tRP

tRRD

COMMAND

DQS

CK, CK

A8/AP

ADDR

(A0~A7,

BA[1:0]

A9~,A11)

ACTIVEA

WRITEA

Da0 Da1 Da2 Da3

Simplified Timing(2) @ BL=4, CL=3

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: K4D263238M-QC50

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: K4D263238M-QC50