128M DDR SDRAM

K4D26323RA-GC

* VDD / VDDQ=2.8V *

- 2 -

Rev. 2.0 (Jan. 2003)

Revision History

Revision 2.0 (January 16, 2003)

· Changed package ball height from 0.25mm to 0.35mm

Revision 1.9 (August 12, 2002)

· Changed tRC of K4D26323RA-GC2A from 20tCK to 15tCK
· Changed tRFC of K4D26323RA-GC2A from 22tCK to 17tCK
· Changed tRAS of K4D26323RA-GC2A from 14tCK to 10tCK
· Changed tRCDRD of K4D26323RA-GC2A from 7tCK to 5tCK
· Changed tRCDWR of K4D26323RA-GC2A from 5tCK to 3tCK
· Changed tRP of K4D26323RA-GC2A from 6tCK to 5tCK
· Changed tDAL of K4D26323RA-GC2A from 9tCK to 8tCK
· Changed tRC of K4D26323RA-GC33 from 17tCK to 13tCK
· Changed tRFC of K4D26323RA-GC33 from 19tCK to 15tCK
· Changed tRAS of K4D26323RA-GC33 from 12tCK to 9tCK
· Changed tRCDRD of K4D26323RA-GC33 from 6tCK to 4tCK
· Changed tRCDWR of K4D26323RA-GC33 from 4tCK to 2tCK
· Changed tRP of K4D26323RA-GC33 from 5tCK to 4tCK
· Changed tWR of K4D26323RA-GC33 from 3tCK to 2tCK
· Changed tDAL of K4D26323RA-GC33 from 8tCK to 7tCK

Revision 1.8 (July 18, 2002)

· Changed power dissipation from 2,0W to 3.3W

Revision 1.7 (May 7, 2002)

· Typo corrected

Revision 1.6 (Janaury 29, 2002)

· Changed CL of K4D26323RA-GC33/36 from 5tCK to 4tCK
· Changed tCK(max) of K4D26323RA-GC2A from 5ns to 4ns.

For all the CL5 operation, guaranteed tCK(max) is 4ns.

Revision 1.5 (December 10, 2001)

· Removed K4D263238A-GC33/40/45/50/55/60(VDD/VDDQ=2.5V) from the spec

Revision 1.4 (November 14, 2001)

· Added K4D26323RA-GC36(VDD/VDDQ=2.8V)

Revision 1.3 (October 22, 2001)

· Corrected part number of K4D263238A-GC2A to K4D26323RA-GC2A
· Changed tCDLR of -GC2A and GC33 from 3tCK to 2tCK and applied since Sept 15, 2001.
· Defined x32 DDR for mobile PC graphics separately - K4D26323AA-GL** featured with VDDQ=1.8V,ICC6=1mA with

reduced operating current. Refer to the K4D26323AA-GL** spec for more detail information.

128M DDR SDRAM

K4D26323RA-GC

* VDD / VDDQ=2.8V *

- 3 -

Rev. 2.0 (Jan. 2003)

Revision 1.2 (September 13, 2001)

· Define DC spec value of K4D26323RA-GC33 and K4D263238A-GC2A
· Changed tCK(max) of -2A and -33 from 7ns to 5ns

Revision 1.1 (September 3, 2001)

· Added K4D26323RA-GC33(VDD/VDDQ=2.8V)
· Added K4D263238A-GC2A(350MHz)

Revision 1.0 (August 16, 2001)

· Changed tCDLR of K4D263238A-GC33 from 2tCK to 3tCK
· Removed VDDQ=1.8V from the spec.
· Added K4D263238A-GL as a low power part
· Defined DC spec.

Revision 0.1 (August 2, 2001) -

Target Spec

· Changed tCK(max) of K4D263238A-GC45/-50/-55/-60 from 7ns to 10ns.

Revision 0.0 (June, 2001) -

Target Spec

· Defined Target Specification

128M DDR SDRAM

K4D26323RA-GC

* VDD / VDDQ=2.8V *

- 4 -

Rev. 2.0 (Jan. 2003)

The K4D26323RA is 134,217,728 bits of hyper synchronous data rate Dynamic RAM organized as 4 x1,048,576 words by

32 bits, fabricated with SAMSUNG

s high performance CMOS technology. Synchronous features with Data Strobe allow

extremely high performance up to 2.8GB/s/chip. I/O transactions are possible on both edges of the clock cycle. Range of

operating frequencies, programmable burst length and programmable latencies allow the device to be useful for a variety

of high performance memory system applications.

· 2.8V + 5% power supply for device operation

· 2.8V + 5% power supply for I/O interface

· SSTL_2 compatible inputs/outputs

· 4 banks operation

· MRS cycle with address key programs

-. Read latency 3,4 (clock)

-. Burst length (2, 4, 8 and Full page)

-. Burst type (sequential & interleave)

· Full page burst length for sequential burst type only

· Start address of the full page burst should be even

· All inputs except data & DM are sampled at the positive

going edge of the system clock

· Differential clock input

· No Wrtie-Interrupted by Read Function

GENERAL DESCRIPTION

FEATURES

· 4 DQS's ( 1DQS / Byte )

· Data I/O transactions on both edges of Data strobe

· DLL aligns DQ and DQS transitions with Clock transition

· Edge aligned data & data strobe output

· Center aligned data & data strobe input

· DM for write masking only

· Auto & Self refresh

· 32ms refresh period (4K cycle)

· 144-Ball FBGA

· Maximum clock frequency up to 350MHz

· Maximum data rate up to 700Mbps/pin

FOR 1M x 32Bit x 4 Bank DDR SDRAM

1M x 32Bit x 4 Banks Double Data Rate Synchronous RAM
with Bi-directional Data Strobe and DLL

ORDERING INFORMATION

Part NO.

Max Freq.

Max Data Rate

Interface

Package

K4D26323RA-GC2A

350MHz

700Mbps/pin

SSTL_2

(VDD/VDDQ=2.8V)

144-Ball FBGA

K4D26323RA-GC33

300MHz

600Mbps/pin

K4D26323RA-GC36

275MHz

550Mbps/pin

128M DDR SDRAM

K4D26323RA-GC

* VDD / VDDQ=2.8V *

- 5 -

Rev. 2.0 (Jan. 2003)

PIN CONFIGURATION

(Top View)

PIN DESCRIPTION

CK,CK

Differential Clock Input

, BA

Bank Select Address

CKE

Clock Enable

Address Input

Chip Select

~ DQ

Data Input/Output

RAS

Row Address Strobe

Power

CAS

Column Address Strobe

Ground

Write Enable

DDQ

Power for DQ

DQS

Data Strobe

SSQ

Ground for DQ

Data Mask

No Connection

RFU

Reserved for Future Use

MCL

Must Connect Low

DQS0

VSS

RFU

Thermal

VSS

Thermal

VSS

Thermal

VSS

Thermal

VSS

Thermal

VSS

Thermal

VSS

Thermal

VSS

Thermal

VSS

Thermal

VSS

Thermal

VSS

Thermal

VSS

Thermal

VSS

Thermal

VSS

Thermal

VSS

Thermal

VSS

Thermal

VSSQ

VSS

RFU

DQ4

DQ6

DQ7

DQ17

DQ19

DQS2

DQ21

DQ22

CAS

RAS

DM0

VDDQ

DQ5

VDDQ

DQ16

DQ18

DM2

DQ20

DQ23

VDD

VDDQ

VDD

BA0

BA1

DQ3

VDDQ

DQ31

DQ1

A10

VDD

DQ2

VDDQ

VDD

A11

DQ0

VDDQ

VDD

DQ29

DQ30

DQ28

VDDQ

VSS

VDDQ

VDD

A8/AP

DM3

VDDQ

DQ26

VDDQ

DQ15

DQ13

DM1

DQ11

DQ9

CKE

DQS3

DQ27

DQ25

DQ24

DQ14

DQ12

DQS1

DQ10

DQ8

VREF

NOTE:
1. RFU1 is reserved for A12
2. RFU2 is reserved for BA2
3. VSS Thermal balls are optional

MCL

128M DDR SDRAM

K4D26323RA-GC

* VDD / VDDQ=2.8V *

- 6 -

Rev. 2.0 (Jan. 2003)

INPUT/OUTPUT FUNCTIONAL DESCRIPTION

*1 : The timing reference point for the differential clocking is the cross point of CK and CK.
For any applications using the single ended clocking, apply V

REF

to CK pin.

Symbol

Type

Function

CK, CK*1

Input

The differential system clock Input.
All of the inputs are sampled on the rising edge of the clock except
DQ

s and DM

s that are sampled on both edges of the DQS.

CKE

Input

Activates the CK signal when high and deactivates the CK signal
when low. By deactivating the clock, CKE low indicates the Power
down mode or Self refresh mode.

Input

CS enables the command decoder when low and disabled the com-
mand decoder when high. When the command decoder is disabled,
new commands are ignored but previous operations continue.

RAS

Input

Latches row addresses on the positive going edge of the CK with
RAS low. Enables row access & precharge.

CAS

Input

Latches column addresses on the positive going edge of the CK with
CAS low. Enables column access.

Input

Enables write operation and row precharge.
Latches data in starting from CAS, WE active.

DQS

~ DQS

Input/Output

Data input and output are synchronized with both edge of DQS.
DQS

for DQ

~ DQ

DQS

for DQ

~ DQ

15,

DQS

for DQ

~ DQ

23,

DQS

for DQ

~ DQ

31.

~ DM

Input

Data In mask. Data In is masked by DM Latency=0 when DM is high
in burst write. DM

for DQ

~ DQ

for DQ

~ DQ

15,

for

~ DQ

23,

for DQ

~ DQ

31.

~ DQ

Input/Output

Data inputs/Outputs are multiplexed on the same pins.

, BA

Input

Selects which bank is to be active.

~ A

Input

Row/Column addresses are multiplexed on the same pins.
Row addresses : RA

~ RA

, Column addresses : CA

~ CA

Column address CA

is used for auto precharge.

Power Supply

Power and ground for the input buffers and core logic.

DDQ

SSQ

Power Supply

Isolated power supply and ground for the output buffers to provide
improved noise immunity.

REF

Power Supply

Reference voltage for inputs, used for SSTL interface.

NC/RFU

No connection/
Reserved for future use

This pin is recommended to be left "No connection" on the device

MCL

Must Connect Low

Must connect low

128M DDR SDRAM

K4D26323RA-GC

* VDD / VDDQ=2.8V *

- 7 -

Rev. 2.0 (Jan. 2003)

BLOCK DIAGRAM

(1Mbit x 32I/O x 4 Bank)

Bank Select

Timing Register

Address Re

gister

Refresh Counter

Row

Buf

f
er

Row Decoder

Col.

u
f
f
er

Data Input Register

Serial to parallel

1Mx32

Sense AMP

2-bit pre

f
etch

Output Buf

f
er

I/O Control

Column Decoder

Latency & Burst Length

Programming Register

t
robe

Gen.

CK,CK

ADDR

LCKE

CK,CK

CKE

RAS

CAS

DMi

LDMi

CK,CK

LCAS

LRAS LCBR

LWE

LWCBR

LRAS

LCBR

CK, CK

LWE

LDMi

x32

DQi

Data Strobe

Intput Buffer

DLL

(DQS0~DQS3)

128M DDR SDRAM

K4D26323RA-GC

* VDD / VDDQ=2.8V *

- 8 -

Rev. 2.0 (Jan. 2003)

· Power-Up Sequence

DDR SDRAMs must be powered up and initialized in a predefined manner to prevent undefined operations.

1. Apply power and keep CKE at low state (All other inputs may be undefined)
- Apply VDD before VDDQ .
- Apply VDDQ before VREF & VTT
2. Start clock and maintain stable condition for minimum 200us.
3. The minimum of 200us after stable power and clock(CK,CK ), apply NOP and take CKE to be high .
4. Issue precharge command for all banks of the device.
5. Issue a EMRS command to enable DLL

6. Issue a MRS command to reset DLL. The additional 200 clock cycles are required to lock the DLL.

1,2

7. Issue precharge command for all banks of the device.

8. Issue at least 2 or more auto-refresh commands.
9. Issue a mode register set command with A8 to low to initialize the mode register.

*1 The additional 200cycles of clock input is required to lock the DLL after enabling DLL.
*2 Sequence of 6&7 is regardless of the order.

FUNCTIONAL DESCRIPTION

Power up & Initialization Sequence

Command

tRP

2 Clock min.

precharge

ALL Banks

2nd Auto

Refresh

Mode

Any

Command

RFC

1st Auto

Refresh

RFC

EMRS

MRS

2 Clock min.

DLL Reset

~ ~

precharge

ALL Banks

Inputs must be

stable for 200us

200 Clock min.

~ ~

2 Clock min.

CK,CK

* When the operating frequency is changed, DLL reset should be required again.

After DLL reset again, the minimum 200 cycles of clock input is needed to lock the DLL.

128M DDR SDRAM

K4D26323RA-GC

* VDD / VDDQ=2.8V *

- 9 -

Rev. 2.0 (Jan. 2003)

The mode register stores the data for controlling the various operating modes of DDR SDRAM. It programs CAS latency,

addressing mode, burst length, test mode, DLL reset and various vendor specific options to make DDR SDRAM useful for
variety of different applications. The default value of the mode register is not defined, therefore the mode register must be
written after EMRS setting for proper operation. The mode register is written by asserting low on CS, RAS, CAS and
WE(The DDR SDRAM should be in active mode with CKE already high prior to writing into the mode register). The state of
address pins A

~ A

and BA

, BA

in the same cycle as CS, RAS, CAS and WE going low is written in the mode register.

Minimum two clock cycles are requested to complete the write operation in the mode register. The mode register contents
can be changed using the same command and clock cycle requirements during operation as long as all banks are in the
idle state. The mode register is divided into various fields depending on functionality. The burst length uses A

~ A

addressing mode uses A

, CAS latency(read latency from column address) uses A

~ A

. A

is used for test mode. A

used for DLL reset. A

, BA

and BA

must be set to low for normal MRS operation. Refer to the table for specific codes

for various burst length, addressing modes and CAS latencies.

MODE REGISTER SET(MRS)

Address Bus

Mode Register

CAS Latency

Latency

Reserved

Burst Length

Burst Type

Sequential

Interleave

Reserve

Full page

Reserve

Burst Type

Type

Sequential

Interleave

* RFU(Reserved for future use)

should stay "0" during MRS
cycle.

MRS Cycle

Command

*1 : MRS can be issued only at all banks precharge state.
*2 : Minimum

is required to issue MRS command.

CK, CK

Precharge

NOP

MRS

NOP

Any

NOP

All Banks

Command

MRD

=2 t

RFU

DLL

CAS Latency

Burst Length

~ A

MRS

EMRS

DLL

DLL Reset

Yes

Test Mode

mode

Normal

Test

NOP

128M DDR SDRAM

K4D26323RA-GC

* VDD / VDDQ=2.8V *

- 10 -

Rev. 2.0 (Jan. 2003)

The extended mode register stores the data for enabling or disabling DLL and selecting output driver

strength. The default value of the extended mode register is not defined, therefore the extened mode register
must be written after power up for enabling or disabling DLL. The extended mode register is written by assert-
ing low on CS, RAS, CAS, WE and high on BA0(The DDR SDRAM should be in all bank precharge with CKE
already high prior to writing into the extended mode register). The state of address pins A0, A2 ~ A5, A7 ~ A11
and BA1 in the same cycle as CS, RAS, CAS and WE going low are written in the extended mode register. A1
and A6 are used for setting driver strength to normal, weak or matched impedance. Two clock cycles are
required to complete the write operation in the extended mode register. The mode register contents can be
changed using the same command and clock cycle requirements during operation as long as all banks are in
the idle state. A0 is used for DLL enable or disable. "High" on BA0 is used for EMRS. All the other address
pins except A0,A1,A6 and BA0 must be set to low for proper EMRS operation. Refer to the table for specific
codes.

DLL Enable

Enable

Disable

~ A

MRS

EMRS

Figure 7. Extended Mode Register set

EXTENDED MODE REGISTER SET(EMRS)

Address Bus

Extended

*1 : RFU(Reserved for future use) should stay "0" during EMRS cycle.

Output Driver Impedence Control

N/A

Do not use

Weak

60%

N/A

Do not use

N/A

Do not use

RFU

D.I.C

RFU

D.I.C

DLL

Mode Register

128M DDR SDRAM

K4D26323RA-GC

* VDD / VDDQ=2.8V *

- 11 -

Rev. 2.0 (Jan. 2003)

Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

Note :

POWER & DC OPERATING CONDITIONS(SSTL_2 In/Out)

Recommended operating conditions(Voltage referenced to V

=0V, T

=0 to 65

Parameter

Symbol

Min

Typ

Max

Unit

Note

Device Supply voltage

2.66

2.8

2.94

1,7

Output Supply voltage

DDQ

2.66

2.8

2.94

1,7

Reference voltage

REF

0.49*V

DDQ

0.51*V

DDQ

Termination voltage

Vtt

REF

-0.04

REF

+0.04

Input logic high voltage

IH(DC)

REF

+0.15

DDQ

+0.30

Input logic low voltage

IL(DC)

-0.30

REF

-0.15

Output logic high voltage

Vtt+0.76

=-15.2mA

Output logic low voltage

Vtt-0.76

=+15.2mA

Input leakage current

-5

Output leakage current

-5

ABSOLUTE MAXIMUM RATINGS

Parameter

Symbol

Value

Unit

Voltage on any pin relative to Vss

, V

OUT

-0.5 ~ 3.6

Voltage on V

supply relative to Vss

-1.0 ~ 3.6

Voltage on V

supply relative to Vss

DDQ

-0.5 ~ 3.6

Storage temperature

STG

-55 ~ +150

Power dissipation

3.3

Short circuit current

1. Under all conditions V

DDQ

must be less than or equal to V

2. V

REF

is expected to equal 0.50*V

DDQ

of the transmitting device and to track variations in the DC level of the same. Peak to

peak noise on the V

REF

may not exceed +

2% of the DC value.

3. V

of the transmitting device must track V

REF

of the receiving device.

4. V

(max.)= V

DDQ

+1.5V for a pulse width and it can not be greater than 1/3 of the cycle rate.

5. V

(mim.)= -1.5V for a pulse width and it can not be greater than 1/3 of the cycle rate.

6. For any pin under test input of 0V < V

< V

is acceptable. For all other pins that are not under test V

=0V.

7. For K4D26323RA-GC2A/33/36, V

DD/

DDQ=

2.8V

Note :

128M DDR SDRAM

K4D26323RA-GC

* VDD / VDDQ=2.8V *

- 12 -

Rev. 2.0 (Jan. 2003)

DC CHARACTERISTICS

Note : 1. Measured with outputs open.

2. Refresh period is 32ms.

Parameter

Symbol

Test Condition

Version

Unit Note

-2A

-33

-36

Operating Current
(One Bank Active)

CC1

Burst Lenth=2

(min)

=0mA,

(min)

500

480

460

Precharge Standby Current
in Power-down mode

CC2

CKE

(max),

(min)

Precharge Standby Current
in Non Power-down mode

CC2

CKE

(min), CS

(min),

(min)

145

130

120

Active Standby Current
power-down mode

CC3

CKE

(max),

(min)

140

130

120

Active Standby Current in
in Non Power-down mode

CC3

CKE

VIH(min), CS

VIH(min),

(min)

400

350

320

Operating Current
( Burst Mode)

CC4

=0mA ,

(min),

Page Burst, All Banks activated.

940

840

800

Refresh Current

CC5

RFC

(min)

330

320

310

Self Refresh Current

CC6

CKE

0.2V

Operating Current
(4Bank interleaving)

CC7

Burst Length=4

(min)

=0mA,

(min)

1200

1080

1000

Recommended operating conditions Unless Otherwise Noted, T

=0 to 65

1. V

is the magnitude of the difference between the input level on CK and the input level on CK

2. The value of V

is expected to equal 0.5*V

DDQ

of the transmitting device and must track variations in the DC level of the same

Note :

AC INPUT OPERATING CONDITIONS

Recommended operating conditions(Voltage referenced to V

=0V, V

=2.8V+

5%, V

DDQ

=2.8V+

5%,T

=0 to 65

Parameter

Symbol

Min

Typ

Max

Unit

Note

Input High (Logic 1) Voltage; DQ

REF

+0.4

Input Low (Logic 0) Voltage; DQ

REF

-0.4

Clock Input Differential Voltage; CK and CK

0.8

DDQ

+0.6

Clock Input Crossing Point Voltage; CK and CK

0.5*V

DDQ

-0.2

0.5*V

DDQ

+0.2

128M DDR SDRAM

K4D26323RA-GC

* VDD / VDDQ=2.8V *

- 13 -

Rev. 2.0 (Jan. 2003)

=50

Output

LOAD

=30pF

(Fig. 1) Output Load Circuit

Z0=50

REF

=0.5*V

DDQ

=0.5*V

DDQ

DECOUPLING CAPACITANCE GUIDE LINE

Recommended decoupling capacitance added to power line at board.

Parameter

Symbol

Value

Unit

Decoupling Capacitance between V

and V

DC1

0.1 + 0.01

Decoupling Capacitance between V

DDQ

and V

SSQ

DC2

0.1 + 0.01

1. V

and V

DDQ

pins are separated each other.

All V

pins are connected in chip. All V

DDQ

pins are connected in chip.

2. V

and V

SSQ

pins are separated each other

All V

pins are connected in chip. All V

SSQ

pins are connected in chip.

Note :

AC OPERATING TEST CONDITIONS

=2.8V

5%, T

= 0 to 65

Parameter

Value

Unit

Note

Input reference voltage for CK(for single ended)

0.50*V

DDQ

CK and CK signal maximum peak swing

1.5

CK signal minimum slew rate

1.0

V/ns

Input Levels(V

)

REF

+0.4/V

REF

-0.4

Input timing measurement reference level

REF

Output timing measurement reference level

Output load condition

See Fig.1

CAPACITANCE

=2.5V, T

= 25

f=1MHz)

Parameter

Symbol

Min

Max

Unit

Input capacitance(

CK, CK )

IN1

1.0

5.0

Input capacitance(A

, BA

~BA

)

IN2

1.0

4.0

Input capacitance
(

CKE, CS, RAS,CAS, WE )

IN3

1.0

4.0

Data & DQS input/output capacitance(DQ

~DQ

)

OUT

1.0

6.5

Input capacitance(DM0 ~ DM3)

IN4

1.0

6.5

128M DDR SDRAM

K4D26323RA-GC

* VDD / VDDQ=2.8V *

- 14 -

Rev. 2.0 (Jan. 2003)

AC CHARACTERISTICS

Simplified Timing @ BL=2, CL=4

Parameter

Sym-

bol

-2A

-33

-36

Unit Note

Min

Max

Min

Max

Min

Max

CK cycle time

CL=3

CL=4

2.86

3.3

3.6

CK high level width

0.45

0.55

0.45

0.55

0.45

0.55

tCK

CK low level width

0.45

0.55

0.45

0.55

0.45

0.55

tCK

DQS out access time from CK

DQSCK

-0.6

0.6

-0.6

0.6

-0.6

0.6

Output access time from CK

-0.6

0.6

-0.6

0.6

-0.6

0.6

Data strobe edge to Dout edge

DQSQ

0.35

0.40

Read preamble

RPRE

0.9

1.1

0.9

1.1

0.9

1.1

tCK

Read postamble

RPST

0.4

0.6

0.4

0.6

0.4

0.6

tCK

CK to valid DQS-in

DQSS

0.85

1.15

0.85

1.15

0.85

1.15

tCK

DQS-In setup time

WPRES

DQS-in hold time

WPREH

0.35

tCK

DQS write postamble

WPST

0.4

0.6

0.4

0.6

0.4

0.6

tCK

DQS-In high level width

DQSH

0.4

0.6

0.4

0.6

0.4

0.6

tCK

DQS-In low level width

DQSL

0.4

0.6

0.4

0.6

0.4

0.6

tCK

Address and Control input setup

0.9

Address and Control input hold

0.9

DQ and DM setup time to DQS

0.35

0.40

DQ and DM hold time to DQS

0.35

0.40

Clock half period

tCLmin

tCHmin

tCLmin

tCHmin

tCLmin

tCHmin

Data output hold time from DQS

tHP-0.35

tHP-

0.4

tCL

tCK

CK, CK

DQS

tIS

tIH

tDS tDH

tRPST

tRPRE

Db0

Db1

tDQSS

tDQSH

tDQSL

tCH

Qa1

Qa2

COMMAND

READA

WRITEB

tDQSQ

WPRES

WPREH

tDQSCK

tAC

128M DDR SDRAM

K4D26323RA-GC

* VDD / VDDQ=2.8V *

- 15 -

Rev. 2.0 (Jan. 2003)

Note 1 :
- The JEDEC DDR specification currently defines the output data valid window(tDV) as the time period when the data
strobe and all data associated with that data strobe are coincidentally valid.
- The previously used definition of tDV(=0.35tCK) artificially penalizes system timing budgets by assuming the worst case
output vaild window even then the clock duty cycle applied to the device is better than 45/55%
- A new AC timing term, tQH which stands for data output hold time from DQS is difined to account for clock duty cycle
variation and replaces tDV
- tQHmin = tHP-X where
. tHP=Minimum half clock period for any given cycle and is defined by clock high or clock low time(tCH,tCL)
. X=A frequency dependent timing allowance account for tDQSQmax

tQH Timing (CL4, BL2)

tHP

CK, CK

DQS

COMMAND

READA

tQH

Qa0

tDQSQ(max)

Qa1

128M DDR SDRAM

K4D26323RA-GC

* VDD / VDDQ=2.8V *

- 16 -

Rev. 2.0 (Jan. 2003)

AC CHARACTERISTICS (II)

K4D26323RA-GC2A

Frequency

Cas Latency

tRC

tRFC

tRAS

tRCDRD tRCDWR

tRP

tRRD

tDAL

Unit

350MHz ( 2.86ns )

tCK

300MHz ( 3.3ns )

tCK

275MHz ( 3.6ns )

tCK

K4D26323RA-GC33

Frequency

Cas Latency

tRC

tRFC

tRAS

tRCDRD tRCDWR

tRP

tRRD

tDAL

Unit

300MHz ( 3.3ns )

tCK

275MHz ( 3.6ns )

tCK

(Unit : Number of Clock)

AC CHARACTERISTICS (I)

Note : 1. For normal write operation, even numbers of Din are to be written inside DRAM

Parameter

Sym-

bol

-2A

-33

-36

Unit Note

Min

Max

Min

Max

Min

Max

Row cycle time

tCK

Refresh row cycle time

RFC

tCK

Row active time

RAS

100K

tCK

RAS to CAS delay for Read

RCDRD

tCK

RAS to CAS delay for Write

RCDWR

tCK

Row precharge time

tCK

Row active to Row active

RRD

tCK

Last data in to Row precharge
@Normal Precharge

tCK

Last data in to Row precharge
@Auto Precharge

WR_A

tCK

Last data in to Read command

CDLR

tCK

Col. address to Col. address

CCD

tCK

Mode register set cycle time

MRD

tCK

Auto precharge write recovery
+ Precharge

DAL

tCK

Exit self refresh to read com-

XSR

200

tCK

Power down exit time

PDEX

1tCK+tIS

Refresh interval time

REF

7.8

K4D26323RA-GC36

Frequency

Cas Latency

tRC

tRFC

tRAS

tRCDRD tRCDWR

tRP

tRRD

tDAL

Unit

275MHz ( 3.6ns )

tCK

128M DDR SDRAM

K4D26323RA-GC

* VDD / VDDQ=2.8V *

- 17 -

Rev. 2.0 (Jan. 2003)

BAa

tRCD

ACTIVEA

ACTIVEB WRITEA

WRITEB

BAa

BAb

BAa

PRECH

BAa

Normal Write Burst

(@ BL=4)

Multi Bank Interleaving Write Burst

(@ BL=4)

BAa

BAb

tRAS

tRC

tRP

tRRD

COMMAND

DQS

CK, CK

A8/AP

ADDR

(A0~A7,

BA[1:0]

A9,A10)

ACTIVEA

WRITEA

Da0 Da1 Da2 Da3

Simplified Timing(2) @ BL=4

Db0 Db1

Db3

Da0 Da1 Da2 Da3

Db2

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