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Электронный компонент: K4D28163HD-TC36

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128M DDR SDRAM
K4D28163HD
- 1 -
Rev. 1.4(Aug. 2002)
128Mbit DDR SDRAM
Revision 1.4
August 2002
2M x 16Bit x 4 Banks
Double Data Rate Synchronous DRAM
Samsung Electronics reserves the right to change products or specification without notice.
128M DDR SDRAM
K4D28163HD
- 2 -
Rev. 1.4(Aug. 2002)
Revision History
Revision 1.4 (August 13, 2002)
Changed ICC3P
Typo corrected
Changed refresh period of K4D28163HD-TC36/40 from 4K/64ms to 4K/32ms.
Revision 1.3 (May 29, 2002)
Added K4D28163HD-TC36 (275MHz)
Revision 1.2 (May 8, 2002)
Typo corrected
Revision 1.1 (January 7, 2002)
Increased Icc2N by 20mA
Revision 1.0 (December 22, 2001)
Defined DC spec.
Revision 0.4 (December 10, 2001) -
Target Spec
Removed Full page Burst Length from the spec.
Revision 0.3 (November 6, 2001) -
Target Spec
Removed K4D28163HD-TC45/55 from the spec.
Revision 0.2 (October 25, 2001) -
Target Spec
Removed K4D28163HD-TC33/36 from the spec.
Revision 0.1 (October 12, 2001) -
Target Spec
Changed V
DD
from 3.3V + 10% to 3.3V + 5%
Revision 0.0 (October 10, 2001) -
Target Spec
Defined Target Specification
128M DDR SDRAM
K4D28163HD
- 3 -
Rev. 1.4(Aug. 2002)
The K4D28163HD is 134,217,728 bits of hyper synchronous data rate Dynamic RAM organized as 4 x 2.097,152 words
by 16 bits, fabricated with SAMSUNG
'
s high performance CMOS technology. Synchronous features with Data Strobe allow
extremely high performance up to 1.1GB/s/chip. I/O transactions are possible on both edges of the clock cycle. Range of
operating frequencies, programmable burst length and programmable latencies allow the device to be useful for a variety
of high performance memory system applications.
3.3V + 5% power supply for device operation
2.5V + 5% power supply for I/O interface
SSTL_2 compatible inputs/outputs
4 banks operation
MRS cycle with address key programs
-. Read latency 3 (clock)
-. Burst length (2, 4 and 8)
-. Burst type (sequential & interleave)
All inputs except data & DM are sampled at the positive
going edge of the system clock
Differential clock input
No Wrtie-Interrupted by Read Function
GENERAL DESCRIPTION
FEATURES
2 DQS's ( 1DQS / Byte )
Data I/O transactions on both edges of Data strobe
DLL aligns DQ and DQS transitions with Clock transition
Edge aligned data & data strobe output
Center aligned data & data strobe input
DM for write masking only
Auto & Self refresh
32ms refresh period (4K cycle) for -36/-40
64ms refresh period (4K cycle) for -50/-60
66pin TSOP-II
Maximum clock frequency up to 275MHz
Maximum data rate up to 550Mbps/pin
FOR 2M x 16Bit x 4 Bank DDR SDRAM
2M x 16Bit x 4 Banks Double Data Rate Synchronous DRAM
with Bi-directional Data Strobe and DLL
ORDERING INFORMATION
Part NO.
Max Freq.
Max Data Rate
Interface
Package
K4D28163HD-TC36
275MHz
550Mbps/pin
SSTL_2
66pin TSOP-II
K4D28163HD-TC40
250MHz
500Mbps/pin
K4D28163HD-TC50
200MHz
400Mbps/pin
K4D28163HD-TC60
166MHz
333Mbps/pin
128M DDR SDRAM
K4D28163HD
- 4 -
Rev. 1.4(Aug. 2002)
PIN CONFIGURATION
(Top View)
PIN DESCRIPTION
CK,CK
Differential Clock Input
BA
0
, BA
1
Bank Select Address
CKE
Clock Enable
A
0
~A
11
Address Input
CS
Chip Select
DQ
0
~ DQ
15
Data Input/Output
RAS
Row Address Strobe
V
DD
Power
CAS
Column Address Strobe
V
SS
Ground
W E
Write Enable
V
DDQ
Power for DQ
'
s
LDQS,UDQS
Data Strobe
V
SSQ
Ground for DQ
'
s
LDM,UDM
Data Mask
NC
No Connection
RFU
Reserved for Future Use
1
66 PIN TSOP(II)
(400mil x 875mil)
2
3
4
5
6
7
8
9
10
11
12
20
19
18
17
16
15
14
13
27
26
25
24
23
22
21
54
53
52
51
50
49
48
47
46
45
44
43
35
36
37
38
39
40
41
42
55
56
57
58
59
60
34
(0.65 mm Pin Pitch)
33
32
31
30
29
28
61
62
63
64
65
66
V
DD
DQ
0
V
D D Q
DQ
1
DQ
2
V
S S Q
DQ
3
DQ
4
V
D D Q
DQ
5
DQ
6
V
S S Q
BA
0
CS
RAS
CAS
WE
LDM
V
D D Q
DQ
7
V
DD
A
3
A
2
A
1
A
0
AP/A
1 0
BA
1
NC
LDQS
NC
NC
NC
V
DD
V
S S
DQ
1 5
V
S S Q
DQ
1 4
DQ
1 3
V
DDQ
DQ
1 2
DQ
1 1
V
S S Q
DQ
1 0
DQ
9
V
DDQ
A
1 1
CKE
CK
UDM
V
R E F
V
S S Q
DQ
8
V
S S
A
4
A
5
A
6
A
7
A
8
A
9
NC
UDQS
NC
V
S S
CK
NC
NC
128M DDR SDRAM
K4D28163HD
- 5 -
Rev. 1.4(Aug. 2002)
INPUT/OUTPUT FUNCTIONAL DESCRIPTION
*1 : The timing reference point for the differential clocking is the cross point of CK and CK.
For any applications using the single ended clocking, apply V
REF
to CK pin.
Symbol
Type
Function
CK, CK*1
Input
The differential system clock Input.
All of the inputs are sampled on the rising edge of the clock except
DQ
'
s and DM
'
s that are sampled on both edges of the DQS.
CKE
Input
Activates the CK signal when high and deactivates the CK signal
when low. By deactivating the clock, CKE low indicates the Power
down mode or Self refresh mode.
CS
Input
CS enables the command decoder when low and disabled the com-
mand decoder when high. When the command decoder is disabled,
new commands are ignored but previous operations continue.
RAS
Input
Latches row addresses on the positive going edge of the CK with
RAS low. Enables row access & precharge.
CAS
Input
Latches column addresses on the positive going edge of the CK with
CAS low. Enables column access.
WE
Input
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
LDQS,(U)DQS
Input/Output
Data input and output are synchronized with both edge of DQS.
For the x16, LDQS corresponds to the data on DQ0-DQ7 ; UDQS
corresponds to the data on DQ8-DQ15.
LDM,UDM
Input
Data in Mask. Data In is masked by DM Latency=0 when DM is
high in burst write. For the x16, LDM corresponds to the data on
DQ0-DQ7 ; UDM correspons to the data on DQ8-DQ15.
DQ
0
~ DQ
15
Input/Output
Data inputs/Outputs are multiplexed on the same pins.
BA
0
, BA
1
Input
Selects which bank is to be active.
A
0
~ A
11
Input
Row/Column addresses are multiplexed on the same pins.
Row addresses : RA
0
~ RA
11
, Column addresses : CA
0
~ CA
8
.
V
DD
/V
SS
Power Supply
Power and ground for the input buffers and core logic.
V
DDQ
/V
SSQ
Power Supply
Isolated power supply and ground for the output buffers to provide
improved noise immunity.
V
REF
Power Supply
Reference voltage for inputs, used for SSTL interface.
NC/RFU
No connection/
Reserved for future use
This pin is recommended to be left "No connection" on the device