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Электронный компонент: K4D553238F-GC

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256M GDDR SDRAM
K4D553238F-GC
- 1 -
Rev 1.3 (Mar. 2005)
256Mbit GDDR SDRAM
Revision 1.3
March 2005
Samsung Electronics reserves the right to change products or specification without notice.
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL
INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure could result in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
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256M GDDR SDRAM
K4D553238F-GC
- 2 -
Rev 1.3 (Mar. 2005)
Revision History
Revision 1.3(March 11, 2005)
Typo corrected
Revision 1.2(February 23, 2005)
Typo corrected
Revision 1.1 (December 29, 2004)
Typo corrected
Revision 1.0 (November 11, 2004)
Defined DC specification
Changed AC spec format
Revision 0.0 (September 7, 2004) -
Target Spec
Defined target specification
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256M GDDR SDRAM
K4D553238F-GC
- 3 -
Rev 1.3 (Mar. 2005)
The K4D553238F is 268,435,456 bits of hyper synchronous data rate Dynamic RAM organized as 4 x 2,097,152 words by
32 bits, fabricated with SAMSUNG
'
s high performance CMOS technology. Synchronous features with Data Strobe allow
extremely high performance up to 2.8GB/s/chip. I/O transactions are possible on both edges of the clock cycle. Range of
operating frequencies, programmable burst length and programmable latencies allow the device to be useful for a variety
of high performance memory system applications.
2.5V 5% power supply for device operation
2.5V 5% power supply for I/O interface
SSTL_2 compatible inputs/outputs
4 banks operation
MRS cycle with address key programs
-. Read latency 4, 5 and 6 (clock)
-. Burst length (2, 4 and 8)
-. Burst type (sequential & interleave)
All inputs except data & DM are sampled at the positive
going edge of the system clock
Differential clock input
GENERAL DESCRIPTION
FEATURES
No Wrtie-Interrupted by Read Function
4 DQS's ( 1DQS / Byte )
Data I/O transactions on both edges of Data strobe
DLL aligns DQ and DQS transitions with Clock transition
Edge aligned data & data strobe output
Center aligned data & data strobe input
DM for write masking only
Auto & Self refresh
32ms refresh period (4K cycle)
144-Ball FBGA
Maximum clock frequency up to 350MHz
Maximum data rate up to 700Mbps/pin
FOR 2M x 32Bit x 4 Bank DDR SDRAM
2M x 32Bit x 4 Banks Graphic Double Data Rate Synchronous DRAM
with Bi-directional Data Strobe and DLL
ORDERING INFORMATION
* K4D553238F-VC is the Lead Free package part number.
Part NO.
Max Freq.
Max Data Rate
Interface
Package
K4D553238F-GC2A
350MHz
700Mbps/pin
SSTL_2
144-Ball FBGA
K4D553238F-GC33
300MHz
600Mbps/pin
K4D553238F-GC36
275MHz
550Mbps/pin
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256M GDDR SDRAM
K4D553238F-GC
- 4 -
Rev 1.3 (Mar. 2005)
PIN CONFIGURATION
(Top View)
PIN DESCRIPTION
CK,CK
Differential Clock Input
BA
0
, BA
1
Bank Select Address
CKE
Clock Enable
A
0
~A
11
Address Input
CS
Chip Select
DQ
0
~ DQ
31
Data Input/Output
RAS
Row Address Strobe
V
DD
Power
CAS
Column Address Strobe
V
SS
Ground
WE
Write Enable
V
DDQ
Power for DQ
'
s
DQS
Data Strobe
V
SSQ
Ground for DQ
'
s
DM
Data Mask
NC
No Connection
RFU
Reserved for Future Use
MCL
Must Connect Low
DQS0
VSS
RFU
1
Thermal
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
RFU
2
A5
A6
DQ4
DQ6
DQ7
DQ17
DQ19
DQS2
DQ21
DQ22
CAS
RAS
CS
DM0
VDDQ
DQ5
VDDQ
DQ16
DQ18
DM2
DQ20
DQ23
WE
NC
NC
NC
VDD
VDDQ
VDDQ
NC
VDDQ
VDDQ
VDD
NC
BA0
BA1
A0
DQ3
VDDQ
DQ31
DQ1
A10
A2
A1
VDD
VDD
VDD
DQ2
VDDQ
VDD
A11
A3
A9
A4
DQ0
VDDQ
VDD
DQ29
DQ30
DQ28
VDDQ
NC
VSS
A7
VDDQ
VDDQ
NC
VDDQ
VDDQ
VDD
CK
A8/AP
DM3
VDDQ
DQ26
VDDQ
DQ15
DQ13
DM1
DQ11
DQ9
NC
CK
CKE
DQS3
DQ27
DQ25
DQ24
DQ14
DQ12
DQS1
DQ10
DQ8
NC
VREF
2
3
4
5
6
7
8
9
10
11
12
13
B
C
D
E
F
G
H
J
K
L
M
N
NOTE:
1. RFU1 is reserved for A12
2. RFU2 is reserved for BA2
3. VSS Thermal balls are optional
MCL
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256M GDDR SDRAM
K4D553238F-GC
- 5 -
Rev 1.3 (Mar. 2005)
INPUT/OUTPUT FUNCTIONAL DESCRIPTION
*1 : The timing reference point for the differential clocking is the cross point of CK and CK.
For any applications using the single ended clocking, apply V
REF
to CK pin.
Symbol
Type
Function
CK, CK*1
Input
The differential system clock Input.
All of the inputs are sampled on the rising edge of the clock except
DQ
'
s and DM
'
s that are sampled on both edges of the DQS.
CKE
Input
Activates the CK signal when high and deactivates the CK signal
when low. By deactivating the clock, CKE low indicates the Power
down mode or Self refresh mode.
CS
Input
CS enables the command decoder when low and disabled the com-
mand decoder when high. When the command decoder is disabled,
new commands are ignored but previous operations continue.
RAS
Input
Latches row addresses on the positive going edge of the CK with
RAS low. Enables row access & precharge.
CAS
Input
Latches column addresses on the positive going edge of the CK with
CAS low. Enables column access.
WE
Input
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
DQS
0
~ DQS
3
Input/Output
Data input and output are synchronized with both edge of DQS.
DQS
0
for DQ
0
~ DQ
7,
DQS
1
for DQ
8
~ DQ
15,
DQS
2
for DQ
16
~ DQ
23,
DQS
3
for DQ
24
~ DQ
31.
DM
0
~ DM
3
Input
Data In mask. Data In is masked by DM Latency=0 when DM is high
in burst write. DM
0
for DQ
0
~ DQ
7,
DM
1
for DQ
8
~ DQ
15,
DM
2
for
DQ
16
~ DQ
23,
DM
3
for DQ
24
~ DQ
31.
DQ
0
~ DQ
31
Input/Output
Data inputs/Outputs are multiplexed on the same pins.
BA
0
, BA
1
Input
Selects which bank is to be active.
A
0
~ A
11
Input
Row/Column addresses are multiplexed on the same pins.
Row addresses : RA
0
~ RA
11
, Column addresses : CA
0
~ CA
7
, CA
9
Column address CA
8
is used for auto precharge.
V
DD
/V
SS
Power Supply
Power and ground for the input buffers and core logic.
V
DDQ
/V
SSQ
Power Supply
Isolated power supply and ground for the output buffers to provide
improved noise immunity.
V
REF
Power Supply
Reference voltage for inputs, used for SSTL interface.
NC/RFU
No connection/
Reserved for future use
This pin is recommended to be left "No connection" on the device
MCL
Must Connect Low
Must connect low
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256M GDDR SDRAM
K4D553238F-GC
- 6 -
Rev 1.3 (Mar. 2005)
BLOCK DIAGRAM
(1Mbit x 32I/O x 4 Bank)
Bank Select
Timing Register
Address Re
gister
Refresh Counter
Row
Buf
f
er
Row Decoder
Col.
B
u
f
f
er
Data Input Register
Serial to parallel
2Mx32
2Mx32
2Mx32
2Mx32
Sense AMP
2-bit pre
f
etch
Output Buf
f
er
I/O Control
Column Decoder
Latency & Burst Length
Programming Register
S
t
robe
Gen.
CK,CK
ADDR
LCKE
CK,CK
CKE
CS
RAS
CAS
WE
DMi
LDMi
CK,CK
LCAS
LRAS LCBR
LWE
LWCBR
LRAS
LCBR
CK, CK
64
64
32
32
LWE
LDMi
x32
DQi
Data Strobe
Intput Buffer
DLL
(DQS0~DQS3)
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256M GDDR SDRAM
K4D553238F-GC
- 7 -
Rev 1.3 (Mar. 2005)
Power-Up Sequence
DDR SDRAMs must be powered up and initialized in a predefined manner to prevent undefined operations.
1. Apply power and keep CKE at low state (All other inputs may be undefined)
- Apply VDD before VDDQ .
- Apply VDDQ before VREF & VTT
2. Start clock and maintain stable condition for minimum 200us.
3. The minimum of 200us after stable power and clock(CK,CK ), apply NOP and take CKE to be high .
4. Issue precharge command for all banks of the device.
5. Issue a EMRS command to enable DLL
(Minimum 20 clock cycles are recommended prior to MRS command, however not mandatory just in case tMRD met)
*1
6. Issue a MRS command to reset DLL. The additional 200 clock cycles are required to lock the DLL.
*
1,2
7. Issue precharge command for all banks of the device.
8. Issue at least 2 or more auto-refresh commands.
9. Issue a mode register set command with A8 to low to initialize the mode register.
*1 The additional 200cycles of clock input is required to lock the DLL after enabling DLL.
*2 Sequence of 6&7 is regardless of the order
FUNCTIONAL DESCRIPTION
Power up & Initialization Sequence
Command
tRP
tMRD
precharge
ALL Banks
2nd Auto
Refresh
Mode
Register Set
Any
Command
t
RFC
1st Auto
Refresh
t
RFC
EMRS
MRS
tMRD.
DLL Reset
precharge
ALL Banks
t
RP
Inputs must be
stable for 200us
~~
200 Clock min.
tMRD
CK,CK
* When the operating frequency is changed, DLL reset should be required again.
After DLL reset again, the minimum 200 cycles of clock input is needed to lock the DLL.
~~
~~
~~
~~
~~
~~
~~
~~
~~
~~
~~
~~
~~
~~
~~
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256M GDDR SDRAM
K4D553238F-GC
- 8 -
Rev 1.3 (Mar. 2005)
The mode register stores the data for controlling the various operating modes of DDR SDRAM. It programs CAS latency,
addressing mode, burst length, test mode, DLL reset and various vendor specific options to make DDR SDRAM useful for
variety of different applications. The default value of the mode register is not defined, therefore the mode register must be
written after EMRS setting for proper operation. The mode register is written by asserting low on CS, RAS, CAS and
WE(The DDR SDRAM should be in active mode with CKE already high prior to writing into the mode register). The state of
address pins A
0
~ A
11
and BA
0
, BA
1
in the same cycle as CS, RAS, CAS and WE going low is written in the mode register.
Minimum two clock cycles are requested to complete the write operation in the mode register. The mode register contents
can be changed using the same command and clock cycle requirements during operation as long as all banks are in the
idle state. The mode register is divided into various fields depending on functionality. The burst length uses A
0
~ A
2
,
addressing mode uses A
3
, CAS latency(read latency from column address) uses A
4
~ A
6
. A
7
is used for test mode. A
8
is
used for DLL reset. A
7,
A
8
, BA
0
and BA
1
must be set to low for normal MRS operation. Refer to the table for specific codes
for various burst length, addressing modes and CAS latencies.
MODE REGISTER SET(MRS)
Address Bus
Mode Register
CAS Latency
A
6
A
5
A
4
Latency
0
0
0
Reserved
0
0
1
Reserved
0
1
0
Reserved
0
1
1
3
1
0
0
4
1
0
1
Reserved
1
1
0
Reserved
1
1
1
Reserved
Burst Length
A
2
A
1
A
0
Burst Type
Sequential
Interleave
0
0
0
Reserved
Reserved
0
0
1
2
2
0
1
0
4
4
0
1
1
8
8
1
0
0
Reserved
Reserved
1
0
1
Reserved
Reserved
1
1
0
Reserved
Reserved
1
1
1
Reserved
Reserved
Burst Type
A
3
Type
0
Sequential
1
Interleave
* RFU(Reserved for future use)
should stay "0" during MRS
cycle.
MRS Cycle
Command
*1 : MRS can be issued only at all banks precharge state.
*2 : Minimum
t
RP
is required to issue MRS command.
0
CK, CK
Precharge
NOP
NOP
MRS
NOP
NOP
2
0
1
6
12
10
11
Any
NOP
All Banks
Command
t
RP
t
MRD
=4 t
CK
BA
1
BA
0
A
11
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
RFU
0
RFU
DLL
TM
CAS Latency
BT
Burst Length
BA
0
A
n
~ A
0
0
MRS
1
EMRS
DLL
A
8
DLL Reset
0
No
1
Yes
Test Mode
A
7
mode
0
Normal
1
Test
NOP
~~
~~
~~
~~
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256M GDDR SDRAM
K4D553238F-GC
- 9 -
Rev 1.3 (Mar. 2005)
The extended mode register stores the data for enabling or disabling DLL and selecting output driver
strength. The default value of the extended mode register is not defined, therefore the extened mode register
must be written after power up for enabling or disabling DLL. The extended mode register is written by assert-
ing low on CS, RAS, CAS, WE and high on BA0(The DDR SDRAM should be in all bank precharge with CKE
already high prior to writing into the extended mode register). The state of address pins A0, A2 ~ A5, A7 ~ A11
and BA1 in the same cycle as CS, RAS, CAS and WE going low are written in the extended mode register. A1
and A6 are used for setting driver strength to normal, weak or matched impedance. Two clock cycles are
required to complete the write operation in the extended mode register. The mode register contents can be
changed using the same command and clock cycle requirements during operation as long as all banks are in
the idle state. A0 is used for DLL enable or disable. "High" on BA0 is used for EMRS. All the other address
pins except A0,A1,A6 and BA0 must be set to low for proper EMRS operation. Refer to the table for specific
codes.
A
0
DLL Enable
0
Enable
1
Disable
BA
0
A
n
~ A
0
0
MRS
1
EMRS
Figure 7. Extended Mode Register set
EXTENDED MODE REGISTER SET(EMRS)
Address Bus
Extended
*1 : RFU(Reserved for future use) should stay "0" during EMRS cycle.
A
6
A
1
Output Driver Impedence Control
0
0
N/A
Do not use
0
1
Weak
60%
1
0
N/A
Do not use
1
1
Full
100%
RFU
1
RFU
D.I.C
RFU
D.I.C
DLL
BA
1
BA
0
A
11
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
Mode Register
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256M GDDR SDRAM
K4D553238F-GC
- 10 -
Rev 1.3 (Mar. 2005)
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
Note :
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Value
Unit
Voltage on any pin relative to Vss
V
IN
, V
OUT
-0.5 ~ 3.6
V
Voltage on V
DD
supply relative to Vss
V
DD
-1.0 ~ 3.6
V
Voltage on V
DD
supply relative to Vss
V
DDQ
-0.5 ~ 3.6
V
Storage temperature
T
STG
-55 ~ +150
C
Power dissipation
P
D
3.3
W
Short circuit current
I
OS
50
mA
POWER & DC OPERATING CONDITIONS(SSTL_2 In/Out)
Recommended operating conditions(Voltage referenced to V
SS
=0V, T
A
=0 to 65
C)
Parameter
Symbol
Min
Typ
Max
Unit
Note
Device Supply voltage
V
DD
2.375
2.5
2.625
V
1
Output Supply voltage
V
DDQ
2.375
2.5
2.625
V
1
Reference voltage
V
REF
0.49*V
DDQ
-
0.51*V
DDQ
V
2
Termination voltage
Vtt
V
REF
-0.04
V
REF
V
REF
+0.04
V
3
Input logic high voltage
V
IH(DC)
V
REF
+0.15
-
V
DDQ
+0.30
V
4
Input logic low voltage
V
IL(DC)
-0.30
-
V
REF
-0.15
V
5
Output logic high voltage
V
OH
Vtt+0.76
-
-
V
I
OH
=-15.2mA, 7
Output logic low voltage
V
OL
-
-
Vtt-0.76
V
I
OL
=+15.2mA, 7
Input leakage current
I
IL
-5
-
5
uA
6
Output leakage current
I
OL
-5
-
5
uA
6
1. Under all conditions VDDQ must be less than or equal to VDD.
2. VREF is expected to equal 0.50*VDDQ of the transmitting device and to track variations in the DC level of the same. Peak to
peak noise on the VREF may not exceed + 2% of the DC value.
3. Vtt of the transmitting device must track VREF of the receiving device.
4. VIH(max.)= VDDQ +1.5V for a pulse width and it can not be greater than 1/3 of the cycle rate.
5. VIL(mim.)= -1.5V for a pulse width and it can not be greater than 1/3 of the cycle rate.
6. For any pin under test input of 0V < VIN < VDD is acceptable. For all other pins that are not under test VIN=0V.
7. Output logic high voltage and low voltage is depend on output channel condition.
Note :
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256M GDDR SDRAM
K4D553238F-GC
- 11 -
Rev 1.3 (Mar. 2005)
DC CHARACTERISTICS
Note : 1. Measured with outputs open.
2. Refresh period is 32ms.
Parameter
Symbol
Test Condition
Version
Unit Note
-2A
-33
-36
Operating Current
(One Bank Active)
I
CC1
Burst Lenth=2
t
RC
t
RC
(min)
I
OL
=0mA,
t
CC
=
t
CC
(min)
340
310
290
mA
Precharge Standby Current
in Power-down mode
I
CC2
P
CKE
V
IL
(max),
t
CC
=
t
CC
(min)
15
15
15
mA
Precharge Standby Current
in Non Power-down mode
I
CC2
N
CKE
V
IH
(min), CS
V
IH
(min),
t
CC
=
t
CC
(min)
75
70
65
mA
Active Standby Current
power-down mode
I
CC3
P
CKE
V
IL
(max),
t
CC
=
t
CC
(min)
70
65
60
mA
Active Standby Current
in Non Power-down mode
I
CC3
N
CKE
VIH(min), CS
VIH(min),
t
CC
=
t
CC
(min)
240
220
210
mA
Operating Current
( Burst Mode)
I
CC4
I
OL
=0mA ,
t
CC
=
t
CC
(min),
Page Burst, All Banks activated.
400
370
360
mA
Refresh Current
I
CC5
t
RC
t
RFC
(min)
380
340
320
mA
1
Self Refresh Current
I
CC6
CKE
0.2V
10
10
10
mA
Operating Current
(4Bank interleaving)
I
CC7
Burst Length=4
t
RC
t
RC
(min)
I
OL
=0mA,
t
CC
=
t
CC
(min)
620
560
530
mA
Recommended operating conditions Unless Otherwise Noted, T
A
=0 to 65
C)
1. V
ID
is the magnitude of the difference between the input level on CK and the input level on CK
2. The value of V
IX
is expected to equal 0.5*V
DDQ
of the transmitting device and must track variations in the DC level of the same
Note :
AC INPUT OPERATING CONDITIONS
Recommended operating conditions(Voltage referenced to V
SS
=0V, T
A
=0 to 65
C)
Parameter
Symbol
Min
Typ
Max
Unit
Note
Input High (Logic 1) Voltage ;DQ
V
IH
V
REF
+0.35
-
-
V
Input Low (Logic 0) Voltage; DQ
V
IL
-
-
V
REF
-0.35
V
Clock Input Differential Voltage; CK and CK
V
ID
0.7
-
V
DDQ
+0.6
V
1
Clock Input Crossing Point Voltage; CK and CK
V
IX
0.5*V
DDQ
-0.2
-
0.5*V
DDQ
+0.2
V
2
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256M GDDR SDRAM
K4D553238F-GC
- 12 -
Rev 1.3 (Mar. 2005)
R
T
=50
Output
C
LOAD
=30pF
(Fig. 1) Output Load Circuit
Z0=50
V
REF
=0.5*V
DDQ
V
tt
=0.5*V
DDQ
DECOUPLING CAPACITANCE GUIDE LINE
Recommended decoupling capacitance added to power line at board.
Parameter
Symbol
Value
Unit
Decoupling Capacitance between V
DD
and V
SS
C
DC1
0.1 + 0.01
uF
Decoupling Capacitance between V
DDQ
and V
SSQ
C
DC2
0.1 + 0.01
uF
1. V
DD
and V
DDQ
pins are separated each other.
All V
DD
pins are connected in chip. All V
DDQ
pins are connected in chip.
2. V
SS
and V
SSQ
pins are separated each other
All V
SS
pins are connected in chip. All V
SSQ
pins are connected in chip.
Note :
AC OPERATING TEST CONDITIONS
(T
A
= 0 to 65
C)
Note 1 : In case of differential clocks(CK and CK ), input reference voltage for clock is a CK and CK's crossing point.
Parameter
Value
Unit
Note
Input reference voltage for CK(for single ended)
0.50*V
DDQ
V
1
CK and CK signal maximum peak swing
1.5
V
CK signal minimum slew rate
1.0
V/ns
Input Levels(V
IH
/V
IL
)
V
REF
+0.4/V
REF
-0.4
V
Input timing measurement reference level
V
REF
V
Output timing measurement reference level
V
tt
V
Output load condition
See Fig.1
CAPACITANCE
(T
A
= 25
C,
f=1MHz)
Parameter
Symbol
Min
Max
Unit
Input capacitance(
CK, CK )
C
IN1
1.0
5.0
pF
Input capacitance(A
0
~A
11
, BA
0
~BA
1
)
C
IN2
1.0
4.0
pF
Input capacitance
(
CKE, CS, RAS,CAS, WE )
C
IN3
1.0
4.0
pF
Data & DQS input/output capacitance(DQ
0
~DQ
31
)
C
OUT
1.0
6.5
pF
Input capacitance(DM0 ~ DM3)
C
IN4
1.0
6.5
pF
background image
256M GDDR SDRAM
K4D553238F-GC
- 13 -
Rev 1.3 (Mar. 2005)
1
3
4
6
7
tCL
tCK
CK, CK
DQS
DQ
CS
DM
2
5
tIS
tIH
8
tDS tDH
0
1
tRPST
tRPRE
Db0
Db1
tDQSS
tDQSH
tDQSL
tCH
Qa1
Qa2
COMMAND
READA
WRITEB
tDQSQ
t
WPRES
t
WPREH
tDQSCK
tAC
Simplified Timing @ BL=2, CL=4
AC CHARACTERISTICS
*1.
The cycle to cycle jitter over 1~6 cycle short term jitter.
Parameter
Symbol
-2A
-33
-36
Unit
Note
Min
Max
Min
Max
Min
Max
CK cycle time
CL=3
tCK
-
4
-
10
-
10
ns
CL=4
2.86
3.3
3.6
ns
CK high level width
tCH
0.45
0.55
0.45
0.55
0.45
0.55
tCK
CK low level width
tCL
0.45
0.55
0.45
0.55
0.45
0.55
tCK
DQS out access time from CK
tDQSCK
-0.55
0.55
-0.55
0.55
-0.6
0.6
ns
Output access time from CK
tAC
-0.55
0.55
-0.55
0.55
-0.6
0.6
ns
Data strobe edge to Dout edge
tDQSQ
-
0.35
-
0.35
-
0.40
ns
1
Read preamble
tRPRE
0.9
1.1
0.9
1.1
0.9
1.1
tCK
Read postamble
tRPST
0.4
0.6
0.4
0.6
0.4
0.6
tCK
CK to valid DQS-in
tDQSS
0.85
1.15
0.85
1.15
0.85
1.15
tCK
DQS-In setup time
tWPRES
0
-
0
-
0
-
ns
DQS-in hold time
tWPREH
0.35
-
0.35
-
0.35
-
tCK
DQS write postamble
tWPST
0.4
0.6
0.4
0.6
0.4
0.6
tCK
DQS-In high level width
tDQSH
0.45
0.55
0.45
0.55
0.45
0.55
tCK
DQS-In low level width
tDQSL
0.45
0.55
0.45
0.55
0.45
0.55
tCK
Address and Control input setup
tIS
0.8
-
0.8
-
0.9
-
ns
Address and Control input hold
tIH
0.8
-
0.8
-
0.9
-
ns
DQ and DM setup time to DQS
tDS
0.35
-
0.35
-
0.40
-
ns
DQ and DM hold time to DQS
tDH
0.35
-
0.35
-
0.40
-
ns
Clock half period
tHP
tCLmin
or
tCHmin
-
tCLmin
or
tCHmin
-
tCLmin
or
tCHmin
-
ns
1
Data Hold skew factor
tQHS
-
0.4
-
0.4
-
0.45
ns
Data output hold time from DQS
tQH
tHP-tQHS
-
tHP-tQHS
-
tHP-tQHS
-
ns
1
Jitter over 1~6 clock cycle error
tJ*1
-
75
-
85
-
95
ps
Cycle to cyde duty cycle error
tDCERR
-
75
-
85
-
95
ps
Rise and fall times of CK
tR, tF
-
600
-
700
-
700
ps
background image
256M GDDR SDRAM
K4D553238F-GC
- 14 -
Rev 1.3 (Mar. 2005)
Note 1 :
- The JEDEC DDR specification currently defines the output data valid window(tDV) as the time period when the data
strobe and all data associated with that data strobe are coincidentally valid.
- The previously used definition of tDV(=0.35tCK) artificially penalizes system timing budgets by assuming the worst case
output vaild window even then the clock duty cycle applied to the device is better than 45/55%
- A new AC timing term, tQH which stands for data output hold time from DQS is difined to account for clock duty cycle
variation and replaces tDV
- tQHmin = tHP-X where
. tHP=Minimum half clock period for any given cycle and is defined by clock high or clock low time(tCH,tCL)
. X=A frequency dependent timing allowance account for tDQSQmax
tQH Timing (CL4, BL2)
1
tHP
CK, CK
DQS
DQ
CS
2
5
0
1
COMMAND
READA
tQH
Qa0
tDQSQ(max)
tDQSQ(max)
3
4
Qa1
VALID
NOP
NOP
NOP
NOP
NOP
NOP
VALID
t
IS
t
IS
CK, CK
CKE
Command
Exit Powr Down mode
Enter Power Down mode
(Read or Write operation
must not be in progress)
3t
CK
Power Down Timing
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256M GDDR SDRAM
K4D553238F-GC
- 15 -
Rev 1.3 (Mar. 2005)
AC CHARACTERISTICS (I)
Note : 1. For normal write operation, even numbers of Din are to be written inside DRAM
2. The number of clock of tRP is restricted by the number of clock of tRAS and tRP
3. The number of clock of tWR_A is fixed. It can't be changed by tCK
4. tRCDWR is equal to tRCDRD-2tCK and the number of clock can not be lower than 2tCK.
5. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then
rounding off to the next higher integer unconditionally.
Parameter
Symbol
-2A
-33
-36
Unit
Note
Min
Max
Min
Max
Min
Max
Row cycle time
tRC
42.9
-
42.9
-
46.8
-
ns
2,5
Refresh row cycle time
tRFC
48.6
-
49.5
-
54
-
ns
5
Row active time
tRAS
28.6
100K
29.7
100K
32.4
100K
ns
5
RAS to CAS delay for Read
tRCDRD
13.2
-
13.2
-
14.4
-
ns
5
RAS to CAS delay for Write
tRCDWR
6.6
-
6.6
-
7.2
-
ns
4
Row precharge time
tRP
13.2
-
13.2
-
14.4
-
ns
5
Row active to Row active
tRRD
9.9
-
9.9
-
10.8
-
ns
5
Last data in to Row precharge
tWR
14.3
-
16.5
-
18
-
ns
5
Last data in to Row precharge
@Auto Precharge
tWR_A
5
-
5
-
5
-
tCK
3
Auto precharge write recovery +
Precharge
tDAL
10
-
9
-
9
-
tCK
3,5
Last data in to Read command
tCDLR
2
-
2
-
2
-
tCK
1
Col. address to Col. address
tCCD
1
-
1
-
1
-
tCK
Mode register set cycle time
tMRD
2
-
2
-
2
-
tCK
Exit self refresh to read command
tXSR
200
-
200
-
200
-
tCK
Power down exit time
tPDEX
3tCK+
tIS
-
3tCK+
tIS
-
3tCK+
tIS
-
ns
Refresh interval time
tREF
7.8
-
7.8
-
7.8
-
us
AC CHARACTERISTICS (II)
K4D553238F-GC2A
Frequency
Cas Latency
tRC
tRFC
tRAS
tRCDRD tRCDWR
tRP
tRRD
tDAL
Unit
350MHz ( 2.86ns )
4
15
17
10
5
3
5
4
10
tCK
300MHz ( 3.3ns )
4
13
15
9
4
2
4
3
9
tCK
275MHz ( 3.6ns )
4
13
15
9
4
2
4
3
9
tCK
K4D553238F-GC33
Frequency
Cas Latency
tRC
tRFC
tRAS
tRCDRD tRCDWR
tRP
tRRD
tDAL
Unit
300MHz ( 3.3ns )
4
13
15
9
4
2
4
3
9
tCK
275MHz ( 3.6ns )
4
13
15
9
4
2
4
3
9
tCK
K4D553238F-GC36
Frequency
Cas Latency
tRC
tRFC
tRAS
tRCDRD tRCDWR
tRP
tRRD
tDAL
Unit
275MHz ( 3.6ns )
4
13
15
9
4
2
4
3
9
tCK
background image
256M GDDR SDRAM
K4D553238F-GC
- 16 -
Rev 1.3 (Mar. 2005)
0
1
2
3
4
5
6
7
8
BAa
Ra
Ra
tRCD
ACTIVEA
ACTIVEB WRITEA
WRITEB
13
14
15
16
17
18
19
20
21
BAa
BAb
Ca
Cb
BAa
Ca
9
10
11
12
PRECH
BAa
22
Ra
Normal Write Burst
(@ BL=4)
Multi Bank Interleaving Write Burst
(@ BL=4)
BAa
Ra
Ra
BAb
Rb
Rb
tRAS
tRC
tRP
tRRD
COMMAND
DQS
DQ
WE
DM
CK, CK
A8/AP
ADDR
(A0~A7,
BA[1:0]
A9,A10)
ACTIVEA
WRITEA
Da0 Da1 Da2 Da3
Simplified Timing(2) @ BL=4
Db0 Db1
Db3
Da0 Da1 Da2 Da3
Db2
background image
256M GDDR SDRAM
K4D553238F-GC
- 17 -
Rev 1.3 (Mar. 2005)
PACKAGE DIMENSIONS (144-Ball FBGA)
Unit : mm
12.0
12.0
0.8
0.8