Preliminary

64M DDR SGRAM

K4D623237M

The K4D623237 is 67,108,864 bits of hyper synchronous data rate Dynamic GRAM organized as 4 x 524,288 words by 32

bits, fabricated with SAMSUNG

s high performance CMOS technology. Synchronous features with Data Strobe allow

extremely high performance up to 1.328GB/s/chip. I/O transactions are possible on both edges of the clock cycle. Range of

operating frequencies, programmable burst length and programmable latencies allow the device to be useful for a variety

of high performance memory system applications.

· 3.3V

5% power supply for device operation

· 2.5V

5% power supply for I/O interface

· SSTL_2 compatible inputs/outputs

· 4 banks operation

· MRS cycle with address key programs

-. Read latency 2, 3 (clock)

-. Burst length (2, 4, 8 and Full page)

-. Burst type (sequential & interleave)

· Full page burst length for sequential burst type only

· Start address of the full page burst should be even

· All inputs except data & DM are sampled at the positive

going edge of the system clock

· Differential clock input

· Data I/O transactions on both edges of Data strobe

· Data input & output & DM are synchronized with DQS

GENERAL DESCRIPTION

FEATURES

· Edge aligned data & data strobe output

· Center aligned data & data strobe input

· DM for write masking only

· Auto & Self refresh

· 16ms refresh period (2K cycle)

· 100pin TQFP package

· Maximum clock frequency up to 166MHz

· Maximum data rate up to 333Mbps/pin

Graphics Features

· SMRS cycle.

-. Load color register

· 16 Columns Block Write.

· Byte Masking with DM for Block Write operation is sup-

ported.

FOR 512K x 32Bit x 4 Bank DDR SGRAM

512K x 32Bit x 4 Banks Double Data Rate Synchronous Graphic RAM
with Bi-directional Data Strobe

ORDERING INFORMATION

Part NO.

Max Freq.

Max Data Rate

Interface

Package

K4D623237M-QC60

166MHz

333Mbps/pin

SSTL_2

100 TQFP

K4D623237M-QC70

143MHz

286Mbps/pin

K4D623237M-QC80

125MHz

250Mbps/pin

K4D623237M-QC10

100MHz

200Mbps/pin

Preliminary

64M DDR SGRAM

K4D623237M

PIN CONFIGURATION

(Top View)

PIN DESCRIPTION

CK,CK

Differential Clock Input

, BA

Bank Select Address

CKE

Clock Enable

Address Input

Chip Select

~ DQ

Data Input/Output

RAS

Row Address Strobe

Power

CAS

Column Address Strobe

Ground

Write Enable

DDQ

Power for DQ

DQS

Data Strobe

SSQ

Ground for DQ

DMi

Data Mask

DSF

Define Special Function

RFU

Reserved for Future Use

MCL

Must Connect Low

DQ29

VSSQ

DQ30

DQ31

VSS

VDDQ

N.C

VSSQ

RFU

DQS

VDDQ

VDD

DQ0

DQ1

VSSQ

DQ2

100

VSS

N.C

A10

VDD

100 Pin TQFP

20 x 14 mm

0.65mm pin Pitch

,

M

(
A

)

Preliminary

64M DDR SGRAM

K4D623237M

INPUT/OUTPUT FUNCTIONAL DESCRIPTION

*1 : The timing reference point for the differential clocking is the cross point of CK and CK.

For any applications using the single ended clocking, apply V

REF

to CK pin.

Symbol

Type

Function

CK, CK

Input

The differential system clock Input.

All of the inputs are sampled on the rising edge of the clock except

s and DM

s that are sampled on both edges of the DQS.

CKE

Input

Activates the CK signal when high and deactivates the CK signal

when low. By deactivating the clock, CKE low indicates the Power

down mode or Self refresh mode.

Input

CS enables the command decoder when low and disabled the com-

mand decoder when high. When the command decoder is disabled,

new commands are ignored but previous operations continue.

RAS

Input

Latches row addresses on the positive going edge of the CK with

RAS low. Enables row access & precharge.

CAS

Input

Latches column addresses on the positive going edge of the CK with

CAS low. Enables column access.

Input

Enables write operation and row precharge.

Latches data in starting from CAS, WE active.

DQS

Input/Output

Data input and output are synchronized with both edge of DQS.

~ DM

Input

Data In mask. Data In is masked by DM Latency=0 when DM is high

in burst write. DM

for DQ

~ DQ

for DQ

~ DQ

15,

for

~ DQ

23,

for DQ

~ DQ

31.

~ DQ

Input/Output

Data inputs/Outputs are multiplexed on the same pins.

, BA

Input

Selects which bank is to be active.

~ A

Input

Row/Column addresses are multiplexed on the same pins.

Row addresses : RA

~ RA

, Column addresses : CA

~ CA

Column address CA

is used for auto precharge.

Power Supply

Power and ground for the input buffers and core logic.

DDQ

SSQ

Power Supply

Isolated power supply and ground for the output buffers to provide

improved noise immunity.

REF

Power Supply

Reference voltage for inputs, used for SSTL interface.

DSF, MCL

Define Special Function

Enables block write and special mode register set and must be con-

nected low to disable these special functions.

Preliminary

64M DDR SGRAM

K4D623237M

BLOCK DIAGRAM

(512Kbit x 32I/O x 4 Bank)

Bank Select

Timing Register

r
e

i
s

t
e

f
r
e

t
e

f
f
e

l
.

B

f
f
e

Data Input Register

Serial to parallel

512Kx32

-
b

i
t

p

r
e

f
e

t
c

t
p

t

B

f
f
e

I
/
O

t
r
o

Column Decoder

Latency & Burst Length

Programming Register

t
r
o

CK,CK

ADD

LCKE

CK,CK

CKE

RAS

CAS

DMi

LDMi

CK,CK

LCAS

LRAS

LCBR

LWE

LWCBR

CK, CK

LWE

LDMi

x32

DQi

Data Strobe

DSF

Intput Buffer

Color Register

MUX

Block Write

Control

Preliminary

64M DDR SGRAM

K4D623237M

· Power-Up Sequence

DDR SGRAMs must be powered up and initialized in a predefined manner to prevent undefined operations.

1. Apply power and keep CKE at low state (All other inputs may be undefined)
- Apply VDD before VDDQ .
- Apply VDDQ before VREF & VTT
2. Start clock and maintain stable condition for a minimum of 200us.
3. The minimum of 200us after stable power and clock(CK,CK ), apply NOP and take CKE to be high .
4. Issue precharge command for all banks of the device.

5. Issue at least 2 or more auto-refresh commands.
6. Issue a mode register set command to initialize the mode register.

cf) Sequence of 4 & 5 is regardless of the order.

FUNCTIONAL DESCRIPTION

Power up Sequence & Auto Refresh(CBR)

Command

Minimum of 2 Refresh Cycles are required

1 tck

precharge

ALL Bank

2nd Auto

Refresh

Mode

Any

Command

1st Auto

Refresh

CK, CK

Inputs must be

stable for 200us

Preliminary

64M DDR SGRAM

K4D623237M

The mode register stores the data for controlling the various operating modes of DDR SGRAM. It programs CAS latency,

addressing mode, burst length, test mode and various vendor specific options to make DDR SGRAM useful for variety of
different applications. The default value of the mode register is not defined, therefore the mode register must be written
after power up to operate the DDR SGRAM. The mode register is written by asserting low on CS, RAS, CAS and WE(The
DDR SGRAM should be in active mode with CKE already high prior to writing into the mode register). The state of address
pins A

~ A

and BA

, BA

in the same cycle as CS, RAS, CAS and WE going low is written in the mode register. One

clock cycle is requested to complete the write operation in the mode register. The mode register contents can be changed
using the same command and clock cycle requirements during operation as long as all banks are in the idle state. The
mode register is divided into various fields depending on functionality. The burst length uses A

~ A

, addressing mode

uses A

, CAS latency(read latency from column address) uses A

~ A

. A

is used for test mode. A

, A

, BA

and BA

must be set to low for normal DDR SGRAM operation. Refer to the table for specific codes for various burst length,
addressing modes and CAS latencies.

MODE REGISTER SET(MRS)

Address Bus

Mode Register

CAS Latency

Latency

Reserve

Burst Length

Burst Type

Sequential

Interleave

Reserve

Full page

Reserve

mode

Normal

Test

Burst Type

Type

Sequential

Interleave

* RFU(Reserved for future use)

should stay "0" during MRS
cycle.

MRS Cycle

Command

*1 : MRS can be issued only at all banks precharge state.
*2 : Minimum

is required to issue MRS command.

CK, CK

Precharge

NOP

MRS

NOP

Any

NOP

All Banks

Command

MRD

=1 t

RFU

CAS Latency

Burst Length

Preliminary

64M DDR SGRAM

K4D623237M

DEFINE SPECIAL FUNCTION(DSF)

The DSF controls the graphic applications of SGRAM. If DSF is tied to low, SGRAM functions are the same as SDRAM
functions. SGRAM can be used as an unified memory by the appropriate DSF command. All the graphic function mode
can be entered only by setting DSF high when issuing commands which otherwise would be normal SDRAM commands.

See the sessions below for the graphic functions that DSF control.

SPECIAL MODE REGISTER SET(SMRS)

There is a special mode register in DDR SGRAM. It is color register. This usage will be explained at "BLOCK WRITE"

session. When A6 and DSF goes high in the same cycle as CS, RAS, CAS and WE going low, load color register(LCR)
process is executed and the color register is filled with color data for associated DQ

s through the DQ pins. At the next

clock of LCR, a new commands can be issued. SMRS, compared with MRS, can be issued at the active state under the
condition that DQ

s are idle.

Special Mode Register Programmed with SMRS

Address

Function

Load Color Register

Function

Disable

Enable

Command

SMRS Cycle

SMRS

NOP

DQS

Color

CK, CK

NOP

Load Color

Block write is a feature allowing the simultaneous writing of consecutive 16 columns of data within a RAM device during

a single access cycle. During block write the data to be written comes from an internal "color" register. The block of col-

umn to be written is aligned on 16 column boundaries and is defined by the column address with the 4 LSB

s ignored.

Write command with DSF=High enables block write for the associated bank. A write command with DSF=Low enables

normal write for the associated bank. The block width is 16 column where column="n" bits for by "n" part. The color reg-

ister is the same width as the data port of the chip. The color register provides the data without column masking. So DQ

states are don

t cared. And Null Column Mask command with high state on DQs make no problem. DQS should toggle

once for valid data mask(DM) input. Block writes are always non-burst, independent of the burst length that has been

programmed into the mode register. Back to back block writes are allowed provided that the specified block write cycle

time(tBWC) is satisfied.

BLOCK WRITE

SMRD

=1 t

Preliminary

64M DDR SGRAM

K4D623237M

CDLW=0

Note 2

1. t

CCD

: CAS to CAS delay. (=1 tCK)

2. t

CDLW

: Last data in to new column address delay. (=0 tCK)

3. t

BWC

: Block write minimum cycle time. (=1 tCK)

CDLW=0

Note 2

BWC

Note 3

2) Write interrupted by Block Write (BL=2)

3) Block Write to Block Write

CK, CK

CMD

ADD

CK, CK

CMD

ADD

*Note :

1) Block Write to Precharge

4) Byte Masking for Block Write

CK, CK

CMD

DMi

CK, CK

CMD

BPL

PRE

CCD Note1

SMRS

16 col.

WRITE

16 col.

Byte Masking

for Block Write

Byte Masking

for Normal Write

Color

DQS

Din 0

Din 1

Din A

Din B

Din C

BPL

PRE

Preliminary

64M DDR SGRAM

K4D623237M

Burst mode operation is used to provide a constant flow of data to memory locations(write cycle), or from memory loca-

tions(read cycle). There are two parameters that define how the burst mode operates. These parameters including burst
sequence and burst length are programmable and determined by address bits A

~ A

during the Mode Register Set com-

mand. The burst type is used to define the sequence in which the burst data will be delivered or stored to the SGRAM.
Two types of burst sequences are supported, sequential and interleaved. See the below table. The burst length controls
the number of bits that will be output after a read command, or the number of bits to be input after a write command. The
burst length can be programmed to have values of 2, 4, 8 or Full page. For the full page operation, the starting address
must be an even number.

BURST MODE OPERATION

BURST LENGTH AND SEQUENCE

Burst Length

Starting Address(A

, A

)

Sequential Mode

Interleave Mode

xx0

0, 1

xx1

1, 0

x00

0, 1, 2, 3

x01

1, 2, 3, 0

1, 0, 3, 2

x10

2, 3, 0, 1

x11

3, 0, 1, 2

3, 2, 1, 0

000

0, 1, 2, 3, 4, 5, 6, 7

001

1, 2, 3, 4, 5, 6, 7, 0

1, 0, 3, 2, 5, 4, 7, 6

010

2, 3, 4, 5, 6, 7, 0, 1

2, 3, 0, 1, 6, 7, 4, 5

011

3, 4, 5, 6, 7, 0, 1, 2

3, 2, 1, 0, 7, 6, 5, 4

100

4, 5, 6, 7, 0, 1, 2, 3

101

5, 6, 7, 0, 1, 2, 3, 4

5, 4, 7, 6, 1, 0, 3, 2

110

6, 7, 0, 1, 2, 3, 4, 5

6, 7, 4, 5, 2, 3, 0, 1

111

7, 0, 1, 2, 3, 4, 5, 6

7, 6, 5, 4, 3, 2, 1, 0

The Bank Activation command is issued by holding CAS and WE high with CS and RAS low at the rising edge of the

clock. The DDR SGRAM has four independent Banks, so two Bank Select addresses(BA

, BA

) are supported. The Bank

Activation command must be applied before any Read or Write operation is executed. The delay from the Bank Activation
command to the first read or write command must meet or exceed the minimum of RAS to CAS delay time(t

RCD

min

). Once

a bank has been activated, it must be precharged before another Bank Activation command can be applied to the same
bank. The minimum time interval between interleaved Bank Activation commands(Bank A to Bank B and vice versa) is the
Bank to Bank delay time(t

RRD

min

BANK ACTIVATION COMMAND

Address

Command

RAS-CAS delay(

RCD

)

Bank Activation Command Cycle

(CAS Latency = 2)

Bank A

Row Addr.

Bank A

Col. Addr.

Bank A

Activate

Write A

with Auto

NOP

Precharge

RAS-RAS delay time(

RRD

)

Bank A

Row Addr.

Bank B

Row. Addr.

Bank A

Activate

Bank B

Activate

NOP

ROW Cycle Time(

)

n+1

n+2

: Don

t care

CK, CK

Preliminary

64M DDR SGRAM

K4D623237M

Burst Read operation in DDR SGRAM is in the same manner as the current SDRAM such that the Burst read command

is issued by asserting CS and CAS low while holding RAS and WE high at the rising edge of the clock after t

RCD

from the

bank activation. The address inputs (A

) determine the starting address for the Burst. The Mode Register sets type of

burst(

equential or interleave) and burst length(2, 4, 8, Full page). The first output data is available after the CAS Latency

from the READ command, and the consecutive data are presented on the falling and rising edge of Data Strobe adopted
by DDR SGRAM until the burst length is completed.

BURST READ OPERATION

The Burst Write command is issued by having CS, CAS, and WE low while holding RAS high at the rising edge of the

clock. The address inputs determine the starting column address. There is no real write latency required for burst write
cycle. The first data for burst write cycle must be applied at the first rising edge of the data strobe enabled after t

DQSS

from

the rising edge of the clock that the write command is issued. The remaining data inputs must be supplied on each subse-
quent falling and rising edge of Data Strobe until the burst length is completed. When the burst has been finished, any
additional data supplied to the DQ pins will be ignored.

BURST WRITE OPERATION

Command

< Burst Length=4, CAS Latency=2, 3 >

READ A

NOP

DQS

CAS Latency=2

Dout 0 Dout 1 Dout 2 Dout 3

DQS

CAS Latency=3

Dout 0 Dout 1 Dout 2 Dout 3

Command

< Burst Length=4 >

NOP

WRITE

NOP

DQS

Din 0

Din 1

Din 2

Din 3

DQSS

Ck, Ck

CK, CK

DSHZ

SDQS

ACS

SHZ

SLZ

Preamble

Postamble

Preamble

Postamble

Preliminary

64M DDR SGRAM

K4D623237M

A Burst Read can be interrupted before completion of the burst by new Read command of any bank. When the previous

burst is interrupted, the remaining addresses are overridden by the new address with the full burst length. The data from
the first Read command continues to appear on the outputs until the CAS latency from the interrupting Read command is
satisfied. At this point the data from the interrupting Read command appears. Read to Read interval is minimum 1 tck.

BURST INTERRUPTION

Read Interrupted by a Read

To interrupt a burst read with a write command, Burst stop command must be asserted to avoid data contention on the I/

O bus by placing the DQ

(Output drivers) in a high impedance state at least one clock cycle before the Write Command is

initiated.

Read Interrupted by Burst stop & a Write

Command

< Burst Length=4, CAS Latency=2 >

READ A

READ B

NOP

DQS

CAS Latency=2

Dout A

Dout B

Command

< Burst Length=4, CAS Latency=2 >

READ

Burst Stop

NOP

WRITE

NOP

DQS

CAS Latency=2

Dout 0

Dout 1

Din 0

Din 1

Din 2

Din 3

CK, CK

NOP

Preliminary

64M DDR SGRAM

K4D623237M

A Burst Read operation can be interrupted by precharge of the same bank. The minimum 1 clock is required for the Read

to precharge intervals without interrupting a Read burst. A precharge command to output disable latency is equivalent to
the CAS latency.

Read Interrupted by a Precharge

Command

< Burst Length=8, CAS Latency=2 >

READ

NOP

Precharge

NOP

DQS

CAS Latency=2

Dout 0

Dout 1

Dout 2

Dout 3

A Burst Write can be interrupted before completion of the burst by the new Write Command, with the only restriction being

that the interval that separates the commands must be at least one clock cycle. When the previous burst is interrupted,
the remaining addresses are overridden by the new address and data will be written into the device until the programmed
burst length is satisfied.

Write Interrupted by a Write

Command

< Burst Length=4 >

NOP

WRITE A

WRITE B

NOP

DQS

Din A

Din B

1 tCK interval

Ck, Ck

CK, CK

Dout 4

Dout 5

Dout 6

Dout 7

Interrupted by precharge

Preliminary

64M DDR SGRAM

K4D623237M

A Burst Write can be interrupted by a Read command to any bank. The DQ

s must be in the high impedance state at

least one clock cycle before interrupting read data appears on the outputs to avoid data contention. When the Read Com-
mand is registered, any residual data from the burst write cycle will be masked by DM. The delay from the last data to Read
command (tCDLR) is required to avoid the data contention DRAM inside.

Write Interrupted by a Read & DM

Command

< Burst Length=8, CAS Latency=2 >

NOP

WRITE

NOP

READ

NOP

DQS

Din 0

Din 1

Din 2

Din 3

A Burst Write operation can be interrupted before completion of the burst by a precharge of the same bank. A Write

Recovery time(tRDL) is required before a Precharge command to finish the Write operation. When Precharge command is
asserted, any residual data from the burst write cycle must be masked by DM.

Write Interrupted by a Precharge & DM

Din 4

Din 5

Dout 0

Dout 1 Dout 2

Command

< Burst Length=8 >

NOP

WRITE A

NOP

Precharge

NOP

WRITE B

DQS

Dina

Dinb

Dina

Din 6

Din 7

CDLRmin

RDLmin

DQSSmax

DQS

CDLRmin

DQSSmin

Din 0

Din 1

Din 2

Din 3

Din 4

Din 5

Din 6

Din 7

DQS

RDLmax

DQSSmin

Dina

Dinb

DQSSmax

Dout 0

Dout 1

Dout 2

CK, CK

Dout 3

Minimum tDQSS

Maximum tDQSS

Minimum tDQSS

Maximum tDQSS

Preliminary

64M DDR SGRAM

K4D623237M

The Burst stop command is initiated by having RAS and CAS high with CS and WE low at the rising edge of the clock

only . The Burst Stop command has the fewest restrictions making it the easiest method to use when terminating a burst
operation before it has been completed. When the Burst Stop command is issued during a burst read cycle, both the data
and DQS(Data Strobe) go to a high impedance state after a delay which is equal to the CAS Latency set in the Mode Reg-
ister. The Burst Stop command, however, is not supported during a write burst operation.

BURST STOP COMMAND

The DDR SGRAM has a Data mask function that can be used in conjunction with data Write cycle only, not Read cycle.

When the Data Mask is activated (DM high) during write operation the write data is masked immediately(DM to Data-mask
Latency is zero).
DM must be issued at the rising edge or the falling edge of Data Strobe instead of a clock edge.

DM FUNCTION

Command

< Burst Length=4, CAS Latency=2, 3 >

READ A

Burst Stop

NOP

DQS

CAS Latency=2

Dout 0 Dout 1

DQS

CAS Latency=3

Command

< Burst Length=8 >

WRITE

NOP

DQS

Din 0

Din 1

Din 2

Din 3

The burst ends after a delay equal to the CAS latency.

Dout 0 Dout 1

Din 4

Din 5

Din 6

Din7

masked by DM=H

CK, CK

DQSSmax

Preliminary

64M DDR SGRAM

K4D623237M

The Auto precharge command can be issued by having column address A

High when a Read or a Write command is

asserted into the DDR SGRAM. If A

is low when Read or Write command is issued, then normal Read or Write burst oper-

ation is asserted and the bank remains active after the completion of the burst sequence. When the Auto precharge com-
mand is activated, the active bank automatically begins to precharge at the earliest possible moment during read or write
cycle after t

RAS

(min) is satisfied.

AUTO-PRECHARGE OPERATION

Command

< Burst Length=4, CAS Latency=2, 3 >

BANK A

NOP

READ A

NOP

DQS

CAS Latency=2

Dout 0 Dout 1 Dout 2 Dout 3

If a Read with Auto-precharge command is initiated, the DDR SGRAM automatically starts the precharge operation on

BL/2 clock later from a Read with Auto-Precharge command when

RAS

(min) is satisfied. If not, the start point of precharge

operation will be delayed until

RAS

(min) is satisfied. Once the precharge operation has started the bank cannot be reacti-

vated and the new command can not be asserted until the Precharge time(

) has been satisfied.

Read with Auto Precharge

ACTIVE

Auto Precharge

* Bank can be reactivated at the

completion of

precharge

Begin Auto-Precharge

DQS

CAS Latency=3

Dout 0 Dout 1 Dout 2 Dout 3

When the Read with Auto precharge command is issued, new command can be asserted at T3,T4 and T5 respectively

as follows, even the new command for the same bank is illigal.

Asserted

command

For same Bank

For Different Bank

Read Interrupt

READ +

NO AP*1

READ+

NO AP

Illegal

Legal

Active

Illegal

Fail

Legal

Precharge

Illegal

Fail

Legal

*1 : AP = Auto Precharge

CK, CK

Preliminary

64M DDR SGRAM

K4D623237M

If A

is high when Write command is issued , the write with Auto-Precharge function is performed. Any new command to

the same bank should not be issued until the internal precharge is completed. The internal precharge begins after keeping

RDL

(min).

Write with Auto Precharge

Command

< Burst Length=4 >

BANK A

NOP

WRITE A

NOP

DQS

Din 0 Din 1 Din 2

ACTIVE

Auto Precharge

* Bank can be reactivated at

completion of

RDL

Internal precharge start

The precharge command is used to precharge or close a bank that has been activated. The precharge command is

issued when CS, RAS and WE are low and CAS is high at the rising edge of the clock, CK. The precharge command can
be used to precharge each bank respectively or all banks simultaneously. The Bank select addresses(BA

, BA

) are used

to define which bank is precharged when the command is initiated. For write cycle,

RDL

(min.) must be satisfied from the

start of the last burst write cycle until the precharge command can be issued. After

from the precharge, an active com-

mand to the same bank can be initiated.

PRECHARGE COMMAND

< Bank Selection for Precharge by Bank address bits >

/AP

BA1

Precharge

Bank A Only

Bank B Only

Bank C Only

Bank D Only

All Banks

CK, CK

< Block Write >

CK, CK

CMD

BPL

Auto Precharge Starts

Din 3

Preliminary

64M DDR SGRAM

K4D623237M

Command

CKE

PRE

A Self Refresh command is defined by having CS, RAS, CAS and CKE held low with WE high at the rising edge of the

clock. Once the self Refresh command is initiated, CKE must be held low to keep the device in Self Refresh mode. After 1
clock cycle from the self refresh command, all of the external control signals including system clock(CK, CK) can be dis-
abled except CKE. The clock is internally disabled during Self Refresh operation to reduce power. To exit the Self Refresh
mode, supply stable clock input before returning CKE high, assert deselect or NOP command and then assert CKE high.
The Auto Refresh is required before self refresh entry and after self refresh exit.

SELF REFRESH

Auto

=High

Refresh

CMD

Command

CKE

Stable Clock

Auto

Refresh

NOP

Self

Refresh

An Auto Refresh command is issued by having CS, RAS and CAS held low with CKE and WE high at the rising edge of

the clock, CK. All banks must be precharged and idle for a

(min) before the Auto Refresh command is applied. No con-

trol of the external address pins is required once this cycle has started because of the internal address counter. When the
refresh cycle has completed, all banks will be in the idle state. A delay between the Auto Refresh command and the next
Activate Command or subsequent Auto Refresh Command must be greater than or equal to the

RFC(

min).

AUTO REFRESH

CK, CK

RC(min)

Preliminary

64M DDR SGRAM

K4D623237M

CKE

Precharge

Active

The power down is entered when CKE Low,and exited when CKE High. Once the power down mode is initiated, all of the

receiver circuits except CK and CKE are gated off to reduce power consumption. The both bank should be in idle state
prior to entering the precharge power down mode and CKE should be set high at least 1 tCK+tIS prior to Row active com-
mand. During power down mode, refresh operations cannot be performed, therefore the device cannot remain in power
down mode longer than the refresh period(t

REF

) of the device.

POWER DOWN MODE

power

Entry

down

Precharge

Command

CK, CK

power

Exit

down

Precharge

power

Entry

down

Active

power

Exit

down

Active

Read

(NOP)

Preliminary

64M DDR SGRAM

K4D623237M

SIMPLIFIED TRUTH TABLE

(V=Valid, X=Don

t Care, H=Logic High, L=Logic Low)

COMMAND

CKEn-1 CKEn

RAS

CAS

DSF

0,1

/AP A

Note

Mode Register Set

OP CODE

1, 2

Special Mode Register Set

Refresh

Auto Refresh

Self
Refresh

Entry

Exit

Bank Active & Row Addr.

Row Address

Read &
Column Address

Auto Precharge Disable

Column

Address

Auto Precharge Enable

Write &
Column Address

Auto Precharge Disable

Column

Address

Auto Precharge Enable

4, 6

Block Write &
Column Address

Auto Precharge Disable

Column

Address

4, 5

Auto Precharge Enable

4,5,6,9

Burst Stop

Precharge

Bank Selection

All Banks

Active Power Down

Entry

Exit

Precharge Power Down Mode

Entry

Exit

No Operation Command

1. OP Code : Operand Code

~ A

& BA

~ BA

: Program keys. (@MRS)

: LCR @ SMRS/Color register exists only one per DQi which all banks share.

Color is loaded into chip through DQ pin

2. MRS can be issued only at all banks precharge state.

SMRS can be issued only if DQ

s are idle.

A new command can be issued after 1 clock cycle of MRS/SMRS.

3. Auto refresh functions are as same as CBR refresh of DRAM.

The automatical precharge without row precharge command is meant by "Auto".

Auto/self refresh can be issued only at all banks precharge state.

Note :

Preliminary

64M DDR SGRAM

K4D623237M

4. BA

~ BA

: Bank select addresses.

If both BA

and BA

are "Low" at read, write, row active and precharge, bank A is selected.

If BA

is "High" and BA

is "Low" at read, write, row active and precharge, bank B is selected.

If BA

is "Low" and BA

is "High" at read, write, row active and precharge, bank C is selected.

If both BA

and BA

are "High" at read, write, row active and precharge, bank D is selected.

5. If A

/AP is "High" at row precharge, BA

and BA

is ignored and all banks are selected.

6. During burst write with auto precharge, new read/write command can not be issued.

Another bank read/write command can be issued after the end of burst.

New row active of the associated bank can be issued at t

after the end of burst.

7. Burst stop command is valid at every burst length.

8. DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0).

9. Graphic features are added to SDRAM

s original features.

If DSF is tied to low, graphic functions are disabled and chip operates as a 64M SDRAM with 32 DQ

Preliminary

64M DDR SGRAM

K4D623237M

FUNCTION TRUTH TABLE

Current State CS RAS CAS WE DSF

Address

Command

Action

IDLE

DESEL

NOP

TERM

NOP

BA, CA, A

READ/WRITE/BW

ILLEGAL*2

BA, RA

ACT

Bank Active, Latch RA

BA, A

PRE/PREA

NOP*4

REFA

AUTO-Refresh*5

Op-Code, Mode-Add

MRS

Mode Register Set*5

SMRS

Special Mode Register Set

ROW ACTIVE H

DESEL

NOP

TERM

NOP

BA, CA, A

READ/READA

Begin Read, Latch CA,
Determine Auto-Precharge

BA, CA, A

WRITE/WRITEA

Begin Write, Latch CA,
Determine Auto-Precharge

BA, CA, A

BW/BWA

Begin Block Write, Latch CA,
Determine Auto-Precharge

BA, RA

ACT

ILLEGAL*2

BA, A

PRE/PREA

Precharge/Precharge All

REFA

ILLEGAL

Op-Code, Mode-Add

MRS

ILLEGAL

SMRS

Special Mode Register Set

READ

DESEL

NOP(Continue Burst to END)

NOP

NOP(Continue Burst to END)

TERM

Terminate Burst

BA, CA, A

READ/READA

Terminate Burst, Latch CA,
Begin New Read, Determine
Auto-Precharge*3

BA, CA, A

WRITE/WRITEA
BW/BWA

ILLEGAL

BA, RA

ACT

ILLEGAL*2

BA, A

PRE/PREA

Terminate Burst, Precharge

REFA

ILLEGAL

Op-Code, Mode-Add

MRS

ILLEGAL

SMRS

ILLEGAL

Preliminary

64M DDR SGRAM

K4D623237M

FUNCTION TRUTH TABLE

(continued)

Current State

CS RAS CAS WE DSF

Address

Command

Action

WRITE

DESEL

NOP(Continue Burst END)

NOP

NOP(Continue Burst END)

TERM

ILLEGAL

BA, CA, A

READ/READA

Terminate Burst With DM=High,
Latch CA, Begin Read, Determine
Auto-Precharge*3

BA, CA, A

WRITE/WRITEA

Terminate Burst, Latch CA,
Begin new Write, Determine Auto-
Precharge*3

BA, CA, A

BW/BWA

Terminate Burst , Latch CA,
New Block Write, Determine AP.

BA, RA

ACT

ILLEGAL*2

BA, A

PRE/PREA

Terminate Burst With DM=High,
Precharge

REFA

ILLEGAL

Op-Code, Mode-Add

MRS

ILLEGAL

SMRS

ILLEGAL

READ with AUTO

PRECHARGE

DESEL

NOP(Continue Burst END)

NOP

NOP(Continue Burst END)

TERM

ILLEGAL

BA, CA, A

READ/WRITE

ILLEGAL*2

BA, RA

ACT

ILLEGAL*2

BA, A

PRE/PREA

ILLEGAL*2

REFA

ILLEGAL

Op-Code, Mode-Add

MRS

ILLEGAL

SMRS

ILLEGAL

WRITE with AUTO

RECHARGE

DESEL

NOP(Continue Burst to END)

NOP

NOP(Continue Burst to END)

TERM

ILLEGAL

BA, CA, A

READ/WRITE

ILLEGAL*2

BA, RA

ACT

ILLEGAL*2

BA, A

PRE/PREA

ILLEGAL*2

REFA

ILLEGAL

Op-Code, Mode-Add

MRS

ILLEGAL

SMRS

ILLEGAL

Preliminary

64M DDR SGRAM

K4D623237M

FUNCTION TRUTH TABLE

(continued)

Current State

RAS CAS

DSF

Address

Command

Action

BLOCK

WRITE

RECOVERING

DESEL

NOP(Continue Block Write)

NOP

NOP(Continue Block Write)

TERM

NOP

BA, CA, A

READ/READA
WRITE/
WRITEA

ILLEGAL

BA, RA

ACT

ILLEGAL*2

BA, A

PRE/PREA

Terminate Block Write, Pre-
charge

REFA

ILLEGAL

Op-Code, Mode-Add

MRS

ILLEGAL

SMRS

ILLEGAL

PRE-

CHARGING

DESEL

NOP(Idle after

)

NOP

NOP(Idle after

)

TERM

NOP

BA, CA, A

READ/WRITE

ILLEGAL*2

BA, RA

ACT

ILLEGAL*2

BA, A

PRE/PREA

NOP*4(Idle after

)

REFA

ILLEGAL

Op-Code, Mode-Add

MRS

ILLEGAL

SMRS

ILLEGAL

ROW

ACTIVATING

DESEL

NOP(ROW Active after

RCD

)

NOP

NOP(ROW Active after

RCD

)

TERM

NOP

BA, CA, A

READ/WRITE

ILLEGAL*2

BA, RA

ACT

ILLEGAL*2

BA, A

PRE/PREA

ILLEGAL*2

REFA

ILLEGAL

Op-Code, Mode-Add

MRS

ILLEGAL

SMRS

ILLEGAL

Preliminary

64M DDR SGRAM

K4D623237M

FUNCTION TRUTH TABLE

(continued)

ABBREVIATIONS :

H=High Level, L=Low level, V=Valid, X=Don

t Care

BA=Bank Address, RA=Row Address, CA=Column Address, NOP=No Operation

Note :

1. All entries assume that CKE was High during the preceding clock cycle and the current clock cycle.
2. ILLEGAL to bank in specified state ; function may be legal in the bank indicated by BA, depending on the state of that bank.
3. Must satisfy bus contention, bus turn around, write recovery requirements.
4. NOP to bank precharging or in idle sate. May precharge bank indicated by BA.
5. ILLEGAL if any bank is not idle.
6. Same Bank

s previous Auto precharge will not be performed. But if Bank is different, previous Auto precharge will be performed.

ILLEGAL = Device operation and/or data-integrity are not guaranteed.

Current State

CS RAS

CAS WE DSF

Address

Command

Action

WRITE

RECOVERING

DESEL

NOP

TERM

NOP

BA, CA, A

READ

ILLEGAL*2

BA, CA, A

WRITE/WRITEA

New Write, Determine AP.

BA, CA, A

BW/BWA

New BW, Determine AP.

BA, RA

ACT

ILLEGAL*2

BA, A

PRE/PREA

ILLEGAL*2

REFA

ILLEGAL

Op-Code, Mode-Add

MRS

ILLEGAL

SMRS

ILLEGAL

RE-

FRESHING

DESEL

NOP(Idle after

)

NOP

NOP(Idle after

)

TERM

NOP

BA, CA, A

READ/WRITE

ILLEGAL

BA, RA

ACT

ILLEGAL

BA, A

PRE/PREA

ILLEGAL

REFA

ILLEGAL

Op-Code, Mode-Add

MRS

ILLEGAL

SMRS

ILLEGAL

Preliminary

64M DDR SGRAM

K4D623237M

FUNCTION TRUTH TABLE for CKE

ABBREVIATIONS :

H=High Level, L=Low level, X=Don

t Care

Note :

1. After CKE

s low to high transition to exist self refresh mode. And a time of tRC(min) has to be elapse after CKE

s low to high

transition to issue a new command.
2. CKE low to high transition is asynchronous as if restarts internal clock.
A minimum setup time "tSS + one clock" must be satisfied before any command other than exit.
3. Power-down and self refresh can be entered only from the all banks idle state.
4. Must be a legal command.

Current State

CKE

n-1

CKE

RAS

CAS

DSF

Add

Action

SELF-

REFRESHING

INVALID

Exit Self-Refresh*1

ILLEGAL

NOP(Maintain Self-Refresh)

Both Bank
Precharge

POWER

DOWN

INVALID

Exit Power Down*2

ILLEGAL

NOP(Maintain Power Down)

ALL BANKS

IDLE

Refer to Function True Table

Enter Power Down*3

ILLEGAL

Row (& Bank) Active

Enter Self-Refresh*3

OP Code

Mode Register Access

OP Code

Special Mode Register Access

Refer to Current State=Power Down

Any State

other than

listed above

Refer to Function True Table

Begin Clock Suspend next cycle*4

Exit Clock Suspend next cycle*4

Maintain Clock Suspend

Preliminary

64M DDR SGRAM

K4D623237M

ABSOLUTE MAXIMUM RATINGS

Parameter

Symbol

Value

Unit

Voltage on any pin relative to Vss

, V

OUT

-1.0 ~ 4.6

Voltage on V

supply relative to Vss

, V

DDQ

-1.0 ~ 4.6

Storage temperature

STG

-55 ~ +150

Power dissipation

1.6

Short circuit current

Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

Note :

POWER & DC OPERATING CONDITIONS(SSTL_2 In/Out)

Recommended operating conditions(Voltage referenced to V

=0V, T

=0 to 65

Parameter

Symbol

Min

Typ

Max

Unit

Note

Device Supply voltage

3.135

3.3

3.465

Output Supply voltage

DDQ

2.375

2.50

2.625

Reference voltage

REF

1.15

1.25

1.35

2, 3

Termination voltage

Vtt

REF

-0.04

REF

+0.04

Input logic high voltage

REF

+0.18

DDQ

+0.30

Input logic low voltage

-0.30

REF

-0.18

Output logic high voltage

Vtt+0.76

=-15.2mA

Output logic low voltage

Vtt-0.76

=+15.2mA

Input leakage current

-5

Output leakage current

-5

1. Under all conditions V

DDQ

must be less than or equal to V

2. Typically, the value of V

REF

is expected to be about 0.50*V

DDQ

of the transmitting device.

REF

is expected to track variation in V

DDQ

3. Peak to peak AC noise on V

REF

may not exceed 2% V

REF

(DC).

4. V

of the transmitting device must track V

REF

of the receiving device.

5. V

(min.)= -1.5V AC(pulse width

5ns).

6. For any pin under test input of 0V

+0.3V is acceptable.

For all other pins that are not under test V

=0V.

Note :

Preliminary

64M DDR SGRAM

K4D623237M

AC CHARACTERISTICS

Simplified Timing(1) @ BL=4, CL=2

Parameter

Symbol

-60

-70

-80

-10

Unit

Note

Min

Max

Min

Max

Min

Max

Min

Max

CK cycle time

CL=2

1000

CL=3

CK high level width

0.4

0.6

0.4

0.6

0.4

0.6

0.4

0.6

tCK

CK low level width

0.4

0.6

0.4

0.6

0.4

0.6

0.4

0.6

tCK

CK rising edge to CK rising edge Delay

CCB

0.45

0.55

0.45

0.55

0.45

0.55

0.45

0.55

tCK

CK Edge to Data Strobe Edge

ACS

2.5

5.5

2.5

5.5

2.5

6.0

2.5

6.0

CK Edge to Output Data Edge

2.5

5.5

2.5

5.5

2.5

6.0

2.5

6.0

Data Strobe Edge to Ouput Data Edge

DQSQ

-0.4

+0.4

-0.5

+0.5

-0.5

+0.5

-0.6

+0.6

Data valid widow

DVQ

1.9

2.1

2.6

3.3

Data strobe valid window

DVQS

1.9

2.1

2.6

3.3

DQS Low-Z to 1st valid DQS(Preamble) @ Read

SLZ

Last valid DQS to DQS Hi-Z(Postamble) @ Read

SHZ

Last valid DQS to DQS Hi-Z(Postamble) @ Write

DSHZ

2.5

Data out active to Hi-Z

HZQ

DQS Write Preamble setup time

SDQS

CK to valid DQS-in

DQSS

3.5

1 tCK

4.5

1 tCK

DQS-in high level width

SIH

0.4

0.6

0.4

0.6

0.4

0.6

0.4

0.6

tCK

DQS-in low level width

SIL

0.4

0.6

0.4

0.6

0.4

0.6

0.4

0.6

tCK

DQS-in cycle time

SIC

tCK

Input setup time

1.5

1.75

2.5

Input hold time

Data in & DM set-up time

0.4

0.6

Data in & DM hold time

0.7

0.8

CK transition time

0.5

1.5

0.5

1.7

0.5

2.5

tCCB

tCL

tCK

tACS

Hi-Z

CK, CK

DQS

tIS

tIH

tAC

tDS tDH

Qa0

tDQSQ

tSHZ

tSLZ

Db0

Db1

Db2

Db3

tDVQS

tSIC

tDQSS

tSIH

tSIL

tDS tDH

tHZQ

tCH

tDVQ

Qa1

Qa2

Qa3

tSDQS

tDSHZ

COMMAND

READ

WRITE

Preliminary

64M DDR SGRAM

K4D623237M

AC CHARACTERISTICS

1. Note : When t

DQSS

is close to the minimum value, t

CDLR

and t

RDL

are 2 tck ,3 tck, respectively.

When t

DQSS

is close to the maximum value, t

CDLR

and t

RDL

are 1.5 tck, 2.5 tck respectively.

For normal write operation, even numbers of Din are to be written inside DRAM.

Simplified Timing(2) @ BL=4, CL=2

Parameter

Symbol

-60

-70

-80

-10

Unit

Note

Min

Max

Min

Max

Min

Max

Min

Max

Row cycle time

Row active time

RAS

100K

RAS to CAS delay

RCD

Row precharge time

Row active to Row active delay

RRD

Last data in to Row precharge

RDL

3.5 tCK

DQSS

3.5 tCK

DQSS

3.5 tCK

DQSS

3.5 tCK

DQSS

Last data in to Read command delay

CDLR

2.5 tCK

DQSS

2.5 tCK

DQSS

2.5 tCK

DQSS

2.5 tCK

DQSS

Last data in to Write command delay

CDLW

tCK

Col. address to Col. address delay

CCD

tCK

Mode register set cycle time

MRD

tCK

Special Mode register set cycle time

SMRD

tCK

Block write cycle

BWC

tCK

Block write to precharge

BPL

tCK

Qa0 Qa1 Qa2 Qa3

BAa

tRCD

ACTIVE

WRITE

Qa0 Qa1 Qa2 Qa3

Qb0 Qb1

Qb3

BAa

BAb

tCCD

BAa

PRECH

BAa

READ

BAa

Qa0 Qa1 Qa2 Qa3

Normal Write Burst

(@ BL=4)

Multi Bank Interleaving Write Burst

(@ BL=4)

Write Interrupted by Read

(@ CL=2, BL=4)

BAa

BAb

Qb2

tCDLR

tRAS

tRC

tRP

tRRD

COMMAND

DQS

CK, CK

A8/AP

ADDR

(A0~A7,

BA[1:0]

A9,A10)

ACTIVE

WRITE

Preliminary

64M DDR SGRAM

K4D623237M

DC CHARACTERISTICS

Note : 1. Measured with outputs open.

2. Refresh period is 16ms.

3. Assumes minimum column address update cycle

BWC

(min).

Parameter

Symbol

Test Condition

CAS

Latency

Version

Unit

Note

-60

-70

-80

-10

Operating Current
(One Bank Active)

CC1

Burst Lenth=2

(min)

=0mA

260

240

220

200

Precharge Standby Current in
Power-down mode

CC2

CKE

(max),

=10ns

CC2

CKE

(max), CK

(min),

Precharge Standby Current
in Non Power-down mode

CC2

CKE

(min), CS

(min),

=10ns Input signals are changed

once

CC2

CKE

(min),CK

(max),

Active Standby Current
power-down mode

CC3

CKE

(max),

=10ns

CC3

CKE

VIL(max),CK

VIL(max),

Active Standby Current in
in Non Power-down mode

CC3

CKE

VIH(min), CS

VIH(min),

=10ns Input signals are changed

once

CC3

CKE

VIH(min),CK

VIL(max),

Input signals are stable.

Operating Current
(Burst Mode)

CC4

=0mA

Page Burst
All Banks activated

CCD

=2 tck

400

360

320

280

300

280

Refresh Current

CC5

(min)

300

290

280

270

Self Refresh Current

CC6

CKE

0.2V

Operating Current
(One Bank Block Write)

CC7

(min)

=0mA

BWC

(min)

420

380

340

300

Recommended operating conditions Unless Otherwise Noted, T

=0 to 65

Preliminary

64M DDR SGRAM

K4D623237M

AC OPERATING TEST CONDITIONS

=3.3V

0.15V, T

= 0 to 65

Parameter

Value

Unit

Note

Input reference voltage for CK(for single ended)

0.50*V

DDQ

CK signal maximum peak swing

1.5

CK signal minimum slew rate

1.0

V/ns

Input Levels(V

)

REF

+0.35/V

REF

-0.35

Input timing measurement reference level

REF

Output timing measurement reference level

Output load condition

See Fig.1

CAPACITANCE

=3.3V, T

= 25

f=1MHz)

Parameter

Symbol

Min

Max

Unit

Input capacitance(A

, BA

~BA

)

IN1

2.5

4.5

Input capacitance
(

CK, CKE, CS, RAS,CAS, WE )

IN2

2.5

5.0

Data & DQS input/output capacitance(DQ

~DQ

)

OUT

2.5

5.5

Input capacitance(DM)

IN3

2.5

5.5

=50

Output

LOAD

=30pF

(Fig. 1) Output Load Circuit

Z0=50

REF

=0.5*V

DDQ

=0.5*V

DDQ

DECOUPLING CAPACITANCE GUIDE LINE

Recommended decoupling capacitance added to power line at board.

Parameter

Symbol

Value

Unit

Decoupling Capacitance between V

and V

DC1

0.1 + 0.01

Decoupling Capacitance between V

DDQ

and V

SSQ

DC2

0.1 + 0.01

1. V

and V

DDQ

pins are separated each other.

All V

pins are connected in chip. All V

DDQ

pins are connected in chip.

2. V

and V

SSQ

pins are separated each other

All V

pins are connected in chip. All V

SSQ

pins are connected in chip.

Note :

Preliminary

64M DDR SGRAM

K4D623237M

Basic Timing (Setup, Hold and Access Time @BL=4, CL=2)

t
C

t
A

i
-
Z

,

C

[
1

:
0

]

/
A

W
E

(
A

,
A

)

t
I
S

t
I
H

W
R

I
T

t
A

I
G

t
D

t
S

t
D

t
S

I
C

t
D

t
S

I
H

t
S

I
L

t
D

t
H

t
C

t
D

t
S

t
D

Preliminary

64M DDR SGRAM

K4D623237M

Multi Bank Interleaving READ (@BL=4, CL=2)

I
V

W
E

t
R

I
G

t
R

t
C

,

C

/
A

(
A

,
A

)

[
1

:
0

]

Preliminary

64M DDR SGRAM

K4D623237M

Auto Precharge after READ Burst (@BL=8)

W
E

t
R

I
V

t
e

t
o

r
e

r
g

t
a

r
t

(
C

)

(
C

)

I
G

t
e

.

T

r
o

t
i
v

f

t
h

r
e

r
g

i
s

f
t
e

r

t
R

f
r
o

t
h

i
s

i
n

t
.

r
e

f

a

t
h

r

a

t
i
v

t
e

i
s

f
r
o

t
h

i
s

i
n

t
.

t

b

r
s

t

r
e

/
w

r
i
t
e

i
t
h

t
o

r
e

r
g

,

C

i
n

t
e

r
r
u

t

o

f

t
h

i
s

i
l
l
e

l
.

(
C

)

(
C

)

,

C

/
A

(
A

,
A

)

[
1

:
0

]

Preliminary

64M DDR SGRAM

K4D623237M

W
E

t
R

t
e

t
o

r
e

r
g

t
a

r
t

W
R

I
T

I
V

I
G

t
e

.

T

r
o

t
i
v

f

t
h

r
e

r
g

i
s

f
t
e

r

t
R

f
r
o

t
h

i
s

i
n

t
.

r
e

/
w

r
i
t
e

f

a

t
h

r

a

t
i
v

t
e

i
s

f
r
o

t
h

i
s

i
n

t
.

t

b

r
s

t

r
e

/
w

r
i
t
e

i
t
h

t
o

r
e

r
g

,

C

i
n

t
e

r
r
u

t

o

f

t
h

i
s

i
l
l
e

l
.

t
R

,

C

/
A

(
A

,
A

)

[
1

:
0

]

Auto Precharge after WRITE Burst (@BL=4)

Preliminary

64M DDR SGRAM

K4D623237M

Write Interrupted by Precharge & DM (@BL=8)

W
E

W
R

I
T

W
R

I
T

W
R

I
T

t
R

t
C

I
G

,

C

/
A

(
A

,
A

)

[
1

:
0

]

Preliminary

64M DDR SGRAM

K4D623237M

Read Interrupted by Precharge (@BL=8)

W
E

(
C

)

(
C

)

.
5

l
i
d

I
G

(
C

)

(
C

)

.
5

l
i
d

,

C

/
A

(
A

,
A

)

[
1

:
0

]

Preliminary

64M DDR SGRAM

K4D623237M

Power up Sequence & Auto Refresh(CBR)

W
E

I
G

,

C

/
A

(
A

,
A

)

i
g

-
Z

r
e

r
g

t

A

t
o

f
r
e

i
s

t
e

r

S

i
g

-
Z

l
l

B

t
o

f
r
e

i
n

i
m

f

2

f
r
e

l
e

r
e

i
r
e

I
n

t
s

t

b

t
a

l
e

f
o

r

2

[
1

:
0

]

I
G

Preliminary

64M DDR SGRAM

K4D623237M

Block Write cycle (with Auto Precharge)

W
E

I
G

,

C

/
A

(
A

,
A

)

t
i
v

(
A

-
B

)

l
o

W
r
i
t
e

(
A

-
B

)

l
o

W
r
i
t
e

i
t
h

t
o

r
e

r
g

(
A

-
B

)

*
N

t
e

.

A

t

B

l
o

W
r
i
t
e

,

C

r
e

i
g

r
e

[
1

:
0

]

W
C

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: K4D623237M-QC70

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: K4D623237M-QC70