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Электронный компонент: K4D623238F-QC40

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- 1 -
Rev. 1.3 (Jul. 2002)
64M DDR SDRAM
K4D623238F-QC
64Mbit DDR SDRAM
Revision 1.3
July 2002
512K x 32Bit x 4 Banks
with Bi-directional Data Strobe and DLL
Double Data Rate Synchronous DRAM
Samsung Electronics reserves the right to change products or specification without notice.
(100-Pin TQFP)
- 2 -
Rev. 1.3 (Jul. 2002)
64M DDR SDRAM
K4D623238F-QC
Revision History
Revision 1.3 (July 18, 2002)
Changed power dissipation from 2.0W to 1.8W
Revision 1.2 (June 17, 2002)
Removed K4D623238F-QC55 from the spec
183/166MHz were supported in K4D623238F-QC50
Revision 1.1 (May 24, 2002)
Removed K4D623238F-QC45/60 from the spec
Revision 1.0 (May 20, 2002)
Defined DC Specification
Typo corrected
Revision 0.0 (April 23, 2002)
- Target Spec
Defined Target Specification
- 3 -
Rev. 1.3 (Jul. 2002)
64M DDR SDRAM
K4D623238F-QC
2.5V + 5% power supply for device operation
2.5V + 5% power supply for I/O interface
SSTL_2 compatible inputs/outputs
4 banks operation
MRS cycle with address key programs
-. Read latency 3,4 (clock)
-. Burst length (2, 4, 8 and Full page)
-. Burst type (sequential & interleave)
Full page burst length for sequential burst type only
Start address of the full page burst should be even
All inputs except data & DM are sampled at the positive
going edge of the system clock
Differential clock input
No Write Interrupted by Read Function
GENERAL DESCRIPTION
FEATURES
Data I/O transactions on both edges of Data strobe
DLL aligns DQ and DQS transitions with Clock transition
Edge aligned data & data strobe output
Center aligned data & data strobe input
DM for write masking only
Auto & Self refresh
16ms refresh period (2K cycle)
100-Pin TQFP package
Maximum clock frequency up to 250MHz
Maximum data rate up to 500Mbps/pin
512K x 32Bit x 4 Banks Double Data Rate Synchronous DRAM
with Bi-directional Data Strobe and DLL
ORDERING INFORMATION
Part NO.
Max Freq.
Max Data Rate
Interface
Package
K4D623238F-QC40
250MHz
500Mbps/pin
SSTL_2
100 TQFP
K4D623238F-QC50
200MHz
400Mbps/pin
The K4D623238F is 67,108,864 bits of hyper synchronous data rate Dynamic RAM organized as 4 x 524,288 words by 32
bits, fabricated with SAMSUNG
's
high performance CMOS technology. Synchronous features with Data Strobe allow
extremely high performance up to
2.0GB/s
/chip. I/O transactions are possible on both edges of the clock cycle. Range of
operating frequencies, programmable burst length and programmable latencies allow the device to be useful for a variety
of high performance memory system applications.
FOR 512K x 32Bit x 4 Bank DDR SDRAM
- 4 -
Rev. 1.3 (Jul. 2002)
64M DDR SDRAM
K4D623238F-QC
PIN CONFIGURATION
(Top View)
PIN DESCRIPTION
CK,CK
Differential Clock Input
BA
0
, BA
1
Bank Select Address
CKE
Clock Enable
A
0
~A
10
Address Input
CS
Chip Select
DQ
0
~ DQ
31
Data Input/Output
RAS
Row Address Strobe
V
DD
Power
CAS
Column Address Strobe
V
SS
Ground
WE
Write Enable
V
DDQ
Power for DQ
'
s
DQS
Data Strobe
V
SSQ
Ground for DQ
'
s
DM
Data Mask
NC
No Connection
RFU
Reserved for Future Use
MCL
Must Connect Low
DQ29
VSSQ
DQ30
DQ31
VSS
VDDQ
N.C
N.C
N.C
N.C
N.C
VSSQ
RFU
DQS
VDDQ
VDD
DQ0
DQ1
VSSQ
DQ2
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
DQ3
VDDQ
DQ4
DQ5
V
SSQ
DQ6
DQ7
VDDQ
DQ
1
6
DQ
1
7
V
SSQ
DQ
1
8
DQ
1
9
VDDQ
VDD
VSS
DQ
2
0
DQ
2
1
V
SSQ
DQ
2
2
DQ
2
3
VDDQ
DM
0
DM
2
WE
CAS
RAS
CS
BA0
BA1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
A7
A6
A5
A4
VSS
A9
N.C
N.C
N.C
N.C
N.C
N.C
N.C
RFU
A10
VDD
A3
A2
A1
A0
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
100 Pin TQFP
20 x 14 mm2
0.65mm pin Pitch
DQ2
8
VDDQ
DQ2
7
DQ2
6
VS
SQ
DQ2
5
DQ2
4
VDDQ
DQ1
5
DQ1
4
VS
SQ
DQ1
3
DQ1
2
VDDQ
VS
S
VDD
DQ1
1
DQ1
0
VS
SQ
DQ9
DQ8
VDDQ
VRE
F
DM
3
DM
1
CK
CK
CKE
MC
L
A8
(
AP)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
- 5 -
Rev. 1.3 (Jul. 2002)
64M DDR SDRAM
K4D623238F-QC
INPUT/OUTPUT FUNCTIONAL DESCRIPTION
*1 : The timing reference point for the differential clocking is the cross point of CK and CK.
For any applications using the single ended clocking, apply V
REF
to CK pin.
Symbol
Type
Function
CK, CK*1
Input
The differential system clock Input.
All of the inputs are sampled on the rising edge of the clock except
DQ
'
s and DM
'
s that are sampled on both edges of the DQS.
CKE
Input
Activates the CK signal when high and deactivates the CK signal
when low. By deactivating the clock, CKE low indicates the Power
down mode or Self refresh mode.
CS
Input
CS enables the command decoder when low and disabled the com-
mand decoder when high. When the command decoder is disabled,
new commands are ignored but previous operations continue.
RAS
Input
Latches row addresses on the positive going edge of the CK with
RAS low. Enables row access & precharge.
CAS
Input
Latches column addresses on the positive going edge of the CK with
CAS low. Enables column access.
WE
Input
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
DQS
Input/Output
Data input and output are synchronized with both edge of DQS.
DM
0
~ DM
3
Input
Data In mask. Data In is masked by DM Latency=0 when DM is high
in burst write. DM
0
for DQ
0
~ DQ
7,
DM
1
for DQ
8
~ DQ
15,
DM
2
for
DQ
16
~ DQ
23,
DM
3
for DQ
24
~ DQ
31.
DQ
0
~ DQ
31
Input/Output
Data inputs/Outputs are multiplexed on the same pins.
BA
0
, BA
1
Input
Selects which bank is to be active.
A
0
~ A
10
Input
Row/Column addresses are multiplexed on the same pins.
Row addresses : RA
0
~ RA
10
, Column addresses : CA
0
~ CA
7
.
Column address CA
8
is used for auto precharge.
V
DD
/V
SS
Power Supply
Power and ground for the input buffers and core logic.
V
DDQ
/V
SSQ
Power Supply
Isolated power supply and ground for the output buffers to provide
improved noise immunity.
V
REF
Power Supply
Reference voltage for inputs, used for SSTL interface.
NC/RFU
No connection/
Reserved for future use
This pin is recommended to be left "No connection" on the device
MCL
Must Connect Low
Must connect low
- 6 -
Rev. 1.3 (Jul. 2002)
64M DDR SDRAM
K4D623238F-QC
BLOCK DIAGRAM
(512Kbit x 32I/O x 4 Bank)
Bank Select
Timing Register
Ad
dre
s
s
R
egi
st
er
Refre
s
h
C
oun
ter
Ro
w
B
u
f
fe
r
R
o
w
D
ec
ode
r
Co
l
.
Bu
f
f
e
r
Data Input Register
Serial to parallel
512Kx32
512Kx32
512Kx32
512Kx32
Sen
s
e
A
M
P
2
-
bi
t
p
re
fetc
h
Ou
t
p
u
t
B
u
f
f
er
I/
O
C
o
n
tro
l
Column Decoder
Latency & Burst Length
Programming Register
St
r
o
b
e
G
en.
CK,CK
ADDR
LCKE
CK,CK
CKE
CS
RAS
CAS
WE
DMi
LDMi
CK,CK
LCAS
LRAS
LCBR
LWE
LWCBR
LR
AS
LC
B
R
CK, CK
64
64
32
32
LWE
LDMi
x32
DQi
Data Strobe
Intput Buffer
DLL
- 7 -
Rev. 1.3 (Jul. 2002)
64M DDR SDRAM
K4D623238F-QC
Power-Up Sequence
DDR SDRAMs must be powered up and initialized in a predefined manner to prevent undefined operations.
1. Apply power and keep CKE at low state (All other inputs may be undefined)
- Apply VDD before VDDQ .
- Apply VDDQ before VREF & VTT
2. Start clock and maintain stable condition for minimum 200us.
3. The minimum of 200us after stable power and clock(CK,CK ), apply NOP and take CKE to be high .
4. Issue precharge command for all banks of the device.
5. Issue a EMRS command to enable DLL
*1
6. Issue a MRS command to reset DLL. The additional 200 clock cycles are required to lock the DLL.
*
1,2
7. Issue precharge command for all banks of the device.
8. Issue at least 2 or more auto-refresh commands.
9. Issue a mode register set command with A8 to low to initialize the mode register.
*1 The additional 200cycles of clock input is required to lock the DLL after enabling DLL.
*2 Sequence of 6&7 is regardless of the order.
FUNCTIONAL DESCRIPTION
Power up & Initialization Sequence
Command
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
tRP
2 Clock min.
precharge
ALL Banks
2nd Auto
Refresh
Mode
Register Set
Any
Command
t
RFC
1st Auto
Refresh
t
RFC
EMRS
MRS
2 Clock min.
DLL Reset
~ ~
~ ~
~ ~
~ ~
~ ~
~ ~
precharge
ALL Banks
t
RP
CK
CK
Inputs must be
stable for 200us
~~
200 Clock min.
~ ~
2 Clock min.
- 8 -
Rev. 1.3 (Jul. 2002)
64M DDR SDRAM
K4D623238F-QC
The mode register stores the data for controlling the various operating modes of DDR SDRAM. It programs CAS latency,
addressing mode, burst length, test mode, DLL reset and various vendor specific options to make DDR SDRAM useful for
variety of different applications. The default value of the mode register is not defined, therefore the mode register must be
written after EMRS setting for proper operation. The mode register is written by asserting low on CS, RAS, CAS and
WE(The DDR SDRAM should be in active mode with CKE already high prior to writing into the mode register). The state of
address pins A
0
~ A
10
and BA
0
, BA
1
in the same cycle as CS, RAS, CAS and WE going low is written in the mode register.
Minimum two clock cycles are requested to complete the write operation in the mode register. The mode register contents
can be changed using the same command and clock cycle requirements during operation as long as all banks are in the
idle state. The mode register is divided into various fields depending on functionality. The burst length uses A
0
~ A
2
,
addressing mode uses A
3
, CAS latency(read latency from column address) uses A
4
~ A
6
. A
7
is used for test mode. A
8
is
used for DLL reset. A
7,
A
8
, BA
0
and BA
1
must be set to low for normal MRS operation. Refer to the table for specific codes
for various burst length, addressing modes and CAS latencies.
MODE REGISTER SET(MRS)
Address Bus
Mode Register
CAS Latency
A
6
A
5
A
4
Latency
0
0
0
Reserved
0
0
1
Reserved
0
1
0
Reserved
0
1
1
3
1
0
0
4
1
0
1
Reserved
1
1
0
Reserved
1
1
1
Reserved
Burst Length
A
2
A
1
A
0
Burst Type
Sequential
Interleave
0
0
0
Reserve
Reserve
0
0
1
2
2
0
1
0
4
4
0
1
1
8
8
1
0
0
Reserve
Reserve
1
0
1
Reserve
Reserve
1
1
0
Reserve
Reserve
1
1
1
Full page
Reserve
Burst Type
A
3
Type
0
Sequential
1
Interleave
* RFU(Reserved for future use)
should stay "0" during MRS
cycle.
MRS Cycle
Command
*1 : MRS can be issued only at all banks precharge state.
*2 : Minimum
t
RP
is required to issue MRS command.
CK, CK
Precharge
NOP
NOP
MRS
NOP
NOP
2
0
1
5
3
4
8
6
7
Any
NOP
All Banks
Command
t
RP
t
MRD
=2 t
CK
BA
1
BA
0
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
RFU
0
RFU
DLL
TM
CAS Latency
BT
Burst Length
BA
0
A
n
~ A
0
0
MRS
1
EMRS
DLL
A
8
DLL Reset
0
No
1
Yes
Test Mode
A
7
mode
0
Normal
1
Test
NOP
- 9 -
Rev. 1.3 (Jul. 2002)
64M DDR SDRAM
K4D623238F-QC
The extended mode register stores the data for enabling or disabling DLL and selecting output driver
strength. The default value of the extended mode register is not defined, therefore the extened mode register
must be written after power up for enabling or disabling DLL. The extended mode register is written by assert-
ing low on CS, RAS, CAS, WE and high on BA0(The DDR SDRAM should be in all bank precharge with CKE
already high prior to writing into the extended mode register). The state of address pins A0, A2 ~ A5, A7 ~ A10
and BA1 in the same cycle as CS, RAS, CAS and WE going low are written in the extended mode register. A1
and A6 are used for setting driver strength to normal, weak or matched impedance. Two clock cycles are
required to complete the write operation in the extended mode register. The mode register contents can be
changed using the same command and clock cycle requirements during operation as long as all banks are in
the idle state. A0 is used for DLL enable or disable. "High" on BA0 is used for EMRS. All the other address
pins except A0,A1,A6 and BA0 must be set to low for proper EMRS operation. Refer to the table for specific
codes.
A
0
DLL Enable
0
Enable
1
Disable
BA
0
A
n
~ A
0
0
MRS
1
EMRS
Figure 7. Extended Mode Register set
EXTENDED MODE REGISTER SET(EMRS)
Address Bus
Extended
BA
1
BA
0
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
RFU
1
RFU
D.I.C
RFU
D.I.C
DLL
Mode Register
* RFU(Reserved for future use)
should stay "0" during EMRS
cycle.
A
6
A
1
Output Driver Impedence Control
0
1
Weak
1
1
Matched
- 10 -
Rev. 1.3 (Jul. 2002)
64M DDR SDRAM
K4D623238F-QC
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
Note :
POWER & DC OPERATING CONDITIONS(SSTL_2 In/Out)
Recommended operating conditions(Voltage referenced to V
SS
=0V, T
A
=0 to 65
C)
Parameter
Symbol
Min
Typ
Max
Unit
Note
Device Supply voltage
V
DD
2.375
2.50
2.625
V
1
Output Supply voltage
V
DDQ
2.375
2.50
2.625
V
1
Reference voltage
V
REF
0.49*V
DDQ
-
0.51*V
DDQ
V
2
Termination voltage
Vtt
V
REF
-0.04
V
REF
V
REF
+0.04
V
3
Input logic high voltage
V
IH
V
REF
+0.15
-
V
DDQ
+0.30
V
4
Input logic low voltage
V
IL
-0.30
-
V
REF
-0.15
V
5
Output logic high voltage
V
OH
Vtt+0.76
-
-
V
I
OH
=-15.2mA
Output logic low voltage
V
OL
-
-
Vtt-0.76
V
I
OL
=+15.2mA
Input leakage current
I
IL
-5
-
5
uA
6
Output leakage current
I
OL
-5
-
5
uA
6
1. Under all conditions V
DDQ
must be less than or equal to V
DD
.
2. V
REF
is expected to equal 0.50*V
DDQ
of the transmitting device and to track variations in the DC level of the same. Peak to
peak noise on the V
REF
may not exceed + 2% of the DC value. Thus, from 0.50*V
DDQ
, V
REF
is allowed + 25mV for DC error
and an additional + 25mV for AC noise.
3. V
tt
of the transmitting device must track V
REF
of the receiving device.
4. V
IH
(max.)= V
DDQ
+1.5V for a pulse and it which can not be greater than 1/3 of the cycle rate.
5. V
IL
(mim.)= -1.5V for a pulse width and it can not be greater than 1/3 of the cycle rate.
6. For any pin under test input of 0V < V
IN
< V
DD
is acceptable. For all other pins that are not under test V
IN
=0V
Note :
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Value
Unit
Voltage on any pin relative to Vss
V
IN
, V
OUT
-0.5 ~ 3.6
V
Voltage on V
DD
supply relative to Vss
V
DD
-1.0 ~ 3.6
V
Voltage on V
DD
supply relative to Vss
V
DDQ
-0.5 ~ 3.6
V
Storage temperature
T
STG
-55 ~ +150
C
Power dissipation
P
D
1.8
W
Short circuit current
I
OS
50
mA
- 11 -
Rev. 1.3 (Jul. 2002)
64M DDR SDRAM
K4D623238F-QC
AC INPUT OPERATING CONDITIONS
Recommended operating conditions(Voltage referenced to V
SS
=0V, V
DD
/ V
DDQ
=2.5V+ 5%, T
A
=0 to 65
C)
Parameter
Symbol
Min
Typ
Max
Unit
Note
Input High (Logic 1) Voltage; DQ
V
IH
V
REF
+0.35
-
-
V
1
Input Low (Logic 0) Voltage; DQ
V
IL
-
-
V
REF
-0.35
V
2
Clock Input Differential Voltage ; CK and CK
V
ID
0.7
-
V
DDQ
+0.6
V
3
Clock Input Crossing Point Voltage ; CK and CK
V
IX
0.5*V
DDQ
-0.2
-
0.5*V
DDQ
+0.2
V
4
1. V
IH
(Max) = 4.2V. The overshoot voltage duration is < 3ns at VDD
2. V
IL
(Min) = -1.5V. The undershoot voltage duration is < 3ns at VSS
3. V
ID
is the magnitude of the difference between the input level on CK and the input level on CK
4. The value of V
IX
is expected to equal 0.5*V
DDQ
of the transmitting device and must track variations in the DC level of the same
Note :
DC CHARACTERISTICS
Note : 1. Measured with outputs open.
2. Refresh period is 16ms.
Parameter
Symbol
Test Condition
Version
Unit
Note
-40
-50
Operating Current
(One Bank Active)
I
CC1
Burst Lenth=2
t
RC
t
RC
(min)
I
OL
=0mA,
t
CC
=
t
CC
(min)
245
215
mA
1
Precharge Standby Current
in Power-down mode
I
CC2
P
CKE
V
IL
(max),
t
CC
=
t
CC
(min)
70
60
mA
Precharge Standby Current
in Non Power-down mode
I
CC2
N
CKE
V
IH
(min), CS
V
IH
(min),
t
CC
=
t
CC
(min)
100
90
mA
Active Standby Current
power-down mode
I
CC3
P
CKE
V
IL
(max),
t
CC
=
t
CC
(min)
100
80
mA
Active Standby Current in
in Non Power-down mode
I
CC3
N
CKE
VIH(min), CS
VIH(min),
t
CC
=
t
CC
(min)
175
150
mA
Operating Current
( Burst Mode)
I
CC4
I
OL
=0mA ,
t
CC
=
t
CC
(min),
Page Burst, All Banks activated.
630
530
mA
Refresh Current
I
CC5
t
RC
t
RFC
(min)
250
230
mA
2
Self Refresh Current
I
CC6
CKE
0.2V
3
mA
Recommended operating conditions Unless Otherwise Noted, T
A
=0 to 65
C)
- 12 -
Rev. 1.3 (Jul. 2002)
64M DDR SDRAM
K4D623238F-QC
AC OPERATING TEST CONDITIONS
(V
DD
=2.5V0.125V, T
A
= 0 to 65
C)
Parameter
Value
Unit
Note
Input reference voltage for CK(for single ended)
0.50*V
DDQ
V
CK and CK signal maximum peak swing
1.5
V
CK signal minimum slew rate
1.0
V/ns
Input Levels(V
IH
/V
IL
)
V
REF
+0.35/V
REF
-0.35
V
Input timing measurement reference level
V
REF
V
Output timing measurement reference level
V
tt
V
Output load condition
See Fig.1
R
T
=50
Output
C
LOAD
=30pF
(Fig. 1) Output Load Circuit
Z0=50
V
REF
=0.5*V
DDQ
V
tt
=0.5*V
DDQ
DECOUPLING CAPACITANCE GUIDE LINE
Recommended decoupling capacitance added to power line at board.
Parameter
Symbol
Value
Unit
Decoupling Capacitance between V
DD
and V
SS
C
DC1
0.1 + 0.01
uF
Decoupling Capacitance between V
DDQ
and V
SSQ
C
DC2
0.1 + 0.01
uF
1. VDD and VDDQ pins are separated each other.
All VDD pins are connected in chip. All VDDQ pins are connected in chip.
2. VSS and VSSQ pins are separated each other
All VSS pins are connected in chip. All VSSQ pins are connected in chip.
Note :
CAPACITANCE
(V
DD
=2.5V, T
A
= 25
C, f=1MHz)
Parameter
Symbol
Min
Max
Unit
Input capacitance( CK, CK )
C
IN1
1.0
5.0
pF
Input capacitance(A
0
~A
10
, BA
0
~BA
1
)
C
IN2
1.0
4.0
pF
Input capacitance
( CKE, CS, RAS,CAS, WE )
C
IN3
1.0
4.0
pF
Data & DQS input/output capacitance(DQ
0
~DQ
31
)
C
OUT
1.0
6.0
pF
Input capacitance(DM0 ~ DM3)
C
IN4
1.0
6.0
pF
- 13 -
Rev. 1.3 (Jul. 2002)
64M DDR SDRAM
K4D623238F-QC
AC CHARACTERISTICS
Parameter
Symbol
-40
-50
Unit
Note
Min
Max
Min
Max
CK cycle time
CL=3
t
CK
-
8
5.0
10
ns
CL=4
4.0
ns
CK high level width
t
CH
0.45
0.55
0.45
0.55
tCK
CK low level width
t
CL
0.45
0.55
0.45
0.55
tCK
DQS out access time from CK
t
DQSCK
-0.6
0.6
-0.7
0.7
ns
Output access time from CK
t
AC
-0.6
0.6
-0.7
0.7
ns
Data strobe edge to Dout edge
t
DQSQ
-
0.4
-
0.45
ns
1
Read preamble
t
RPRE
0.9
1.1
0.9
1.1
tCK
Read postamble
t
RPST
0.4
0.6
0.4
0.6
tCK
CK to valid DQS-in
t
DQSS
0.85
1.15
0.8
1.2
tCK
DQS-In setup time
t
WPRES
0
-
0
-
ns
DQS-in hold time
t
WPREH
0.35
-
0.25
-
tCK
DQS write postamble
t
WPST
0.4
0.6
0.4
0.6
tCK
DQS-In high level width
t
DQSH
0.4
0.6
0.4
0.6
tCK
DQS-In low level width
t
DQSL
0.4
0.6
0.4
0.6
tCK
Address and Control input setup
t
IS
0.9
-
1.0
-
ns
Address and Control input hold
t
IH
0.9
-
1.0
-
ns
DQ and DM setup time to DQS
t
DS
0.4
-
0.45
-
ns
DQ and DM hold time to DQS
t
DH
0.4
-
0.45
-
ns
Clock half period
t
HP
tCLmin
or
tCHmin
-
tCLmin
or
tCHmin
-
ns
1
Data output hold time from DQS
t
QH
tHP-0.4
-
tHP-0.45
-
ns
1
1
3
4
6
7
tCL
tCK
Hi-Z
Hi-Z
CK, CK
DQS
DQ
CS
DM
2
5
tIS
tIH
8
tDS tDH
0
1
tRPST
tRPRE
Db0
Db1
tDQSS
tDQSH
tCH
Da1
Da2
tWPST
COMMAND
READA
WRITEB
tDQSQ
t
WPRES
t
WPREH
tDQSCK
tAC
Simplified Timing @ BL=2, CL=3
- 14 -
Rev. 1.3 (Jul. 2002)
64M DDR SDRAM
K4D623238F-QC
Note 1 :
- The JEDEC DDR specification currently defines the output data valid window(tDV) as the time period when the data
strobe and all data associated with that data strobe are coincidentally valid.
- The previously used definition of tDV(=0.35tCK) artificially penalizes system timing budgets by assuming the worst case
output vaild window even then the clock duty cycle applied to the device is better than 45/55%
- A new AC timing term, tQH which stands for data output hold time from DQS is difined to account for clock duty cycle
variation and replaces tDV
- tQHmin = tHP-X where
. tHP=Minimum half clock period for any given cycle and is defined by clock high or clock low time(tCH,tCL)
. X=A frequency dependent timing allowance account for tDQSQmax
tQH Timing (CL3, BL2)
1
3
4
tHP
CK, CK
DQS
DQ
CS
2
5
0
1
COMMAND
READA
tQH
Da0
tDQSQ(max)
tDQSQ(max)
Da1
- 15 -
Rev. 1.3 (Jul. 2002)
64M DDR SDRAM
K4D623238F-QC
AC CHARACTERISTICS (I)
Note : 1. For normal write operation, even numbers of Din are to be written inside DRAM
Parameter
Symbol
-40
-50
Unit
Note
Min
Max
Min
Max
Row cycle time
tRC
15
-
12
-
tCK
Refresh row cycle time
tRFC
17
-
14
-
tCK
Row active time
tRAS
10
100K
8
100K
tCK
RAS to CAS delay for Read
tRCDRD
5
-
4
-
tCK
RAS to CAS delay for Write
tRCDWR
3
2
tCK
Row precharge time
tRP
5
-
4
-
tCK
Row active to Row active
tRRD
3
-
2
-
tCK
Last data in to Row precharge
tWR
3
-
2
-
tCK
1
Last data in to Read command
tCDLR
2
-
2
-
tCK
1
Col. address to Col. address
tCCD
1
-
1
-
tCK
Mode register set cycle time
tMRD
2
-
2
-
tCK
Auto precharge write recovery + Precharge
tDAL
8
-
6
-
tCK
Exit self refresh to read command
tXSR
200
-
200
-
tCK
Power down exit time
tPDEX
1tCK+tIS
-
1tCK+tIS
-
ns
Refresh interval time
tREF
7.8
-
7.8
-
us
- 16 -
Rev. 1.3 (Jul. 2002)
64M DDR SDRAM
K4D623238F-QC
AC CHARACTERISTICS (II)
*183/166MHz were supported in K4D623238F-QC50
K4D623238F-QC40
Frequency
Cas Latency
tRC
tRFC
tRAS
tRCDRD
tRCDWR
tRP
tRRD
tDAL
Unit
250MHz ( 4.0ns )
4
15
17
10
5
3
5
3
8
tCK
200MHz ( 5.0ns )
3
12
14
8
4
2
4
2
6
tCK
K4D623238F-QC50
Frequency
Cas Latency
tRC
tRFC
tRAS
tRCDRD
tRCDWR
tRP
tRRD
tDAL
Unit
200MHz ( 5.0ns )
3
12
14
8
4
2
4
2
6
tCK
183MHz ( 5.5ns )
3
12
14
8
4
2
4
2
6
tCK
166MHz ( 6.0ns )
3
10
12
7
3
2
3
2
5
tCK
- 17 -
Rev. 1.3 (Jul. 2002)
64M DDR SDRAM
K4D623238F-QC
Simplified Timing(2) @ BL=4
0
1
2
3
4
5
6
7
8
BAa
Ra
Ra
tRCD
ACTIVEA
ACTIVEB WRITEA
WRITEB
13
14
15
16
17
18
19
20
21
BAa
BAb
Ca
Cb
BAa
Ca
9
10
11
12
PRECH
BAa
22
Ra
Normal Write Burst
(@ BL=4)
Multi Bank Interleaving Write Burst
(@ BL=4)
BAa
Ra
Ra
BAb
Rb
Rb
tRAS
tRC
tRP
tRRD
COMMAND
DQS
DQ
WE
DM
CK, CK
A8/AP
ADDR
(A0~A7,
BA[1:0]
A9,A10)
ACTIVEA
WRITEA
Da0 Da1 Da2 Da3
Db0 Db1
Db3
Da0 Da1 Da2 Da3
Db2
- 18 -
Rev. 1.3 (Jul. 2002)
64M DDR SDRAM
K4D623238F-QC
0.825
0
.
575
0.65
0.13 MAX
PACKAGE DIMENSIONS (TQFP)
Dimensions in Millimeters
0.10 MAX
0 ~ 7
17.20
0.20
14.00
0.10
23.20
0.20
1.00
0.10
1.20 MAX *
0.05 MIN
0.80
0.20
#1
0.09~0.20
#100
0.30
0.08
20.00
0.10